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PPCDisassembler.cpp
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1//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "llvm/MC/MCDecoder.h"
14#include "llvm/MC/MCInst.h"
18#include "llvm/Support/Endian.h"
19
20using namespace llvm;
21using namespace llvm::MCD;
22
24
25#define DEBUG_TYPE "ppc-disassembler"
26
28
29namespace {
30class PPCDisassembler : public MCDisassembler {
31 bool IsLittleEndian;
32
33public:
34 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
35 bool IsLittleEndian)
36 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
37
38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39 ArrayRef<uint8_t> Bytes, uint64_t Address,
40 raw_ostream &CStream) const override;
41};
42} // end anonymous namespace
43
45 const MCSubtargetInfo &STI,
46 MCContext &Ctx) {
47 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
48}
49
51 const MCSubtargetInfo &STI,
52 MCContext &Ctx) {
53 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
54}
55
68
69static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
70 uint64_t /*Address*/,
71 const MCDisassembler * /*Decoder*/) {
74}
75
76static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
77 uint64_t /*Address*/,
78 const MCDisassembler * /*Decoder*/) {
79 int32_t Offset = SignExtend32<24>(Imm);
82}
83
84// FIXME: These can be generated by TableGen from the existing register
85// encoding values!
86
87template <std::size_t N>
89 const MCPhysReg (&Regs)[N]) {
90 if (RegNo >= N)
92 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
94}
95
97 uint64_t Address,
98 const MCDisassembler *Decoder) {
99 return decodeRegisterClass(Inst, RegNo, CRRegs);
100}
101
103 uint64_t Address,
104 const MCDisassembler *Decoder) {
105 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
106}
107
109 uint64_t Address,
110 const MCDisassembler *Decoder) {
111 return decodeRegisterClass(Inst, RegNo, FRegs);
112}
113
115 uint64_t Address,
116 const MCDisassembler *Decoder) {
117 return decodeRegisterClass(Inst, RegNo, FRegs);
118}
119
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 if (RegNo > 30 || (RegNo & 1))
125 return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
126}
127
129 uint64_t Address,
130 const MCDisassembler *Decoder) {
131 return decodeRegisterClass(Inst, RegNo, VFRegs);
132}
133
135 uint64_t Address,
136 const MCDisassembler *Decoder) {
137 return decodeRegisterClass(Inst, RegNo, VRegs);
138}
139
141 uint64_t Address,
142 const MCDisassembler *Decoder) {
143 return decodeRegisterClass(Inst, RegNo, VSRegs);
144}
145
147 uint64_t Address,
148 const MCDisassembler *Decoder) {
149 return decodeRegisterClass(Inst, RegNo, VSFRegs);
150}
151
153 uint64_t Address,
154 const MCDisassembler *Decoder) {
155 return decodeRegisterClass(Inst, RegNo, VSSRegs);
156}
157
159 uint64_t Address,
160 const MCDisassembler *Decoder) {
161 return decodeRegisterClass(Inst, RegNo, RRegs);
162}
163
164static DecodeStatus
166 const MCDisassembler *Decoder) {
167 return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
168}
169
171 uint64_t Address,
172 const MCDisassembler *Decoder) {
173 return decodeRegisterClass(Inst, RegNo, XRegs);
174}
175
177 uint64_t Address,
178 const MCDisassembler *Decoder) {
179 return decodeRegisterClass(Inst, RegNo, XRegs);
180}
181
182static DecodeStatus
184 const MCDisassembler *Decoder) {
185 return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
186}
187
189 uint64_t Address,
190 const MCDisassembler *Decoder) {
191 return decodeRegisterClass(Inst, RegNo, SPERegs);
192}
193
195 uint64_t Address,
196 const MCDisassembler *Decoder) {
197 return decodeRegisterClass(Inst, RegNo, ACCRegs);
198}
199
201 uint64_t Address,
202 const void *Decoder) {
203 return decodeRegisterClass(Inst, RegNo, WACCRegs);
204}
205
207 uint64_t Address,
208 const void *Decoder) {
209 return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
210}
211
212// TODO: Make this function static when the register class is used by a new
213// instruction.
215 uint64_t Address,
216 const void *Decoder) {
217 return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
218}
219
221 uint64_t Address,
222 const void *Decoder) {
223 return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
224}
225
227 uint64_t Address,
228 const void *Decoder) {
229 return decodeRegisterClass(Inst, RegNo, DMRRegs);
230}
231
232// TODO: Make this function static when the register class is used by a new
233// instruction.
235 uint64_t Address, const void *Decoder) {
236 return decodeRegisterClass(Inst, RegNo, DMRpRegs);
237}
238
240 uint64_t Address,
241 const MCDisassembler *Decoder) {
242 return decodeRegisterClass(Inst, RegNo, VSRpRegs);
243}
244
245#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
246#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
247
248template <unsigned N>
250 int64_t Address,
251 const MCDisassembler *Decoder) {
252 if (!isUInt<N>(Imm))
256}
257
258template <unsigned N>
260 int64_t Address,
261 const MCDisassembler *Decoder) {
262 if (!isUInt<N>(Imm))
266}
267
269 int64_t Address,
270 const MCDisassembler *Decoder) {
271 if (Imm != 0)
275}
276
278 uint64_t Address,
279 const MCDisassembler *Decoder) {
280 if (RegNo & 1)
282 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
284}
285
287 int64_t Address,
288 const MCDisassembler *Decoder) {
289 // The rix displacement is an immediate shifted by 2
292}
293
295 int64_t Address,
296 const MCDisassembler *Decoder) {
297 // Decode the disp field for a hash store or hash check operation.
298 // The field is composed of an immediate value that is 6 bits
299 // and covers the range -8 to -512. The immediate is always negative and 2s
300 // complement which is why we sign extend a 7 bit value.
301 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
302
305}
306
308 int64_t Address,
309 const MCDisassembler *Decoder) {
310 // The rix16 displacement has 12-bits which are shifted by 4.
313}
314
316 int64_t Address,
317 const MCDisassembler *Decoder) {
318 // Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.
319
320 uint64_t Disp = Imm & 0x1F;
321
322 Inst.addOperand(MCOperand::createImm(Disp << 3));
324}
325
327 int64_t Address,
328 const MCDisassembler *Decoder) {
329 // Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.
330
331 uint64_t Disp = Imm & 0x1F;
332
333 Inst.addOperand(MCOperand::createImm(Disp << 2));
335}
336
338 int64_t Address,
339 const MCDisassembler *Decoder) {
340 // Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.
341
342 uint64_t Disp = Imm & 0x1F;
343 Inst.addOperand(MCOperand::createImm(Disp << 1));
345}
346
348 int64_t Address,
349 const MCDisassembler *Decoder) {
350 // The cr bit encoding is 0x80 >> cr_reg_num.
351
352 unsigned Zeros = llvm::countr_zero(Imm);
353 if (Zeros >= 8)
355
356 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
358}
359
360#include "PPCGenDisassemblerTables.inc"
361
362DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
363 ArrayRef<uint8_t> Bytes,
364 uint64_t Address,
365 raw_ostream &CS) const {
366 auto *ReadFunc = IsLittleEndian ? support::endian::read32le
368
369 // If this is an 8-byte prefixed instruction, handle it here.
370 // Note: prefixed instructions aren't technically 8-byte entities - the prefix
371 // appears in memory at an address 4 bytes prior to that of the base
372 // instruction regardless of endianness. So we read the two pieces and
373 // rebuild the 8-byte instruction.
374 // TODO: In this function we call decodeInstruction several times with
375 // different decoder tables. It may be possible to only call once by
376 // looking at the top 6 bits of the instruction.
377 if (STI.hasFeature(PPC::FeaturePrefixInstrs) && Bytes.size() >= 8) {
378 uint32_t Prefix = ReadFunc(Bytes.data());
379 uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
380 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
381 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
382 this, STI);
383 if (result != MCDisassembler::Fail) {
384 Size = 8;
385 return result;
386 }
387 }
388
389 // Get the four bytes of the instruction.
390 Size = 4;
391 if (Bytes.size() < 4) {
392 Size = 0;
394 }
395
396 // Read the instruction in the proper endianness.
397 uint64_t Inst = ReadFunc(Bytes.data());
398
399 if (STI.hasFeature(PPC::FeatureSPE)) {
400 DecodeStatus result =
401 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
402 if (result != MCDisassembler::Fail)
403 return result;
404 }
405
406 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
407}
MCDisassembler::DecodeStatus DecodeStatus
#define LLVM_ABI
Definition Compiler.h:213
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
IRTranslator LLVM IR MI
#define T
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg(&Regs)[N])
static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDispSPE4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler()
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDispRIHashOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeDispSPE2Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
static DecodeStatus decodeDispSPE8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeDispRIX16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeDispRIXOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
#define DEFINE_PPC_REGCLASSES
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
const T * data() const
Definition ArrayRef.h:144
Context object for machine code objects.
Definition MCContext.h:83
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
void addOperand(const MCOperand Op)
Definition MCInst.h:215
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint32_t read32be(const void *P)
Definition Endian.h:437
uint32_t read32le(const void *P)
Definition Endian.h:428
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:477
Target & getThePPC64LETarget()
Target & getThePPC32Target()
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition bit.h:186
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:198
Target & getThePPC64Target()
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
Definition MathExtras.h:565
Target & getThePPC32LETarget()
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:583
#define N
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.