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RISCVDisassembler.cpp
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1//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "TargetInfo/RISCVTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Endian.h"
27
28using namespace llvm;
29using namespace llvm::MCD;
30
31#define DEBUG_TYPE "riscv-disassembler"
32
33typedef MCDisassembler::DecodeStatus DecodeStatus;
34
35namespace {
36class RISCVDisassembler : public MCDisassembler {
37 std::unique_ptr<MCInstrInfo const> const MCII;
38
39public:
40 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCInstrInfo const *MCII)
42 : MCDisassembler(STI, Ctx), MCII(MCII) {}
43
44 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
45 ArrayRef<uint8_t> Bytes, uint64_t Address,
46 raw_ostream &CStream) const override;
47
48private:
49 DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
50 ArrayRef<uint8_t> Bytes, uint64_t Address,
51 raw_ostream &CStream) const;
52
53 DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
54 ArrayRef<uint8_t> Bytes, uint64_t Address,
55 raw_ostream &CStream) const;
56 DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream) const;
59};
60} // end anonymous namespace
61
62static MCDisassembler *createRISCVDisassembler(const Target &T,
63 const MCSubtargetInfo &STI,
64 MCContext &Ctx) {
65 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
66}
67
68extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
80
81static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
82 uint64_t Address,
83 const MCDisassembler *Decoder) {
84 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
85
86 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
87 return MCDisassembler::Fail;
88
89 MCRegister Reg = RISCV::X0 + RegNo;
90 Inst.addOperand(MCOperand::createReg(Reg));
91 return MCDisassembler::Success;
92}
93
94static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo,
95 uint64_t Address,
96 const MCDisassembler *Decoder) {
97 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
98
99 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
100 return MCDisassembler::Fail;
101
102 MCRegister Reg = RISCV::X0_H + RegNo;
103 Inst.addOperand(MCOperand::createReg(Reg));
104 return MCDisassembler::Success;
105}
106
107static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo,
108 uint64_t Address,
109 const MCDisassembler *Decoder) {
110 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
111
112 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
113 return MCDisassembler::Fail;
114
115 MCRegister Reg = RISCV::X0_W + RegNo;
116 Inst.addOperand(MCOperand::createReg(Reg));
117 return MCDisassembler::Success;
118}
119
120static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 MCRegister Reg = RISCV::X0 + RegNo;
124 if (Reg != RISCV::X1 && Reg != RISCV::X5)
125 return MCDisassembler::Fail;
126
127 Inst.addOperand(MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
129}
130
131static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 32)
135 return MCDisassembler::Fail;
136
137 MCRegister Reg = RISCV::F0_H + RegNo;
138 Inst.addOperand(MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 32)
146 return MCDisassembler::Fail;
147
148 MCRegister Reg = RISCV::F0_F + RegNo;
149 Inst.addOperand(MCOperand::createReg(Reg));
150 return MCDisassembler::Success;
151}
152
153static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 8) {
157 return MCDisassembler::Fail;
158 }
159 MCRegister Reg = RISCV::F8_F + RegNo;
160 Inst.addOperand(MCOperand::createReg(Reg));
161 return MCDisassembler::Success;
162}
163
164static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo >= 32)
168 return MCDisassembler::Fail;
169
170 MCRegister Reg = RISCV::F0_D + RegNo;
171 Inst.addOperand(MCOperand::createReg(Reg));
172 return MCDisassembler::Success;
173}
174
175static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo >= 8) {
179 return MCDisassembler::Fail;
180 }
181 MCRegister Reg = RISCV::F8_D + RegNo;
182 Inst.addOperand(MCOperand::createReg(Reg));
183 return MCDisassembler::Success;
184}
185
186static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo >= 32)
190 return MCDisassembler::Fail;
191
192 MCRegister Reg = RISCV::F0_Q + RegNo;
193 Inst.addOperand(MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195}
196
197static DecodeStatus DecodeGPRX1RegisterClass(MCInst &Inst,
198 const MCDisassembler *Decoder) {
199 Inst.addOperand(MCOperand::createReg(RISCV::X1));
200 return MCDisassembler::Success;
201}
202
203static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
204 const MCDisassembler *Decoder) {
205 Inst.addOperand(MCOperand::createReg(RISCV::X2));
206 return MCDisassembler::Success;
207}
208
209static DecodeStatus DecodeGPRX5RegisterClass(MCInst &Inst,
210 const MCDisassembler *Decoder) {
211 Inst.addOperand(MCOperand::createReg(RISCV::X5));
212 return MCDisassembler::Success;
213}
214
215static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
216 uint64_t Address,
217 const MCDisassembler *Decoder) {
218 if (RegNo == 0)
219 return MCDisassembler::Fail;
220
221 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
222}
223
224static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo,
225 uint32_t Address,
226 const MCDisassembler *Decoder) {
227 if (RegNo == 2)
228 return MCDisassembler::Fail;
229
230 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
231}
232
233static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo,
234 uint64_t Address,
235 const MCDisassembler *Decoder) {
236 if (RegNo == 31) {
237 return MCDisassembler::Fail;
238 }
239
240 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
241}
242
243static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
244 uint64_t Address,
245 const MCDisassembler *Decoder) {
246 if (RegNo >= 8)
247 return MCDisassembler::Fail;
248
249 MCRegister Reg = RISCV::X8 + RegNo;
250 Inst.addOperand(MCOperand::createReg(Reg));
251 return MCDisassembler::Success;
252}
253
254static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
255 uint64_t Address,
256 const MCDisassembler *Decoder) {
257 if (RegNo >= 32 || RegNo % 2)
258 return MCDisassembler::Fail;
259
260 const RISCVDisassembler *Dis =
261 static_cast<const RISCVDisassembler *>(Decoder);
262 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
263 MCRegister Reg = RI->getMatchingSuperReg(
264 RISCV::X0 + RegNo, RISCV::sub_gpr_even,
265 &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
266 Inst.addOperand(MCOperand::createReg(Reg));
267 return MCDisassembler::Success;
268}
269
270static DecodeStatus
271DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address,
272 const MCDisassembler *Decoder) {
273 if (RegNo == 0)
274 return MCDisassembler::Fail;
275
276 return DecodeGPRPairRegisterClass(Inst, RegNo, Address, Decoder);
277}
278
279static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo,
280 uint64_t Address,
281 const MCDisassembler *Decoder) {
282 if (RegNo >= 8 || RegNo % 2)
283 return MCDisassembler::Fail;
284
285 const RISCVDisassembler *Dis =
286 static_cast<const RISCVDisassembler *>(Decoder);
287 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
288 MCRegister Reg = RI->getMatchingSuperReg(
289 RISCV::X8 + RegNo, RISCV::sub_gpr_even,
290 &RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID]);
291 Inst.addOperand(MCOperand::createReg(Reg));
292 return MCDisassembler::Success;
293}
294
295static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo,
296 uint64_t Address,
297 const void *Decoder) {
298 if (RegNo >= 8)
299 return MCDisassembler::Fail;
300
301 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
302 Inst.addOperand(MCOperand::createReg(Reg));
303 return MCDisassembler::Success;
304}
305
306static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
307 uint64_t Address,
308 const MCDisassembler *Decoder) {
309 if (RegNo >= 32)
310 return MCDisassembler::Fail;
311
312 MCRegister Reg = RISCV::V0 + RegNo;
313 Inst.addOperand(MCOperand::createReg(Reg));
314 return MCDisassembler::Success;
315}
316
317static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
318 uint64_t Address,
319 const MCDisassembler *Decoder) {
320 if (RegNo >= 32 || RegNo % 2)
321 return MCDisassembler::Fail;
322
323 const RISCVDisassembler *Dis =
324 static_cast<const RISCVDisassembler *>(Decoder);
325 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
326 MCRegister Reg =
327 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
328 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
329
330 Inst.addOperand(MCOperand::createReg(Reg));
331 return MCDisassembler::Success;
332}
333
334static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
335 uint64_t Address,
336 const MCDisassembler *Decoder) {
337 if (RegNo >= 32 || RegNo % 4)
338 return MCDisassembler::Fail;
339
340 const RISCVDisassembler *Dis =
341 static_cast<const RISCVDisassembler *>(Decoder);
342 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
343 MCRegister Reg =
344 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
345 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
346
347 Inst.addOperand(MCOperand::createReg(Reg));
348 return MCDisassembler::Success;
349}
350
351static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
352 uint64_t Address,
353 const MCDisassembler *Decoder) {
354 if (RegNo >= 32 || RegNo % 8)
355 return MCDisassembler::Fail;
356
357 const RISCVDisassembler *Dis =
358 static_cast<const RISCVDisassembler *>(Decoder);
359 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
360 MCRegister Reg =
361 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
362 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
363
364 Inst.addOperand(MCOperand::createReg(Reg));
365 return MCDisassembler::Success;
366}
367
368static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
369 uint64_t Address,
370 const MCDisassembler *Decoder) {
371 if (RegNo)
372 return MCDisassembler::Fail;
373
374 Inst.addOperand(MCOperand::createReg(RISCV::V0));
375 return MCDisassembler::Success;
376}
377
378static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo,
379 uint64_t Address,
380 const MCDisassembler *Decoder) {
381 if (RegNo > 15)
382 return MCDisassembler::Fail;
383
384 MCRegister Reg = RISCV::T0 + RegNo;
385 Inst.addOperand(MCOperand::createReg(Reg));
386 return MCDisassembler::Success;
387}
388
389static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
390 uint64_t Address,
391 const MCDisassembler *Decoder) {
392 if (RegNo > 15 || RegNo % 2)
393 return MCDisassembler::Fail;
394
395 MCRegister Reg = RISCV::T0 + RegNo;
396 Inst.addOperand(MCOperand::createReg(Reg));
397 return MCDisassembler::Success;
398}
399
400static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
401 uint64_t Address,
402 const MCDisassembler *Decoder) {
403 if (RegNo > 15 || RegNo % 4)
404 return MCDisassembler::Fail;
405
406 MCRegister Reg = RISCV::T0 + RegNo;
407 Inst.addOperand(MCOperand::createReg(Reg));
408 return MCDisassembler::Success;
409}
410
411static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
412 uint64_t Address,
413 const MCDisassembler *Decoder) {
414 if (RegNo >= 2)
415 return MCDisassembler::Fail;
416
417 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
418
419 Inst.addOperand(MCOperand::createReg(Reg));
420 return MCDisassembler::Success;
421}
422
423static DecodeStatus decodeImmThreeOperand(MCInst &Inst,
424 const MCDisassembler *Decoder) {
425 Inst.addOperand(MCOperand::createImm(3));
426 return MCDisassembler::Success;
427}
428
429static DecodeStatus decodeImmFourOperand(MCInst &Inst,
430 const MCDisassembler *Decoder) {
431 Inst.addOperand(MCOperand::createImm(4));
432 return MCDisassembler::Success;
433}
434
435template <unsigned N>
436static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
437 int64_t Address,
438 const MCDisassembler *Decoder) {
439 assert(isUInt<N>(Imm) && "Invalid immediate");
440 Inst.addOperand(MCOperand::createImm(Imm));
441 return MCDisassembler::Success;
442}
443
444template <unsigned Width, unsigned LowerBound>
445static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm,
446 int64_t Address,
447 const MCDisassembler *Decoder) {
448 assert(isUInt<Width>(Imm) && "Invalid immediate");
449
450 if (Imm < LowerBound)
451 return MCDisassembler::Fail;
452
453 Inst.addOperand(MCOperand::createImm(Imm));
454 return MCDisassembler::Success;
455}
456
457template <unsigned Width, unsigned LowerBound>
458static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
459 int64_t Address,
460 const MCDisassembler *Decoder) {
461 assert(isUInt<Width>(Imm) && "Invalid immediate");
462
463 if ((Imm + 1) < LowerBound)
464 return MCDisassembler::Fail;
465
466 Inst.addOperand(MCOperand::createImm(Imm + 1));
467 return MCDisassembler::Success;
468}
469
470static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm,
471 int64_t Address,
472 const MCDisassembler *Decoder) {
473 assert(isUInt<3>(Imm) && "Invalid Slist immediate");
474 const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
475 Inst.addOperand(MCOperand::createImm(Slist[Imm]));
476 return MCDisassembler::Success;
477}
478
479static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
480 int64_t Address,
481 const MCDisassembler *Decoder) {
482 assert(isUInt<6>(Imm) && "Invalid immediate");
483
484 if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
485 !isUInt<5>(Imm))
486 return MCDisassembler::Fail;
487
488 Inst.addOperand(MCOperand::createImm(Imm));
489 return MCDisassembler::Success;
490}
491
492template <unsigned N>
493static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
494 int64_t Address,
495 const MCDisassembler *Decoder) {
496 if (Imm == 0)
497 return MCDisassembler::Fail;
498 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
499}
500
501static DecodeStatus
502decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
503 const MCDisassembler *Decoder) {
504 if (Imm == 0)
505 return MCDisassembler::Fail;
506 return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
507}
508
509template <unsigned N>
510static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm,
511 int64_t Address,
512 const MCDisassembler *Decoder) {
513 assert(isUInt<N>(Imm) && "Invalid immediate");
514 Inst.addOperand(MCOperand::createImm(Imm + 1));
515 return MCDisassembler::Success;
516}
517
518static DecodeStatus decodeImmZibiOperand(MCInst &Inst, uint32_t Imm,
519 int64_t Address,
520 const MCDisassembler *Decoder) {
521 assert(isUInt<5>(Imm) && "Invalid immediate");
522 Inst.addOperand(MCOperand::createImm(Imm ? Imm : -1LL));
523 return MCDisassembler::Success;
524}
525
526template <unsigned N>
527static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
528 int64_t Address,
529 const MCDisassembler *Decoder) {
530 assert(isUInt<N>(Imm) && "Invalid immediate");
531 // Sign-extend the number in the bottom N bits of Imm
532 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
533 return MCDisassembler::Success;
534}
535
536template <unsigned N>
537static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
538 int64_t Address,
539 const MCDisassembler *Decoder) {
540 if (Imm == 0)
541 return MCDisassembler::Fail;
542 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
543}
544
545template <unsigned T, unsigned N>
546static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm,
547 int64_t Address,
548 const MCDisassembler *Decoder) {
549 assert(isUInt<T - N + 1>(Imm) && "Invalid immediate");
550 // Sign-extend the number in the bottom T bits of Imm after accounting for
551 // the fact that the T bit immediate is stored in T-N bits (the LSB is
552 // always zero)
553 Inst.addOperand(MCOperand::createImm(SignExtend64<T>(Imm << N)));
554 return MCDisassembler::Success;
555}
556
557static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
558 int64_t Address,
559 const MCDisassembler *Decoder) {
560 assert(isUInt<6>(Imm) && "Invalid immediate");
561 if (Imm == 0)
562 return MCDisassembler::Fail;
563 Imm = SignExtend64<6>(Imm) & 0xfffff;
564 Inst.addOperand(MCOperand::createImm(Imm));
565 return MCDisassembler::Success;
566}
567
568static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
569 const MCDisassembler *Decoder) {
570 assert(isUInt<3>(Imm) && "Invalid immediate");
571 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
572 return MCDisassembler::Fail;
573
574 Inst.addOperand(MCOperand::createImm(Imm));
575 return MCDisassembler::Success;
576}
577
578static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
579 const MCDisassembler *Decoder) {
580 assert(isUInt<3>(Imm) && "Invalid immediate");
581 if (Imm != RISCVFPRndMode::RTZ)
582 return MCDisassembler::Fail;
583
584 Inst.addOperand(MCOperand::createImm(Imm));
585 return MCDisassembler::Success;
586}
587
588static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
589 uint64_t Address,
590 const MCDisassembler *Decoder) {
591 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
592 if (Imm < RISCVZC::RA || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
593 return MCDisassembler::Fail;
594 Inst.addOperand(MCOperand::createImm(Imm));
595 return MCDisassembler::Success;
596}
597
598static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
599 uint64_t Address,
600 const MCDisassembler *Decoder) {
601 if (Imm < RISCVZC::RA_S0)
602 return MCDisassembler::Fail;
603 return decodeZcmpRlist(Inst, Imm, Address, Decoder);
604}
605
606#include "RISCVGenDisassemblerTables.inc"
607
608namespace {
609
610struct DecoderListEntry {
611 const uint8_t *Table;
612 FeatureBitset ContainedFeatures;
613 const char *Desc;
614
615 bool haveContainedFeatures(const FeatureBitset &ActiveFeatures) const {
616 return ContainedFeatures.none() ||
617 (ContainedFeatures & ActiveFeatures).any();
618 }
619};
620
621} // end anonymous namespace
622
623static constexpr FeatureBitset XCVFeatureGroup = {
624 RISCV::FeatureVendorXCVbitmanip, RISCV::FeatureVendorXCVelw,
625 RISCV::FeatureVendorXCVmac, RISCV::FeatureVendorXCVmem,
626 RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
627 RISCV::FeatureVendorXCVbi};
628
629static constexpr FeatureBitset XRivosFeatureGroup = {
630 RISCV::FeatureVendorXRivosVisni,
631 RISCV::FeatureVendorXRivosVizip,
632};
633
634static constexpr FeatureBitset XqciFeatureGroup = {
635 RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
636 RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
637 RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
638 RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
639 RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqciio,
640 RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,
641 RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
642 RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
643 RISCV::FeatureVendorXqcisls, RISCV::FeatureVendorXqcisync,
644};
645
646static constexpr FeatureBitset XSfVectorGroup = {
647 RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
648 RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
649 RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
650static constexpr FeatureBitset XSfSystemGroup = {
651 RISCV::FeatureVendorXSiFivecdiscarddlone,
652 RISCV::FeatureVendorXSiFivecflushdlone,
653};
654
655static constexpr FeatureBitset XMIPSGroup = {
656 RISCV::FeatureVendorXMIPSLSP,
657 RISCV::FeatureVendorXMIPSCMov,
658 RISCV::FeatureVendorXMIPSCBOP,
659 RISCV::FeatureVendorXMIPSEXECTL,
660};
661
662static constexpr FeatureBitset XTHeadGroup = {
663 RISCV::FeatureVendorXTHeadBa, RISCV::FeatureVendorXTHeadBb,
664 RISCV::FeatureVendorXTHeadBs, RISCV::FeatureVendorXTHeadCondMov,
665 RISCV::FeatureVendorXTHeadCmo, RISCV::FeatureVendorXTHeadFMemIdx,
666 RISCV::FeatureVendorXTHeadMac, RISCV::FeatureVendorXTHeadMemIdx,
667 RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,
668 RISCV::FeatureVendorXTHeadVdot};
669
670static constexpr FeatureBitset XAndesGroup = {
671 RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
672 RISCV::FeatureVendorXAndesVBFHCvt,
673 RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
674 RISCV::FeatureVendorXAndesVDot};
675
676static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
677
678static constexpr DecoderListEntry DecoderList32[]{
679 // Vendor Extensions
680 {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
681 {DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
682 {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
683 {DecoderTableXVentana32,
684 {RISCV::FeatureVendorXVentanaCondOps},
685 "XVentanaCondOps"},
686 {DecoderTableXTHead32, XTHeadGroup, "T-Head extensions"},
687 {DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
688 {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
689 {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
690 {DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},
691 {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
692 {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
693 // Standard Extensions
694 {DecoderTable32, {}, "standard 32-bit instructions"},
695 {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
696 {DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
697 {DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
698};
699
700namespace {
701// Define bitwidths for various types used to instantiate the decoder.
702template <> constexpr uint32_t InsnBitWidth<uint16_t> = 16;
703template <> constexpr uint32_t InsnBitWidth<uint32_t> = 32;
704// Use uint64_t to represent 48 bit instructions.
705template <> constexpr uint32_t InsnBitWidth<uint64_t> = 48;
706} // namespace
707
708DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
709 ArrayRef<uint8_t> Bytes,
710 uint64_t Address,
711 raw_ostream &CS) const {
712 if (Bytes.size() < 4) {
713 Size = 0;
714 return MCDisassembler::Fail;
715 }
716 Size = 4;
717
718 uint32_t Insn = support::endian::read32le(Bytes.data());
719
720 for (const DecoderListEntry &Entry : DecoderList32) {
721 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
722 continue;
723
724 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
725 DecodeStatus Result =
726 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
727 if (Result == MCDisassembler::Fail)
728 continue;
729
730 return Result;
731 }
732
733 return MCDisassembler::Fail;
734}
735
736static constexpr DecoderListEntry DecoderList16[]{
737 // Vendor Extensions
738 {DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16-bit"},
739 {DecoderTableXqccmp16,
740 {RISCV::FeatureVendorXqccmp},
741 "Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
742 {DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
743 // Standard Extensions
744 // DecoderTableZicfiss16 must be checked before DecoderTable16.
745 {DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
746 {DecoderTable16, {}, "standard 16-bit instructions"},
747 {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
748 // Zc* instructions incompatible with Zcf or Zcd
749 {DecoderTableZcOverlap16,
750 {},
751 "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)"},
752};
753
754DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
755 ArrayRef<uint8_t> Bytes,
756 uint64_t Address,
757 raw_ostream &CS) const {
758 if (Bytes.size() < 2) {
759 Size = 0;
760 return MCDisassembler::Fail;
761 }
762 Size = 2;
763
764 uint16_t Insn = support::endian::read16le(Bytes.data());
765
766 for (const DecoderListEntry &Entry : DecoderList16) {
767 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
768 continue;
769
770 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
771 DecodeStatus Result =
772 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
773 if (Result != MCDisassembler::Fail)
774 return Result;
775 }
776
777 return MCDisassembler::Fail;
778}
779
780static constexpr DecoderListEntry DecoderList48[]{
781 {DecoderTableXqci48, XqciFeatureGroup, "Qualcomm uC 48bit"},
782};
783
784DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
785 ArrayRef<uint8_t> Bytes,
786 uint64_t Address,
787 raw_ostream &CS) const {
788 if (Bytes.size() < 6) {
789 Size = 0;
790 return MCDisassembler::Fail;
791 }
792 Size = 6;
793
794 uint64_t Insn = 0;
795 for (size_t i = Size; i-- != 0;)
796 Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
797
798 for (const DecoderListEntry &Entry : DecoderList48) {
799 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
800 continue;
801
802 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
803 DecodeStatus Result =
804 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
805 if (Result == MCDisassembler::Fail)
806 continue;
807
808 return Result;
809 }
810
811 return MCDisassembler::Fail;
812}
813
814DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
815 ArrayRef<uint8_t> Bytes,
816 uint64_t Address,
817 raw_ostream &CS) const {
818 CommentStream = &CS;
819 // It's a 16 bit instruction if bit 0 and 1 are not 0b11.
820 if ((Bytes[0] & 0b11) != 0b11)
821 return getInstruction16(MI, Size, Bytes, Address, CS);
822
823 // It's a 32 bit instruction if bit 1:0 are 0b11(checked above) and bits 4:2
824 // are not 0b111.
825 if ((Bytes[0] & 0b1'1100) != 0b1'1100)
826 return getInstruction32(MI, Size, Bytes, Address, CS);
827
828 // 48-bit instructions are encoded as 0bxx011111.
829 if ((Bytes[0] & 0b11'1111) == 0b01'1111) {
830 return getInstruction48(MI, Size, Bytes, Address, CS);
831 }
832
833 // 64-bit instructions are encoded as 0x0111111.
834 if ((Bytes[0] & 0b111'1111) == 0b011'1111) {
835 Size = Bytes.size() >= 8 ? 8 : 0;
836 return MCDisassembler::Fail;
837 }
838
839 // Remaining cases need to check a second byte.
840 if (Bytes.size() < 2) {
841 Size = 0;
842 return MCDisassembler::Fail;
843 }
844
845 // 80-bit through 176-bit instructions are encoded as 0bxnnnxxxx_x1111111.
846 // Where the number of bits is (80 + (nnn * 16)) for nnn != 0b111.
847 unsigned nnn = (Bytes[1] >> 4) & 0b111;
848 if (nnn != 0b111) {
849 Size = 10 + (nnn * 2);
850 if (Bytes.size() < Size)
851 Size = 0;
852 return MCDisassembler::Fail;
853 }
854
855 // Remaining encodings are reserved for > 176-bit instructions.
856 Size = 0;
857 return MCDisassembler::Fail;
858}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:213
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
Reg
Register Reg
Definition MachineSink.cpp:2117
T
#define T
Definition Mips16ISelLowering.cpp:353
XqciFeatureGroup
static constexpr FeatureBitset XqciFeatureGroup
Definition RISCVDisassembler.cpp:634
decodeUImmSlistOperand
static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:470
XSMTGroup
static constexpr FeatureBitset XSMTGroup
Definition RISCVDisassembler.cpp:676
decodeUImmLog2XLenOperand
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:479
XCVFeatureGroup
static constexpr FeatureBitset XCVFeatureGroup
Definition RISCVDisassembler.cpp:623
DecoderList48
static constexpr DecoderListEntry DecoderList48[]
Definition RISCVDisassembler.cpp:780
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:527
DecoderList16
static constexpr DecoderListEntry DecoderList16[]
Definition RISCVDisassembler.cpp:736
DecodeGPRX1X5RegisterClass
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:120
DecodeGPRNoX31RegisterClass
static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:233
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:243
decodeImmFourOperand
static DecodeStatus decodeImmFourOperand(MCInst &Inst, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:429
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:164
decodeUImmLog2XLenNonZeroOperand
static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:502
decodeRTZArg
static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:578
createRISCVDisassembler
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition RISCVDisassembler.cpp:62
DecodeGPRF16RegisterClass
static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:94
DecodeTRM2RegisterClass
static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:389
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:186
decodeSImmOperandAndLslN
static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:546
XSfVectorGroup
static constexpr FeatureBitset XSfVectorGroup
Definition RISCVDisassembler.cpp:646
DecoderList32
static constexpr DecoderListEntry DecoderList32[]
Definition RISCVDisassembler.cpp:678
DecodeGPRX5RegisterClass
static DecodeStatus DecodeGPRX5RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:209
decodeImmThreeOperand
static DecodeStatus decodeImmThreeOperand(MCInst &Inst, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:423
decodeXqccmpRlistS0
static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:598
DecodeFPR32CRegisterClass
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:153
decodeUImmPlus1Operand
static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:510
decodeCLUIImmOperand
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:557
decodeZcmpRlist
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:588
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:436
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:142
DecodeVRM8RegisterClass
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:351
DecodeVRM4RegisterClass
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:334
DecodeGPRNoX2RegisterClass
static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:224
DecodeVRRegisterClass
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:306
DecodeVRM2RegisterClass
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:317
DecodeGPRPairRegisterClass
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:254
decodeImmZibiOperand
static DecodeStatus decodeImmZibiOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:518
DecodeSPRegisterClass
static DecodeStatus DecodeSPRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:203
XMIPSGroup
static constexpr FeatureBitset XMIPSGroup
Definition RISCVDisassembler.cpp:655
decodeSImmNonZeroOperand
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:537
DecodeGPRPairNoX0RegisterClass
static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:271
DecodeVMV0RegisterClass
static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:368
DecodeTRRegisterClass
static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:378
DecodeFPR64CRegisterClass
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:175
DecodeGPRF32RegisterClass
static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:107
XAndesGroup
static constexpr FeatureBitset XAndesGroup
Definition RISCVDisassembler.cpp:670
DecodeTRM4RegisterClass
static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:400
DecodeGPRNoX0RegisterClass
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:215
decodeFRMArg
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:568
DecodeGPRX1RegisterClass
static DecodeStatus DecodeGPRX1RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:197
DecodeSR07RegisterClass
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const void *Decoder)
Definition RISCVDisassembler.cpp:295
XTHeadGroup
static constexpr FeatureBitset XTHeadGroup
Definition RISCVDisassembler.cpp:662
XRivosFeatureGroup
static constexpr FeatureBitset XRivosFeatureGroup
Definition RISCVDisassembler.cpp:629
decodeUImmPlus1OperandGE
static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:458
LLVMInitializeRISCVDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
Definition RISCVDisassembler.cpp:69
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:131
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:81
decodeVMaskReg
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:411
decodeUImmNonZeroOperand
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:493
XSfSystemGroup
static constexpr FeatureBitset XSfSystemGroup
Definition RISCVDisassembler.cpp:650
decodeUImmOperandGE
static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:445
DecodeGPRPairCRegisterClass
static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:279
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition Debug.h:114
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
llvm::ArrayRef::data
const T * data() const
Definition ArrayRef.h:144
llvm::FeatureBitset
Container class for subtarget features.
Definition SubtargetFeature.h:42
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition MCDisassembler.h:230
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:150
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition MCRegisterInfo.cpp:108
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:122
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:146
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint32_t
uint64_t
uint8_t
llvm::BitmaskEnumDetail::any
constexpr bool any(E Val)
Definition BitmaskEnum.h:151
llvm::COFF::Entry
@ Entry
Definition COFF.h:862
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition RISCVBaseInfo.h:448
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm::support::endian::read16le
uint16_t read16le(const void *P)
Definition Endian.h:425
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition Endian.h:428
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition RISCVTargetInfo.cpp:14
llvm::getTheRISCV64beTarget
Target & getTheRISCV64beTarget()
Definition RISCVTargetInfo.cpp:29
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:207
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:198
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition RISCVTargetInfo.cpp:19
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:583
llvm::getTheRISCV32beTarget
Target & getTheRISCV32beTarget()
Definition RISCVTargetInfo.cpp:24
N
#define N
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:934
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