#include "RISCVISelDAGToDAG.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCVISelLowering.h"
#include "RISCVInstrInfo.h"
#include "RISCVSelectionDAGInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "RISCVGenDAGISel.inc"

Macros
#define	DEBUG_TYPE "riscv-isel"
#define	PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection"
#define	GET_DAGISEL_BODY RISCVDAGToDAGISel
#define	INST_NF_CASE(NAME, NF)
#define	INST_NF_CASE_MASK(NAME, NF)
#define	INST_NF_CASE_FF(NAME, NF)
#define	INST_NF_CASE_FF_MASK(NAME, NF)
#define	INST_ALL_NF_CASE_BASE(MACRO_NAME, NAME)
#define	INST_ALL_NF_CASE(NAME)
#define	INST_ALL_NF_CASE_WITH_FF(NAME)
#define	CASE_VMSLT_OPCODES(lmulenum, suffix)
#define	CASE_VMNAND_VMSET_OPCODES(lmulenum, suffix)
#define	CASE_VMSLT_OPCODES(lmulenum, suffix)
#define	CASE_VMXOR_VMANDN_VMOR_OPCODES(lmulenum, suffix)

Functions
static SDValue	selectImmSeq (SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, RISCVMatInt::InstSeq &Seq)
static SDValue	selectImm (SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, int64_t Imm, const RISCVSubtarget &Subtarget)
static unsigned	getSegInstNF (unsigned Intrinsic)
static bool	selectConstantAddr (SelectionDAG CurDAG, const SDLoc &DL, const MVT VT, const RISCVSubtarget Subtarget, SDValue Addr, SDValue &Base, SDValue &Offset, bool IsPrefetch=false)
static bool	isWorthFoldingAdd (SDValue Add)
bool	isRegImmLoadOrStore (SDNode *User, SDValue Add)
static bool	isRegRegScaleLoadOrStore (SDNode *User, SDValue Add, const RISCVSubtarget &Subtarget)
	Return true if this a load/store that we have a RegRegScale instruction for.
static bool	isWorthFoldingIntoRegRegScale (const RISCVSubtarget &Subtarget, SDValue Add, SDValue Shift=SDValue())
	Is it profitable to fold this Add into RegRegScale load/store.
static bool	vectorPseudoHasAllNBitUsers (SDNode User, unsigned UserOpNo, unsigned Bits, const TargetInstrInfo TII)
static SDValue	findVSplat (SDValue N)
static bool	selectVSplatImmHelper (SDValue N, SDValue &SplatVal, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, std::function< bool(int64_t)> ValidateImm, bool Decrement=false)
static bool	usesAllOnesMask (SDValue MaskOp)
static bool	isImplicitDef (SDValue V)

Variables
static cl::opt< bool >	UsePseudoMovImm ("riscv-use-rematerializable-movimm", cl::Hidden, cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization"), cl::init(false))

Macro Definition Documentation

◆ CASE_VMNAND_VMSET_OPCODES

#define CASE_VMNAND_VMSET_OPCODES	(		lmulenum,
			suffix )

Value:

  case RISCVVType::lmulenum:                                                   \
    VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix;                            \
    VMSetOpcode = RISCV::PseudoVMSET_M_##suffix;                               \
    break;

Referenced by llvm::RISCVDAGToDAGISel::Select().

◆ CASE_VMSLT_OPCODES [1/2]

#define CASE_VMSLT_OPCODES	(		lmulenum,
			suffix )

Value:

  case RISCVVType::lmulenum:                                                   \
    VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix                 \
                             : RISCV::PseudoVMSLT_VX_##suffix;                 \
    VMSGTOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix                 \
                             : RISCV::PseudoVMSGT_VX_##suffix;                 \
    break;

Referenced by llvm::RISCVDAGToDAGISel::Select().

◆ CASE_VMSLT_OPCODES [2/2]

#define CASE_VMSLT_OPCODES	(		lmulenum,
			suffix )

Value:

  case RISCVVType::lmulenum:                                                   \
    VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix                 \
                             : RISCV::PseudoVMSLT_VX_##suffix;                 \
    VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix##_MASK      \
                                 : RISCV::PseudoVMSLT_VX_##suffix##_MASK;      \
    VMSGTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix##_MASK      \
                                 : RISCV::PseudoVMSGT_VX_##suffix##_MASK;      \
    break;

◆ CASE_VMXOR_VMANDN_VMOR_OPCODES

#define CASE_VMXOR_VMANDN_VMOR_OPCODES	(		lmulenum,
			suffix )

Value:

  case RISCVVType::lmulenum:                                                   \
    VMXOROpcode = RISCV::PseudoVMXOR_MM_##suffix;                              \
    VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix;                            \
    VMOROpcode = RISCV::PseudoVMOR_MM_##suffix;                                \
    break;

Referenced by llvm::RISCVDAGToDAGISel::Select().

◆ DEBUG_TYPE

#define DEBUG_TYPE "riscv-isel"

Definition at line 30 of file RISCVISelDAGToDAG.cpp.

◆ GET_DAGISEL_BODY

#define GET_DAGISEL_BODY RISCVDAGToDAGISel

Definition at line 39 of file RISCVISelDAGToDAG.cpp.

◆ INST_ALL_NF_CASE

#define INST_ALL_NF_CASE ( NAME )

Value:

INST_ALL_NF_CASE_BASE(INST_NF_CASE, NAME) \

INST_ALL_NF_CASE_BASE(INST_NF_CASE_MASK, NAME)

INST_NF_CASE

#define INST_NF_CASE(NAME, NF)

INST_ALL_NF_CASE_BASE

#define INST_ALL_NF_CASE_BASE(MACRO_NAME, NAME)

INST_NF_CASE_MASK

#define INST_NF_CASE_MASK(NAME, NF)

Referenced by getSegInstNF().

◆ INST_ALL_NF_CASE_BASE

#define INST_ALL_NF_CASE_BASE	(		MACRO_NAME,
			NAME )

Value:

  MACRO_NAME(NAME, 2)                                                          \
  MACRO_NAME(NAME, 3)                                                          \
  MACRO_NAME(NAME, 4)                                                          \
  MACRO_NAME(NAME, 5)                                                          \
  MACRO_NAME(NAME, 6)                                                          \
  MACRO_NAME(NAME, 7)                                                          \
  MACRO_NAME(NAME, 8)

◆ INST_ALL_NF_CASE_WITH_FF

#define INST_ALL_NF_CASE_WITH_FF ( NAME )

Value:

  INST_ALL_NF_CASE(NAME)                                                       \
  INST_ALL_NF_CASE_BASE(INST_NF_CASE_FF, NAME)                                 \
  INST_ALL_NF_CASE_BASE(INST_NF_CASE_FF_MASK, NAME)

Referenced by getSegInstNF().

◆ INST_NF_CASE

#define INST_NF_CASE	(		NAME,
			NF )

Value:

case Intrinsic::riscv_##NAME##NF: \

return NF;

◆ INST_NF_CASE_FF

#define INST_NF_CASE_FF	(		NAME,
			NF )

Value:

case Intrinsic::riscv_##NAME##NF##ff: \

return NF;

◆ INST_NF_CASE_FF_MASK

#define INST_NF_CASE_FF_MASK	(		NAME,
			NF )

Value:

case Intrinsic::riscv_##NAME##NF##ff_mask: \

return NF;

◆ INST_NF_CASE_MASK

#define INST_NF_CASE_MASK	(		NAME,
			NF )

Value:

case Intrinsic::riscv_##NAME##NF##_mask: \

return NF;

◆ PASS_NAME

#define PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection"

Definition at line 31 of file RISCVISelDAGToDAG.cpp.

Function Documentation

◆ findVSplat()

SDValue findVSplat ( SDValue N )

static

Definition at line 4071 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::ISD::INSERT_SUBVECTOR, N, SDValue(), and llvm::Splat.

Referenced by llvm::RISCVDAGToDAGISel::selectVSplat(), llvm::RISCVDAGToDAGISel::selectVSplatImm64Neg(), and selectVSplatImmHelper().

◆ getSegInstNF()

unsigned getSegInstNF ( unsigned Intrinsic )

static

Definition at line 998 of file RISCVISelDAGToDAG.cpp.

References INST_ALL_NF_CASE, INST_ALL_NF_CASE_WITH_FF, and llvm_unreachable.

Referenced by llvm::RISCVDAGToDAGISel::Select().

◆ isImplicitDef()

bool isImplicitDef ( SDValue V )

static

Definition at line 4332 of file RISCVISelDAGToDAG.cpp.

References I, and isImplicitDef().

Referenced by isImplicitDef().

◆ isRegImmLoadOrStore()

bool isRegImmLoadOrStore	(	SDNode *	User,
		SDValue	Add )

Definition at line 2908 of file RISCVISelDAGToDAG.cpp.

References llvm::Add, llvm::cast(), llvm::User::getOperand(), and getVal().

Referenced by llvm::RISCVDAGToDAGISel::areOffsetsWithinAlignment().

◆ isRegRegScaleLoadOrStore()

bool isRegRegScaleLoadOrStore	(	SDNode *	User,
		SDValue	Add,
		const RISCVSubtarget &	Subtarget )

static

Return true if this a load/store that we have a RegRegScale instruction for.

Definition at line 3165 of file RISCVISelDAGToDAG.cpp.

References llvm::Add, llvm::cast(), and llvm::EVT::isScalarInteger().

Referenced by isWorthFoldingIntoRegRegScale().

◆ isWorthFoldingAdd()

bool isWorthFoldingAdd ( SDValue Add )

static

Definition at line 2879 of file RISCVISelDAGToDAG.cpp.

References llvm::Add, llvm::cast(), llvm::User::getOperand(), llvm::EVT::isScalarInteger(), and llvm::isStrongerThanMonotonic().

Referenced by llvm::RISCVDAGToDAGISel::SelectAddrRegImm().

◆ isWorthFoldingIntoRegRegScale()

bool isWorthFoldingIntoRegRegScale	(	const RISCVSubtarget &	Subtarget,
		SDValue	Add,
		SDValue	Shift = SDValue() )

static

Is it profitable to fold this Add into RegRegScale load/store.

If Shift is non-null, then we have matched a shl+add. We allow reassociating (add (add (shl A C2) B) C1) -> (add (add B C1) (shl A C2)) if there is a single addi and we don't have a SHXADD instruction we could use. FIXME: May still need to check how many and what kind of users the SHL has.

Definition at line 3188 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::Add, assert(), llvm::cast(), llvm::User::getOperand(), llvm::RISCVSubtarget::hasShlAdd(), llvm::isa(), llvm::isInt(), isRegRegScaleLoadOrStore(), SDValue(), llvm::ISD::SHL, and llvm::Value::users().

Referenced by llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale().

◆ selectConstantAddr()

bool selectConstantAddr	(	SelectionDAG *	CurDAG,
		const SDLoc &	DL,
		const MVT	VT,
		const RISCVSubtarget *	Subtarget,
		SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset,
		bool	IsPrefetch = false )

static

◆ selectImm()

SDValue selectImm	(	SelectionDAG *	CurDAG,
		const SDLoc &	DL,
		const MVT	VT,
		int64_t	Imm,
		const RISCVSubtarget &	Subtarget )

static

Definition at line 208 of file RISCVISelDAGToDAG.cpp.

References DL, llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVMatInt::generateTwoRegInstSeq(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::Lo, SDValue(), selectImmSeq(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and UsePseudoMovImm.

Referenced by llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectInvLogicImm(), llvm::RISCVDAGToDAGISel::selectScalarFPAsInt(), and llvm::RISCVDAGToDAGISel::tryBitfieldInsertOpFromOrAndImm().

◆ selectImmSeq()

SDValue selectImmSeq	(	SelectionDAG *	CurDAG,
		const SDLoc &	DL,
		const MVT	VT,
		RISCVMatInt::InstSeq &	Seq )

static

Definition at line 179 of file RISCVISelDAGToDAG.cpp.

References DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::RISCVMatInt::Imm, llvm::RISCVMatInt::RegImm, llvm::RISCVMatInt::RegReg, llvm::RISCVMatInt::RegX0, and SDValue().

Referenced by selectConstantAddr(), and selectImm().

◆ selectVSplatImmHelper()

bool selectVSplatImmHelper	(	SDValue	N,
		SDValue &	SplatVal,
		SelectionDAG &	DAG,
		const RISCVSubtarget &	Subtarget,
		std::function< bool(int64_t)>	ValidateImm,
		bool	Decrement = false )

static

Definition at line 4095 of file RISCVISelDAGToDAG.cpp.

References assert(), findVSplat(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::isa(), N, and llvm::Splat.

Referenced by llvm::RISCVDAGToDAGISel::selectVSplatSimm5(), llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1(), llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1NoDec(), llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(), and llvm::RISCVDAGToDAGISel::selectVSplatUimm().

◆ usesAllOnesMask()

bool usesAllOnesMask ( SDValue MaskOp )

static

Definition at line 4318 of file RISCVISelDAGToDAG.cpp.

References llvm::SDValue::getMachineOpcode(), llvm::SDNode::isMachineOpcode(), and Opc.

◆ vectorPseudoHasAllNBitUsers()

bool vectorPseudoHasAllNBitUsers	(	SDNode *	User,
		unsigned	UserOpNo,
		unsigned	Bits,
		const TargetInstrInfo *	TII )

static

Definition at line 3816 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::User::getNumOperands(), llvm::User::getOperand(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCV::getVectorLowDemandedScalarBits(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::hasVLOp(), and TII.

Referenced by llvm::RISCVDAGToDAGISel::hasAllNBitUsers().

Variable Documentation

◆ UsePseudoMovImm

cl::opt< bool > UsePseudoMovImm("riscv-use-rematerializable-movimm", cl::Hidden, cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization"), cl::init(false))	(	"riscv-use-rematerializable-movimm"	,
		cl::Hidden	,
		cl::desc("Use a rematerializable pseudoinstruction for 2 instruction " "constant materialization")	,
		cl::init(false)	)

static

Referenced by selectImm().

Macros

Functions

Variables

Macro Definition Documentation

◆ CASE_VMNAND_VMSET_OPCODES

◆ CASE_VMSLT_OPCODES [1/2]

◆ CASE_VMSLT_OPCODES [2/2]

◆ CASE_VMXOR_VMANDN_VMOR_OPCODES

◆ DEBUG_TYPE

◆ GET_DAGISEL_BODY

◆ INST_ALL_NF_CASE

◆ INST_ALL_NF_CASE_BASE

◆ INST_ALL_NF_CASE_WITH_FF

◆ INST_NF_CASE

◆ INST_NF_CASE_FF

◆ INST_NF_CASE_FF_MASK

◆ INST_NF_CASE_MASK

◆ PASS_NAME

Function Documentation

◆ findVSplat()

◆ getSegInstNF()

◆ isImplicitDef()

◆ isRegImmLoadOrStore()

◆ isRegRegScaleLoadOrStore()

◆ isWorthFoldingAdd()

◆ isWorthFoldingIntoRegRegScale()

◆ selectConstantAddr()

◆ selectImm()

◆ selectImmSeq()

◆ selectVSplatImmHelper()

◆ usesAllOnesMask()

◆ vectorPseudoHasAllNBitUsers()

Variable Documentation

◆ UsePseudoMovImm