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SPIRVUtils.cpp
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1//===--- SPIRVUtils.cpp ---- SPIR-V Utility Functions -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains miscellaneous utility functions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SPIRVUtils.h"
15#include "SPIRV.h"
16#include "SPIRVGlobalRegistry.h"
17#include "SPIRVInstrInfo.h"
18#include "SPIRVSubtarget.h"
19#include "llvm/ADT/StringRef.h"
26#include "llvm/IR/IntrinsicsSPIRV.h"
27#include <queue>
28#include <vector>
29
30namespace llvm {
31
32// The following functions are used to add these string literals as a series of
33// 32-bit integer operands with the correct format, and unpack them if necessary
34// when making string comparisons in compiler passes.
35// SPIR-V requires null-terminated UTF-8 strings padded to 32-bit alignment.
36static uint32_t convertCharsToWord(const StringRef &Str, unsigned i) {
37 uint32_t Word = 0u; // Build up this 32-bit word from 4 8-bit chars.
38 for (unsigned WordIndex = 0; WordIndex < 4; ++WordIndex) {
39 unsigned StrIndex = i + WordIndex;
40 uint8_t CharToAdd = 0; // Initilize char as padding/null.
41 if (StrIndex < Str.size()) { // If it's within the string, get a real char.
42 CharToAdd = Str[StrIndex];
43 }
44 Word |= (CharToAdd << (WordIndex * 8));
45 }
46 return Word;
47}
48
49// Get length including padding and null terminator.
50static size_t getPaddedLen(const StringRef &Str) {
51 return (Str.size() + 4) & ~3;
52}
53
54void addStringImm(const StringRef &Str, MCInst &Inst) {
55 const size_t PaddedLen = getPaddedLen(Str);
56 for (unsigned i = 0; i < PaddedLen; i += 4) {
57 // Add an operand for the 32-bits of chars or padding.
59 }
60}
61
63 const size_t PaddedLen = getPaddedLen(Str);
64 for (unsigned i = 0; i < PaddedLen; i += 4) {
65 // Add an operand for the 32-bits of chars or padding.
66 MIB.addImm(convertCharsToWord(Str, i));
67 }
68}
69
71 std::vector<Value *> &Args) {
72 const size_t PaddedLen = getPaddedLen(Str);
73 for (unsigned i = 0; i < PaddedLen; i += 4) {
74 // Add a vector element for the 32-bits of chars or padding.
75 Args.push_back(B.getInt32(convertCharsToWord(Str, i)));
76 }
77}
78
79std::string getStringImm(const MachineInstr &MI, unsigned StartIndex) {
80 return getSPIRVStringOperand(MI, StartIndex);
81}
82
85 assert(Def && Def->getOpcode() == TargetOpcode::G_GLOBAL_VALUE &&
86 "Expected G_GLOBAL_VALUE");
87 const GlobalValue *GV = Def->getOperand(1).getGlobal();
88 Value *V = GV->getOperand(0);
90 return CDA->getAsCString().str();
91}
92
93void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB) {
94 const auto Bitwidth = Imm.getBitWidth();
95 if (Bitwidth == 1)
96 return; // Already handled
97 else if (Bitwidth <= 32) {
98 MIB.addImm(Imm.getZExtValue());
99 // Asm Printer needs this info to print floating-type correctly
100 if (Bitwidth == 16)
102 return;
103 } else if (Bitwidth <= 64) {
104 uint64_t FullImm = Imm.getZExtValue();
105 uint32_t LowBits = FullImm & 0xffffffff;
106 uint32_t HighBits = (FullImm >> 32) & 0xffffffff;
107 MIB.addImm(LowBits).addImm(HighBits);
108 return;
109 }
110 report_fatal_error("Unsupported constant bitwidth");
111}
112
114 MachineIRBuilder &MIRBuilder) {
115 if (!Name.empty()) {
116 auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target);
117 addStringImm(Name, MIB);
118 }
119}
120
122 const SPIRVInstrInfo &TII) {
123 if (!Name.empty()) {
124 auto MIB =
125 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpName))
126 .addUse(Target);
127 addStringImm(Name, MIB);
128 }
129}
130
132 const std::vector<uint32_t> &DecArgs,
133 StringRef StrImm) {
134 if (!StrImm.empty())
135 addStringImm(StrImm, MIB);
136 for (const auto &DecArg : DecArgs)
137 MIB.addImm(DecArg);
138}
139
141 SPIRV::Decoration::Decoration Dec,
142 const std::vector<uint32_t> &DecArgs, StringRef StrImm) {
143 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate)
144 .addUse(Reg)
145 .addImm(static_cast<uint32_t>(Dec));
146 finishBuildOpDecorate(MIB, DecArgs, StrImm);
147}
148
150 SPIRV::Decoration::Decoration Dec,
151 const std::vector<uint32_t> &DecArgs, StringRef StrImm) {
152 MachineBasicBlock &MBB = *I.getParent();
153 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpDecorate))
154 .addUse(Reg)
155 .addImm(static_cast<uint32_t>(Dec));
156 finishBuildOpDecorate(MIB, DecArgs, StrImm);
157}
158
160 SPIRV::Decoration::Decoration Dec, uint32_t Member,
161 const std::vector<uint32_t> &DecArgs,
162 StringRef StrImm) {
163 auto MIB = MIRBuilder.buildInstr(SPIRV::OpMemberDecorate)
164 .addUse(Reg)
165 .addImm(Member)
166 .addImm(static_cast<uint32_t>(Dec));
167 finishBuildOpDecorate(MIB, DecArgs, StrImm);
168}
169
171 const SPIRVInstrInfo &TII,
172 SPIRV::Decoration::Decoration Dec, uint32_t Member,
173 const std::vector<uint32_t> &DecArgs,
174 StringRef StrImm) {
175 MachineBasicBlock &MBB = *I.getParent();
176 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemberDecorate))
177 .addUse(Reg)
178 .addImm(Member)
179 .addImm(static_cast<uint32_t>(Dec));
180 finishBuildOpDecorate(MIB, DecArgs, StrImm);
181}
182
184 const MDNode *GVarMD, const SPIRVSubtarget &ST) {
185 for (unsigned I = 0, E = GVarMD->getNumOperands(); I != E; ++I) {
186 auto *OpMD = dyn_cast<MDNode>(GVarMD->getOperand(I));
187 if (!OpMD)
188 report_fatal_error("Invalid decoration");
189 if (OpMD->getNumOperands() == 0)
190 report_fatal_error("Expect operand(s) of the decoration");
191 ConstantInt *DecorationId =
192 mdconst::dyn_extract<ConstantInt>(OpMD->getOperand(0));
193 if (!DecorationId)
194 report_fatal_error("Expect SPIR-V <Decoration> operand to be the first "
195 "element of the decoration");
196
197 // The goal of `spirv.Decorations` metadata is to provide a way to
198 // represent SPIR-V entities that do not map to LLVM in an obvious way.
199 // FP flags do have obvious matches between LLVM IR and SPIR-V.
200 // Additionally, we have no guarantee at this point that the flags passed
201 // through the decoration are not violated already in the optimizer passes.
202 // Therefore, we simply ignore FP flags, including NoContraction, and
203 // FPFastMathMode.
204 if (DecorationId->getZExtValue() ==
205 static_cast<uint32_t>(SPIRV::Decoration::NoContraction) ||
206 DecorationId->getZExtValue() ==
207 static_cast<uint32_t>(SPIRV::Decoration::FPFastMathMode)) {
208 continue; // Ignored.
209 }
210 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate)
211 .addUse(Reg)
212 .addImm(static_cast<uint32_t>(DecorationId->getZExtValue()));
213 for (unsigned OpI = 1, OpE = OpMD->getNumOperands(); OpI != OpE; ++OpI) {
214 if (ConstantInt *OpV =
215 mdconst::dyn_extract<ConstantInt>(OpMD->getOperand(OpI)))
216 MIB.addImm(static_cast<uint32_t>(OpV->getZExtValue()));
217 else if (MDString *OpV = dyn_cast<MDString>(OpMD->getOperand(OpI)))
218 addStringImm(OpV->getString(), MIB);
219 else
220 report_fatal_error("Unexpected operand of the decoration");
221 }
222 }
223}
224
226 MachineFunction *MF = I.getParent()->getParent();
227 MachineBasicBlock *MBB = &MF->front();
228 MachineBasicBlock::iterator It = MBB->SkipPHIsAndLabels(MBB->begin()),
229 E = MBB->end();
230 bool IsHeader = false;
231 unsigned Opcode;
232 for (; It != E && It != I; ++It) {
233 Opcode = It->getOpcode();
234 if (Opcode == SPIRV::OpFunction || Opcode == SPIRV::OpFunctionParameter) {
235 IsHeader = true;
236 } else if (IsHeader &&
237 !(Opcode == SPIRV::ASSIGN_TYPE || Opcode == SPIRV::OpLabel)) {
238 ++It;
239 break;
240 }
241 }
242 return It;
243}
244
247 if (I == MBB->begin())
248 return I;
249 --I;
250 while (I->isTerminator() || I->isDebugValue()) {
251 if (I == MBB->begin())
252 break;
253 --I;
254 }
255 return I;
256}
257
258SPIRV::StorageClass::StorageClass
259addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI) {
260 switch (AddrSpace) {
261 case 0:
262 return SPIRV::StorageClass::Function;
263 case 1:
264 return SPIRV::StorageClass::CrossWorkgroup;
265 case 2:
266 return SPIRV::StorageClass::UniformConstant;
267 case 3:
268 return SPIRV::StorageClass::Workgroup;
269 case 4:
270 return SPIRV::StorageClass::Generic;
271 case 5:
272 return STI.canUseExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes)
273 ? SPIRV::StorageClass::DeviceOnlyINTEL
274 : SPIRV::StorageClass::CrossWorkgroup;
275 case 6:
276 return STI.canUseExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes)
277 ? SPIRV::StorageClass::HostOnlyINTEL
278 : SPIRV::StorageClass::CrossWorkgroup;
279 case 7:
280 return SPIRV::StorageClass::Input;
281 case 8:
282 return SPIRV::StorageClass::Output;
283 case 9:
284 return SPIRV::StorageClass::CodeSectionINTEL;
285 case 10:
286 return SPIRV::StorageClass::Private;
287 case 11:
288 return SPIRV::StorageClass::StorageBuffer;
289 case 12:
290 return SPIRV::StorageClass::Uniform;
291 default:
292 report_fatal_error("Unknown address space");
293 }
294}
295
296SPIRV::MemorySemantics::MemorySemantics
297getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC) {
298 switch (SC) {
299 case SPIRV::StorageClass::StorageBuffer:
300 case SPIRV::StorageClass::Uniform:
301 return SPIRV::MemorySemantics::UniformMemory;
302 case SPIRV::StorageClass::Workgroup:
303 return SPIRV::MemorySemantics::WorkgroupMemory;
304 case SPIRV::StorageClass::CrossWorkgroup:
305 return SPIRV::MemorySemantics::CrossWorkgroupMemory;
306 case SPIRV::StorageClass::AtomicCounter:
307 return SPIRV::MemorySemantics::AtomicCounterMemory;
308 case SPIRV::StorageClass::Image:
309 return SPIRV::MemorySemantics::ImageMemory;
310 default:
311 return SPIRV::MemorySemantics::None;
312 }
313}
314
315SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord) {
316 switch (Ord) {
318 return SPIRV::MemorySemantics::Acquire;
320 return SPIRV::MemorySemantics::Release;
322 return SPIRV::MemorySemantics::AcquireRelease;
324 return SPIRV::MemorySemantics::SequentiallyConsistent;
328 return SPIRV::MemorySemantics::None;
329 }
330 llvm_unreachable(nullptr);
331}
332
333SPIRV::Scope::Scope getMemScope(LLVMContext &Ctx, SyncScope::ID Id) {
334 // Named by
335 // https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#_scope_id.
336 // We don't need aliases for Invocation and CrossDevice, as we already have
337 // them covered by "singlethread" and "" strings respectively (see
338 // implementation of LLVMContext::LLVMContext()).
339 static const llvm::SyncScope::ID SubGroup =
340 Ctx.getOrInsertSyncScopeID("subgroup");
341 static const llvm::SyncScope::ID WorkGroup =
342 Ctx.getOrInsertSyncScopeID("workgroup");
343 static const llvm::SyncScope::ID Device =
344 Ctx.getOrInsertSyncScopeID("device");
345
347 return SPIRV::Scope::Invocation;
348 else if (Id == llvm::SyncScope::System)
349 return SPIRV::Scope::CrossDevice;
350 else if (Id == SubGroup)
351 return SPIRV::Scope::Subgroup;
352 else if (Id == WorkGroup)
353 return SPIRV::Scope::Workgroup;
354 else if (Id == Device)
355 return SPIRV::Scope::Device;
356 return SPIRV::Scope::CrossDevice;
357}
358
360 const MachineRegisterInfo *MRI) {
361 MachineInstr *MI = MRI->getVRegDef(ConstReg);
362 MachineInstr *ConstInstr =
363 MI->getOpcode() == SPIRV::G_TRUNC || MI->getOpcode() == SPIRV::G_ZEXT
364 ? MRI->getVRegDef(MI->getOperand(1).getReg())
365 : MI;
366 if (auto *GI = dyn_cast<GIntrinsic>(ConstInstr)) {
367 if (GI->is(Intrinsic::spv_track_constant)) {
368 ConstReg = ConstInstr->getOperand(2).getReg();
369 return MRI->getVRegDef(ConstReg);
370 }
371 } else if (ConstInstr->getOpcode() == SPIRV::ASSIGN_TYPE) {
372 ConstReg = ConstInstr->getOperand(1).getReg();
373 return MRI->getVRegDef(ConstReg);
374 } else if (ConstInstr->getOpcode() == TargetOpcode::G_CONSTANT ||
375 ConstInstr->getOpcode() == TargetOpcode::G_FCONSTANT) {
376 ConstReg = ConstInstr->getOperand(0).getReg();
377 return ConstInstr;
378 }
379 return MRI->getVRegDef(ConstReg);
380}
381
383 const MachineInstr *MI = getDefInstrMaybeConstant(ConstReg, MRI);
384 assert(MI && MI->getOpcode() == TargetOpcode::G_CONSTANT);
385 return MI->getOperand(1).getCImm()->getValue().getZExtValue();
386}
387
388bool isSpvIntrinsic(const MachineInstr &MI, Intrinsic::ID IntrinsicID) {
389 if (const auto *GI = dyn_cast<GIntrinsic>(&MI))
390 return GI->is(IntrinsicID);
391 return false;
392}
393
394Type *getMDOperandAsType(const MDNode *N, unsigned I) {
395 Type *ElementTy = cast<ValueAsMetadata>(N->getOperand(I))->getType();
396 return toTypedPointer(ElementTy);
397}
398
399// The set of names is borrowed from the SPIR-V translator.
400// TODO: may be implemented in SPIRVBuiltins.td.
401static bool isPipeOrAddressSpaceCastBI(const StringRef MangledName) {
402 return MangledName == "write_pipe_2" || MangledName == "read_pipe_2" ||
403 MangledName == "write_pipe_2_bl" || MangledName == "read_pipe_2_bl" ||
404 MangledName == "write_pipe_4" || MangledName == "read_pipe_4" ||
405 MangledName == "reserve_write_pipe" ||
406 MangledName == "reserve_read_pipe" ||
407 MangledName == "commit_write_pipe" ||
408 MangledName == "commit_read_pipe" ||
409 MangledName == "work_group_reserve_write_pipe" ||
410 MangledName == "work_group_reserve_read_pipe" ||
411 MangledName == "work_group_commit_write_pipe" ||
412 MangledName == "work_group_commit_read_pipe" ||
413 MangledName == "get_pipe_num_packets_ro" ||
414 MangledName == "get_pipe_max_packets_ro" ||
415 MangledName == "get_pipe_num_packets_wo" ||
416 MangledName == "get_pipe_max_packets_wo" ||
417 MangledName == "sub_group_reserve_write_pipe" ||
418 MangledName == "sub_group_reserve_read_pipe" ||
419 MangledName == "sub_group_commit_write_pipe" ||
420 MangledName == "sub_group_commit_read_pipe" ||
421 MangledName == "to_global" || MangledName == "to_local" ||
422 MangledName == "to_private";
423}
424
425static bool isEnqueueKernelBI(const StringRef MangledName) {
426 return MangledName == "__enqueue_kernel_basic" ||
427 MangledName == "__enqueue_kernel_basic_events" ||
428 MangledName == "__enqueue_kernel_varargs" ||
429 MangledName == "__enqueue_kernel_events_varargs";
430}
431
432static bool isKernelQueryBI(const StringRef MangledName) {
433 return MangledName == "__get_kernel_work_group_size_impl" ||
434 MangledName == "__get_kernel_sub_group_count_for_ndrange_impl" ||
435 MangledName == "__get_kernel_max_sub_group_size_for_ndrange_impl" ||
436 MangledName == "__get_kernel_preferred_work_group_size_multiple_impl";
437}
438
440 if (!Name.starts_with("__"))
441 return false;
442
443 return isEnqueueKernelBI(Name) || isKernelQueryBI(Name) ||
444 isPipeOrAddressSpaceCastBI(Name.drop_front(2)) ||
445 Name == "__translate_sampler_initializer";
446}
447
449 bool IsNonMangledOCL = isNonMangledOCLBuiltin(Name);
450 bool IsNonMangledSPIRV = Name.starts_with("__spirv_");
451 bool IsNonMangledHLSL = Name.starts_with("__hlsl_");
452 bool IsMangled = Name.starts_with("_Z");
453
454 // Otherwise use simple demangling to return the function name.
455 if (IsNonMangledOCL || IsNonMangledSPIRV || IsNonMangledHLSL || !IsMangled)
456 return Name.str();
457
458 // Try to use the itanium demangler.
459 if (char *DemangledName = itaniumDemangle(Name.data())) {
460 std::string Result = DemangledName;
461 free(DemangledName);
462 return Result;
463 }
464
465 // Autocheck C++, maybe need to do explicit check of the source language.
466 // OpenCL C++ built-ins are declared in cl namespace.
467 // TODO: consider using 'St' abbriviation for cl namespace mangling.
468 // Similar to ::std:: in C++.
469 size_t Start, Len = 0;
470 size_t DemangledNameLenStart = 2;
471 if (Name.starts_with("_ZN")) {
472 // Skip CV and ref qualifiers.
473 size_t NameSpaceStart = Name.find_first_not_of("rVKRO", 3);
474 // All built-ins are in the ::cl:: namespace.
475 if (Name.substr(NameSpaceStart, 11) != "2cl7__spirv")
476 return std::string();
477 DemangledNameLenStart = NameSpaceStart + 11;
478 }
479 Start = Name.find_first_not_of("0123456789", DemangledNameLenStart);
480 [[maybe_unused]] bool Error =
481 Name.substr(DemangledNameLenStart, Start - DemangledNameLenStart)
482 .getAsInteger(10, Len);
483 assert(!Error && "Failed to parse demangled name length");
484 return Name.substr(Start, Len).str();
485}
486
488 if (Name.starts_with("opencl.") || Name.starts_with("ocl_") ||
489 Name.starts_with("spirv."))
490 return true;
491 return false;
492}
493
494bool isSpecialOpaqueType(const Type *Ty) {
495 if (const TargetExtType *ExtTy = dyn_cast<TargetExtType>(Ty))
496 return isTypedPointerWrapper(ExtTy)
497 ? false
498 : hasBuiltinTypePrefix(ExtTy->getName());
499
500 return false;
501}
502
503bool isEntryPoint(const Function &F) {
504 // OpenCL handling: any function with the SPIR_KERNEL
505 // calling convention will be a potential entry point.
506 if (F.getCallingConv() == CallingConv::SPIR_KERNEL)
507 return true;
508
509 // HLSL handling: special attribute are emitted from the
510 // front-end.
511 if (F.getFnAttribute("hlsl.shader").isValid())
512 return true;
513
514 return false;
515}
516
518 TypeName.consume_front("atomic_");
519 if (TypeName.consume_front("void"))
520 return Type::getVoidTy(Ctx);
521 else if (TypeName.consume_front("bool") || TypeName.consume_front("_Bool"))
522 return Type::getIntNTy(Ctx, 1);
523 else if (TypeName.consume_front("char") ||
524 TypeName.consume_front("signed char") ||
525 TypeName.consume_front("unsigned char") ||
526 TypeName.consume_front("uchar"))
527 return Type::getInt8Ty(Ctx);
528 else if (TypeName.consume_front("short") ||
529 TypeName.consume_front("signed short") ||
530 TypeName.consume_front("unsigned short") ||
531 TypeName.consume_front("ushort"))
532 return Type::getInt16Ty(Ctx);
533 else if (TypeName.consume_front("int") ||
534 TypeName.consume_front("signed int") ||
535 TypeName.consume_front("unsigned int") ||
536 TypeName.consume_front("uint"))
537 return Type::getInt32Ty(Ctx);
538 else if (TypeName.consume_front("long") ||
539 TypeName.consume_front("signed long") ||
540 TypeName.consume_front("unsigned long") ||
541 TypeName.consume_front("ulong"))
542 return Type::getInt64Ty(Ctx);
543 else if (TypeName.consume_front("half") ||
544 TypeName.consume_front("_Float16") ||
545 TypeName.consume_front("__fp16"))
546 return Type::getHalfTy(Ctx);
547 else if (TypeName.consume_front("float"))
548 return Type::getFloatTy(Ctx);
549 else if (TypeName.consume_front("double"))
550 return Type::getDoubleTy(Ctx);
551
552 // Unable to recognize SPIRV type name
553 return nullptr;
554}
555
556std::unordered_set<BasicBlock *>
557PartialOrderingVisitor::getReachableFrom(BasicBlock *Start) {
558 std::queue<BasicBlock *> ToVisit;
559 ToVisit.push(Start);
560
561 std::unordered_set<BasicBlock *> Output;
562 while (ToVisit.size() != 0) {
563 BasicBlock *BB = ToVisit.front();
564 ToVisit.pop();
565
566 if (Output.count(BB) != 0)
567 continue;
568 Output.insert(BB);
569
570 for (BasicBlock *Successor : successors(BB)) {
571 if (DT.dominates(Successor, BB))
572 continue;
573 ToVisit.push(Successor);
574 }
575 }
576
577 return Output;
578}
579
580bool PartialOrderingVisitor::CanBeVisited(BasicBlock *BB) const {
581 for (BasicBlock *P : predecessors(BB)) {
582 // Ignore back-edges.
583 if (DT.dominates(BB, P))
584 continue;
585
586 // One of the predecessor hasn't been visited. Not ready yet.
587 if (BlockToOrder.count(P) == 0)
588 return false;
589
590 // If the block is a loop exit, the loop must be finished before
591 // we can continue.
592 Loop *L = LI.getLoopFor(P);
593 if (L == nullptr || L->contains(BB))
594 continue;
595
596 // SPIR-V requires a single back-edge. And the backend first
597 // step transforms loops into the simplified format. If we have
598 // more than 1 back-edge, something is wrong.
599 assert(L->getNumBackEdges() <= 1);
600
601 // If the loop has no latch, loop's rank won't matter, so we can
602 // proceed.
603 BasicBlock *Latch = L->getLoopLatch();
604 assert(Latch);
605 if (Latch == nullptr)
606 continue;
607
608 // The latch is not ready yet, let's wait.
609 if (BlockToOrder.count(Latch) == 0)
610 return false;
611 }
612
613 return true;
614}
615
617 auto It = BlockToOrder.find(BB);
618 if (It != BlockToOrder.end())
619 return It->second.Rank;
620
621 size_t result = 0;
622 for (BasicBlock *P : predecessors(BB)) {
623 // Ignore back-edges.
624 if (DT.dominates(BB, P))
625 continue;
626
627 auto Iterator = BlockToOrder.end();
628 Loop *L = LI.getLoopFor(P);
629 BasicBlock *Latch = L ? L->getLoopLatch() : nullptr;
630
631 // If the predecessor is either outside a loop, or part of
632 // the same loop, simply take its rank + 1.
633 if (L == nullptr || L->contains(BB) || Latch == nullptr) {
634 Iterator = BlockToOrder.find(P);
635 } else {
636 // Otherwise, take the loop's rank (highest rank in the loop) as base.
637 // Since loops have a single latch, highest rank is easy to find.
638 // If the loop has no latch, then it doesn't matter.
639 Iterator = BlockToOrder.find(Latch);
640 }
641
642 assert(Iterator != BlockToOrder.end());
643 result = std::max(result, Iterator->second.Rank + 1);
644 }
645
646 return result;
647}
648
649size_t PartialOrderingVisitor::visit(BasicBlock *BB, size_t Unused) {
650 ToVisit.push(BB);
651 Queued.insert(BB);
652
653 size_t QueueIndex = 0;
654 while (ToVisit.size() != 0) {
655 BasicBlock *BB = ToVisit.front();
656 ToVisit.pop();
657
658 if (!CanBeVisited(BB)) {
659 ToVisit.push(BB);
660 if (QueueIndex >= ToVisit.size())
662 "No valid candidate in the queue. Is the graph reducible?");
663 QueueIndex++;
664 continue;
665 }
666
667 QueueIndex = 0;
668 size_t Rank = GetNodeRank(BB);
669 OrderInfo Info = {Rank, BlockToOrder.size()};
670 BlockToOrder.emplace(BB, Info);
671
672 for (BasicBlock *S : successors(BB)) {
673 if (Queued.count(S) != 0)
674 continue;
675 ToVisit.push(S);
676 Queued.insert(S);
677 }
678 }
679
680 return 0;
681}
682
684 DT.recalculate(F);
685 LI = LoopInfo(DT);
686
687 visit(&*F.begin(), 0);
688
689 Order.reserve(F.size());
690 for (auto &[BB, Info] : BlockToOrder)
691 Order.emplace_back(BB);
692
693 std::sort(Order.begin(), Order.end(), [&](const auto &LHS, const auto &RHS) {
694 return compare(LHS, RHS);
695 });
696}
697
699 const BasicBlock *RHS) const {
700 const OrderInfo &InfoLHS = BlockToOrder.at(const_cast<BasicBlock *>(LHS));
701 const OrderInfo &InfoRHS = BlockToOrder.at(const_cast<BasicBlock *>(RHS));
702 if (InfoLHS.Rank != InfoRHS.Rank)
703 return InfoLHS.Rank < InfoRHS.Rank;
704 return InfoLHS.TraversalIndex < InfoRHS.TraversalIndex;
705}
706
708 BasicBlock &Start, std::function<bool(BasicBlock *)> Op) {
709 std::unordered_set<BasicBlock *> Reachable = getReachableFrom(&Start);
710 assert(BlockToOrder.count(&Start) != 0);
711
712 // Skipping blocks with a rank inferior to |Start|'s rank.
713 auto It = Order.begin();
714 while (It != Order.end() && *It != &Start)
715 ++It;
716
717 // This is unexpected. Worst case |Start| is the last block,
718 // so It should point to the last block, not past-end.
719 assert(It != Order.end());
720
721 // By default, there is no rank limit. Setting it to the maximum value.
722 std::optional<size_t> EndRank = std::nullopt;
723 for (; It != Order.end(); ++It) {
724 if (EndRank.has_value() && BlockToOrder[*It].Rank > *EndRank)
725 break;
726
727 if (Reachable.count(*It) == 0) {
728 continue;
729 }
730
731 if (!Op(*It)) {
732 EndRank = BlockToOrder[*It].Rank;
733 }
734 }
735}
736
738 if (F.size() == 0)
739 return false;
740
741 bool Modified = false;
742 std::vector<BasicBlock *> Order;
743 Order.reserve(F.size());
744
746 llvm::append_range(Order, RPOT);
747
748 assert(&*F.begin() == Order[0]);
749 BasicBlock *LastBlock = &*F.begin();
750 for (BasicBlock *BB : Order) {
751 if (BB != LastBlock && &*LastBlock->getNextNode() != BB) {
752 Modified = true;
753 BB->moveAfter(LastBlock);
754 }
755 LastBlock = BB;
756 }
757
758 return Modified;
759}
760
762 MachineInstr *MaybeDef = MRI.getVRegDef(Reg);
763 if (MaybeDef && MaybeDef->getOpcode() == SPIRV::ASSIGN_TYPE)
764 MaybeDef = MRI.getVRegDef(MaybeDef->getOperand(1).getReg());
765 return MaybeDef;
766}
767
768bool getVacantFunctionName(Module &M, std::string &Name) {
769 // It's a bit of paranoia, but still we don't want to have even a chance that
770 // the loop will work for too long.
771 constexpr unsigned MaxIters = 1024;
772 for (unsigned I = 0; I < MaxIters; ++I) {
773 std::string OrdName = Name + Twine(I).str();
774 if (!M.getFunction(OrdName)) {
775 Name = std::move(OrdName);
776 return true;
777 }
778 }
779 return false;
780}
781
782// Assign SPIR-V type to the register. If the register has no valid assigned
783// class, set register LLT type and class according to the SPIR-V type.
786 bool Force) {
787 GR->assignSPIRVTypeToVReg(SpvType, Reg, MF);
788 if (!MRI->getRegClassOrNull(Reg) || Force) {
789 MRI->setRegClass(Reg, GR->getRegClass(SpvType));
790 MRI->setType(Reg, GR->getRegType(SpvType));
791 }
792}
793
794// Create a SPIR-V type, assign SPIR-V type to the register. If the register has
795// no valid assigned class, set register LLT type and class according to the
796// SPIR-V type.
798 MachineIRBuilder &MIRBuilder,
799 SPIRV::AccessQualifier::AccessQualifier AccessQual,
800 bool EmitIR, bool Force) {
802 GR->getOrCreateSPIRVType(Ty, MIRBuilder, AccessQual, EmitIR),
803 GR, MIRBuilder.getMRI(), MIRBuilder.getMF(), Force);
804}
805
806// Create a virtual register and assign SPIR-V type to the register. Set
807// register LLT type and class according to the SPIR-V type.
810 const MachineFunction &MF) {
811 Register Reg = MRI->createVirtualRegister(GR->getRegClass(SpvType));
812 MRI->setType(Reg, GR->getRegType(SpvType));
813 GR->assignSPIRVTypeToVReg(SpvType, Reg, MF);
814 return Reg;
815}
816
817// Create a virtual register and assign SPIR-V type to the register. Set
818// register LLT type and class according to the SPIR-V type.
820 MachineIRBuilder &MIRBuilder) {
821 return createVirtualRegister(SpvType, GR, MIRBuilder.getMRI(),
822 MIRBuilder.getMF());
823}
824
825// Create a SPIR-V type, virtual register and assign SPIR-V type to the
826// register. Set register LLT type and class according to the SPIR-V type.
828 const Type *Ty, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIRBuilder,
829 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
831 GR->getOrCreateSPIRVType(Ty, MIRBuilder, AccessQual, EmitIR), GR,
832 MIRBuilder);
833}
834
836 Value *Arg, Value *Arg2, ArrayRef<Constant *> Imms,
837 IRBuilder<> &B) {
839 Args.push_back(Arg2);
840 Args.push_back(buildMD(Arg));
841 llvm::append_range(Args, Imms);
842 return B.CreateIntrinsic(IntrID, {Types}, Args);
843}
844
845// Return true if there is an opaque pointer type nested in the argument.
846bool isNestedPointer(const Type *Ty) {
847 if (Ty->isPtrOrPtrVectorTy())
848 return true;
849 if (const FunctionType *RefTy = dyn_cast<FunctionType>(Ty)) {
850 if (isNestedPointer(RefTy->getReturnType()))
851 return true;
852 for (const Type *ArgTy : RefTy->params())
853 if (isNestedPointer(ArgTy))
854 return true;
855 return false;
856 }
857 if (const ArrayType *RefTy = dyn_cast<ArrayType>(Ty))
858 return isNestedPointer(RefTy->getElementType());
859 return false;
860}
861
862bool isSpvIntrinsic(const Value *Arg) {
863 if (const auto *II = dyn_cast<IntrinsicInst>(Arg))
864 if (Function *F = II->getCalledFunction())
865 if (F->getName().starts_with("llvm.spv."))
866 return true;
867 return false;
868}
869
870// Function to create continued instructions for SPV_INTEL_long_composites
871// extension
872SmallVector<MachineInstr *, 4>
874 unsigned MinWC, unsigned ContinuedOpcode,
875 ArrayRef<Register> Args, Register ReturnRegister,
877
879 constexpr unsigned MaxWordCount = UINT16_MAX;
880 const size_t NumElements = Args.size();
881 size_t MaxNumElements = MaxWordCount - MinWC;
882 size_t SPIRVStructNumElements = NumElements;
883
884 if (NumElements > MaxNumElements) {
885 // Do adjustments for continued instructions which always had only one
886 // minumum word count.
887 SPIRVStructNumElements = MaxNumElements;
888 MaxNumElements = MaxWordCount - 1;
889 }
890
891 auto MIB =
892 MIRBuilder.buildInstr(Opcode).addDef(ReturnRegister).addUse(TypeID);
893
894 for (size_t I = 0; I < SPIRVStructNumElements; ++I)
895 MIB.addUse(Args[I]);
896
897 Instructions.push_back(MIB.getInstr());
898
899 for (size_t I = SPIRVStructNumElements; I < NumElements;
900 I += MaxNumElements) {
901 auto MIB = MIRBuilder.buildInstr(ContinuedOpcode);
902 for (size_t J = I; J < std::min(I + MaxNumElements, NumElements); ++J)
903 MIB.addUse(Args[J]);
904 Instructions.push_back(MIB.getInstr());
905 }
906 return Instructions;
907}
908
910 unsigned LC = SPIRV::LoopControl::None;
911 // Currently used only to store PartialCount value. Later when other
912 // LoopControls are added - this map should be sorted before making
913 // them loop_merge operands to satisfy 3.23. Loop Control requirements.
914 std::vector<std::pair<unsigned, unsigned>> MaskToValueMap;
915 if (getBooleanLoopAttribute(L, "llvm.loop.unroll.disable")) {
916 LC |= SPIRV::LoopControl::DontUnroll;
917 } else {
918 if (getBooleanLoopAttribute(L, "llvm.loop.unroll.enable") ||
919 getBooleanLoopAttribute(L, "llvm.loop.unroll.full")) {
920 LC |= SPIRV::LoopControl::Unroll;
921 }
922 std::optional<int> Count =
923 getOptionalIntLoopAttribute(L, "llvm.loop.unroll.count");
924 if (Count && Count != 1) {
925 LC |= SPIRV::LoopControl::PartialCount;
926 MaskToValueMap.emplace_back(
927 std::make_pair(SPIRV::LoopControl::PartialCount, *Count));
928 }
929 }
930 SmallVector<unsigned, 1> Result = {LC};
931 for (auto &[Mask, Val] : MaskToValueMap)
932 Result.push_back(Val);
933 return Result;
934}
935
936const std::set<unsigned> &getTypeFoldingSupportedOpcodes() {
937 // clang-format off
938 static const std::set<unsigned> TypeFoldingSupportingOpcs = {
939 TargetOpcode::G_ADD,
940 TargetOpcode::G_FADD,
941 TargetOpcode::G_STRICT_FADD,
942 TargetOpcode::G_SUB,
943 TargetOpcode::G_FSUB,
944 TargetOpcode::G_STRICT_FSUB,
945 TargetOpcode::G_MUL,
946 TargetOpcode::G_FMUL,
947 TargetOpcode::G_STRICT_FMUL,
948 TargetOpcode::G_SDIV,
949 TargetOpcode::G_UDIV,
950 TargetOpcode::G_FDIV,
951 TargetOpcode::G_STRICT_FDIV,
952 TargetOpcode::G_SREM,
953 TargetOpcode::G_UREM,
954 TargetOpcode::G_FREM,
955 TargetOpcode::G_STRICT_FREM,
956 TargetOpcode::G_FNEG,
957 TargetOpcode::G_CONSTANT,
958 TargetOpcode::G_FCONSTANT,
959 TargetOpcode::G_AND,
960 TargetOpcode::G_OR,
961 TargetOpcode::G_XOR,
962 TargetOpcode::G_SHL,
963 TargetOpcode::G_ASHR,
964 TargetOpcode::G_LSHR,
965 TargetOpcode::G_SELECT,
966 TargetOpcode::G_EXTRACT_VECTOR_ELT,
967 };
968 // clang-format on
969 return TypeFoldingSupportingOpcs;
970}
971
972bool isTypeFoldingSupported(unsigned Opcode) {
973 return getTypeFoldingSupportedOpcodes().count(Opcode) > 0;
974}
975
976// Traversing [g]MIR accounting for pseudo-instructions.
978 return (Def->getOpcode() == SPIRV::ASSIGN_TYPE ||
979 Def->getOpcode() == TargetOpcode::COPY)
980 ? MRI->getVRegDef(Def->getOperand(1).getReg())
981 : Def;
982}
983
985 if (MachineInstr *Def = MRI->getVRegDef(MO.getReg()))
986 return passCopy(Def, MRI);
987 return nullptr;
988}
989
991 if (MachineInstr *Def = getDef(MO, MRI)) {
992 if (Def->getOpcode() == TargetOpcode::G_CONSTANT ||
993 Def->getOpcode() == SPIRV::OpConstantI)
994 return Def;
995 }
996 return nullptr;
997}
998
999int64_t foldImm(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
1000 if (MachineInstr *Def = getImm(MO, MRI)) {
1001 if (Def->getOpcode() == SPIRV::OpConstantI)
1002 return Def->getOperand(2).getImm();
1003 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1004 return Def->getOperand(1).getCImm()->getZExtValue();
1005 }
1006 llvm_unreachable("Unexpected integer constant pattern");
1007}
1008
1010 const MachineInstr *ResType) {
1011 return foldImm(ResType->getOperand(2), MRI);
1012}
1013
1016 // Find the position to insert the OpVariable instruction.
1017 // We will insert it after the last OpFunctionParameter, if any, or
1018 // after OpFunction otherwise.
1019 MachineBasicBlock::iterator VarPos = BB.begin();
1020 while (VarPos != BB.end() && VarPos->getOpcode() != SPIRV::OpFunction) {
1021 ++VarPos;
1022 }
1023 // Advance VarPos to the next instruction after OpFunction, it will either
1024 // be an OpFunctionParameter, so that we can start the next loop, or the
1025 // position to insert the OpVariable instruction.
1026 ++VarPos;
1027 while (VarPos != BB.end() &&
1028 VarPos->getOpcode() == SPIRV::OpFunctionParameter) {
1029 ++VarPos;
1030 }
1031 // VarPos is now pointing at after the last OpFunctionParameter, if any,
1032 // or after OpFunction, if no parameters.
1033 return VarPos != BB.end() && VarPos->getOpcode() == SPIRV::OpLabel ? ++VarPos
1034 : VarPos;
1035}
1036
1037} // namespace llvm
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock & MBB
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition CSEInfo.cpp:27
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition MD5.cpp:55
#define I(x, y, z)
Definition MD5.cpp:58
This file declares the MachineIRBuilder class.
Register Reg
Type::TypeID TypeID
uint64_t IntrinsicInst * II
#define P(N)
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
Class to represent array types.
LLVM Basic Block Representation.
Definition BasicBlock.h:62
LLVM_ABI void moveAfter(BasicBlock *MovePos)
Unlink this basic block from its current function and insert it right after MovePos in the function M...
const Instruction & front() const
Definition BasicBlock.h:482
This class represents a function call, abstracting a target machine's calling convention.
An array constant whose element type is a simple 1/2/4/8-byte integer or float/double,...
Definition Constants.h:702
StringRef getAsCString() const
If this array is isCString(), then this method returns the array (without the trailing null byte) as ...
Definition Constants.h:675
This is the shared class of boolean and integer constants.
Definition Constants.h:87
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition Constants.h:163
bool dominates(const DomTreeNodeBase< NodeT > *A, const DomTreeNodeBase< NodeT > *B) const
dominates - Returns true iff A dominates B.
Lightweight error class with error context and mandatory checking.
Definition Error.h:159
Class to represent function types.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition IRBuilder.h:2780
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
void addOperand(const MCOperand Op)
Definition MCInst.h:215
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
Metadata node.
Definition Metadata.h:1078
const MDOperand & getOperand(unsigned I) const
Definition Metadata.h:1442
unsigned getNumOperands() const
Return number of MDNode operands.
Definition Metadata.h:1448
A single uniqued string.
Definition Metadata.h:721
MachineInstrBundleIterator< MachineInstr > iterator
const MachineBasicBlock & front() const
Helper class to build MachineInstr.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
MachineRegisterInfo * getMRI()
Getter for MRI.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition Module.h:67
size_t GetNodeRank(BasicBlock *BB) const
void partialOrderVisit(BasicBlock &Start, std::function< bool(BasicBlock *)> Op)
bool compare(const BasicBlock *LHS, const BasicBlock *RHS) const
Wrapper class representing virtual and physical registers.
Definition Register.h:19
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, const MachineFunction &MF)
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineInstr &I, SPIRV::AccessQualifier::AccessQualifier AQ, bool EmitIR)
const TargetRegisterClass * getRegClass(SPIRVType *SpvType) const
LLT getRegType(SPIRVType *SpvType) const
bool canUseExtension(SPIRV::Extension::Extension E) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
std::string str() const
str - Get the contents as an std::string.
Definition StringRef.h:225
constexpr bool empty() const
empty - Check if the string is empty.
Definition StringRef.h:143
Class to represent target extensions types, which are generally unintrospectable from target-independ...
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition Twine.h:82
LLVM_ABI std::string str() const
Return the twine contents as a std::string.
Definition Twine.cpp:17
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
static LLVM_ABI IntegerType * getInt64Ty(LLVMContext &C)
Definition Type.cpp:298
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
Definition Type.cpp:297
static LLVM_ABI Type * getVoidTy(LLVMContext &C)
Definition Type.cpp:281
static LLVM_ABI IntegerType * getInt8Ty(LLVMContext &C)
Definition Type.cpp:295
static LLVM_ABI IntegerType * getInt16Ty(LLVMContext &C)
Definition Type.cpp:296
static LLVM_ABI IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition Type.cpp:301
static LLVM_ABI Type * getDoubleTy(LLVMContext &C)
Definition Type.cpp:286
static LLVM_ABI Type * getFloatTy(LLVMContext &C)
Definition Type.cpp:285
static LLVM_ABI Type * getHalfTy(LLVMContext &C)
Definition Type.cpp:283
Value * getOperand(unsigned i) const
Definition User.h:232
LLVM Value Representation.
Definition Value.h:75
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition ilist_node.h:348
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SPIR_KERNEL
Used for SPIR kernel functions.
@ BasicBlock
Various leaf nodes.
Definition ISDOpcodes.h:81
@ SingleThread
Synchronized with respect to signal handlers executing in the same thread.
Definition LLVMContext.h:55
@ System
Synchronized with respect to all concurrently executing threads.
Definition LLVMContext.h:58
std::enable_if_t< detail::IsValidPointer< X, Y >::value, X * > dyn_extract(Y &&MD)
Extract a Value from Metadata, if any.
Definition Metadata.h:695
This is an optimization pass for GlobalISel generic memory operations.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
bool getVacantFunctionName(Module &M, std::string &Name)
std::string getStringImm(const MachineInstr &MI, unsigned StartIndex)
LLVM_ABI bool getBooleanLoopAttribute(const Loop *TheLoop, StringRef Name)
Returns true if Name is applied to TheLoop and enabled.
bool isTypedPointerWrapper(const TargetExtType *ExtTy)
Definition SPIRVUtils.h:378
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static void finishBuildOpDecorate(MachineInstrBuilder &MIB, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
bool isTypeFoldingSupported(unsigned Opcode)
static uint32_t convertCharsToWord(const StringRef &Str, unsigned i)
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:644
MachineInstr * getDef(const MachineOperand &MO, const MachineRegisterInfo *MRI)
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
auto successors(const MachineBasicBlock *BB)
CallInst * buildIntrWithMD(Intrinsic::ID IntrID, ArrayRef< Type * > Types, Value *Arg, Value *Arg2, ArrayRef< Constant * > Imms, IRBuilder<> &B)
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition STLExtras.h:2116
unsigned getArrayComponentCount(const MachineRegisterInfo *MRI, const MachineInstr *ResType)
bool sortBlocks(Function &F)
SmallVector< unsigned, 1 > getSpirvLoopControlOperandsFromLoopMetadata(Loop *L)
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
SmallVector< MachineInstr *, 4 > createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode, unsigned MinWC, unsigned ContinuedOpcode, ArrayRef< Register > Args, Register ReturnRegister, Register TypeID)
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
MachineBasicBlock::iterator getFirstValidInstructionInsertPoint(MachineBasicBlock &BB)
bool isNestedPointer(const Type *Ty)
MetadataAsValue * buildMD(Value *Arg)
Definition SPIRVUtils.h:488
std::string getOclOrSpirvBuiltinDemangledName(StringRef Name)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
MachineBasicBlock::iterator getOpVariableMBBIt(MachineInstr &I)
Register createVirtualRegister(SPIRVType *SpvType, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI, const MachineFunction &MF)
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
std::string getSPIRVStringOperand(const InstType &MI, unsigned StartIndex)
void buildOpMemberDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, uint32_t Member, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
Type * toTypedPointer(Type *Ty)
Definition SPIRVUtils.h:433
DEMANGLE_ABI char * itaniumDemangle(std::string_view mangled_name, bool ParseParams=true)
Returns a non-NULL pointer to a NUL-terminated C style string that should be explicitly freed,...
bool isSpecialOpaqueType(const Type *Ty)
void setRegClassType(Register Reg, SPIRVType *SpvType, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI, const MachineFunction &MF, bool Force)
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:167
MachineBasicBlock::iterator getInsertPtValidEnd(MachineBasicBlock *MBB)
FunctionAddr VTableAddr Count
Definition InstrProf.h:139
const MachineInstr SPIRVType
static bool isNonMangledOCLBuiltin(StringRef Name)
MachineInstr * passCopy(MachineInstr *Def, const MachineRegisterInfo *MRI)
bool isEntryPoint(const Function &F)
const std::set< unsigned > & getTypeFoldingSupportedOpcodes()
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI)
LLVM_ABI std::optional< int > getOptionalIntLoopAttribute(const Loop *TheLoop, StringRef Name)
Find named metadata for a loop with an integer value.
AtomicOrdering
Atomic ordering for LLVM's memory model.
SPIRV::Scope::Scope getMemScope(LLVMContext &Ctx, SyncScope::ID Id)
static bool isPipeOrAddressSpaceCastBI(const StringRef MangledName)
void buildOpSpirvDecorations(Register Reg, MachineIRBuilder &MIRBuilder, const MDNode *GVarMD, const SPIRVSubtarget &ST)
std::string getStringValueFromReg(Register Reg, MachineRegisterInfo &MRI)
int64_t foldImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Type * parseBasicTypeName(StringRef &TypeName, LLVMContext &Ctx)
DWARFExpression::Operation Op
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:560
bool hasBuiltinTypePrefix(StringRef Name)
Type * getMDOperandAsType(const MDNode *N, unsigned I)
auto predecessors(const MachineBasicBlock *BB)
static size_t getPaddedLen(const StringRef &Str)
bool isSpvIntrinsic(const MachineInstr &MI, Intrinsic::ID IntrinsicID)
void addStringImm(const StringRef &Str, MCInst &Inst)
static bool isKernelQueryBI(const StringRef MangledName)
MachineInstr * getVRegDef(MachineRegisterInfo &MRI, Register Reg)
static bool isEnqueueKernelBI(const StringRef MangledName)
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord)
#define N