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TargetTransformInfo.h
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1//===- TargetTransformInfo.h ------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This pass exposes codegen information to IR-level passes. Every
10/// transformation that uses codegen information is broken into three parts:
11/// 1. The IR-level analysis pass.
12/// 2. The IR-level transformation interface which provides the needed
13/// information.
14/// 3. Codegen-level implementation which uses target-specific hooks.
15///
16/// This file defines #2, which is the interface that IR-level transformations
17/// use for querying the codegen.
18///
19//===----------------------------------------------------------------------===//
20
21#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
22#define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
23
24#include "llvm/ADT/APInt.h"
25#include "llvm/ADT/ArrayRef.h"
29#include "llvm/IR/FMF.h"
30#include "llvm/IR/InstrTypes.h"
31#include "llvm/IR/PassManager.h"
32#include "llvm/Pass.h"
37#include <functional>
38#include <optional>
39#include <utility>
40
41namespace llvm {
42
43namespace Intrinsic {
44typedef unsigned ID;
45}
46
47class AllocaInst;
48class AssumptionCache;
50class DominatorTree;
51class BranchInst;
52class Function;
53class GlobalValue;
54class InstCombiner;
57class IntrinsicInst;
58class LoadInst;
59class Loop;
60class LoopInfo;
64class SCEV;
65class ScalarEvolution;
66class SmallBitVector;
67class StoreInst;
68class SwitchInst;
70class Type;
71class VPIntrinsic;
72struct KnownBits;
73
74/// Information about a load/store intrinsic defined by the target.
76 /// This is the pointer that the intrinsic is loading from or storing to.
77 /// If this is non-null, then analysis/optimization passes can assume that
78 /// this intrinsic is functionally equivalent to a load/store from this
79 /// pointer.
80 Value *PtrVal = nullptr;
81
82 // Ordering for atomic operations.
84
85 // Same Id is set by the target for corresponding load/store intrinsics.
86 unsigned short MatchingId = 0;
87
88 bool ReadMem = false;
89 bool WriteMem = false;
90 bool IsVolatile = false;
91
93
99};
100
101/// Attributes of a target dependent hardware loop.
105 Loop *L = nullptr;
108 const SCEV *ExitCount = nullptr;
110 Value *LoopDecrement = nullptr; // Decrement the loop counter by this
111 // value in every iteration.
112 bool IsNestingLegal = false; // Can a hardware loop be a parent to
113 // another hardware loop?
114 bool CounterInReg = false; // Should loop counter be updated in
115 // the loop via a phi?
116 bool PerformEntryTest = false; // Generate the intrinsic which also performs
117 // icmp ne zero on the loop counter value and
118 // produces an i1 to guard the loop entry.
120 DominatorTree &DT,
121 bool ForceNestedLoop = false,
122 bool ForceHardwareLoopPHI = false);
123 LLVM_ABI bool canAnalyze(LoopInfo &LI);
124};
125
127 const IntrinsicInst *II = nullptr;
128 Type *RetTy = nullptr;
129 Intrinsic::ID IID;
130 SmallVector<Type *, 4> ParamTys;
132 FastMathFlags FMF;
133 // If ScalarizationCost is UINT_MAX, the cost of scalarizing the
134 // arguments and the return value will be computed based on types.
135 InstructionCost ScalarizationCost = InstructionCost::getInvalid();
136 TargetLibraryInfo const *LibInfo = nullptr;
137
138public:
140 Intrinsic::ID Id, const CallBase &CI,
142 bool TypeBasedOnly = false, TargetLibraryInfo const *LibInfo = nullptr);
143
145 Intrinsic::ID Id, Type *RTy, ArrayRef<Type *> Tys,
146 FastMathFlags Flags = FastMathFlags(), const IntrinsicInst *I = nullptr,
148
151
155 const IntrinsicInst *I = nullptr,
157 TargetLibraryInfo const *LibInfo = nullptr);
158
159 Intrinsic::ID getID() const { return IID; }
160 const IntrinsicInst *getInst() const { return II; }
161 Type *getReturnType() const { return RetTy; }
162 FastMathFlags getFlags() const { return FMF; }
163 InstructionCost getScalarizationCost() const { return ScalarizationCost; }
164 const SmallVectorImpl<const Value *> &getArgs() const { return Arguments; }
165 const SmallVectorImpl<Type *> &getArgTypes() const { return ParamTys; }
166 const TargetLibraryInfo *getLibInfo() const { return LibInfo; }
167
168 bool isTypeBasedOnly() const {
169 return Arguments.empty();
170 }
171
172 bool skipScalarizationCost() const { return ScalarizationCost.isValid(); }
173};
174
176 /// Don't use tail folding
178 /// Use predicate only to mask operations on data in the loop.
179 /// When the VL is not known to be a power-of-2, this method requires a
180 /// runtime overflow check for the i + VL in the loop because it compares the
181 /// scalar induction variable against the tripcount rounded up by VL which may
182 /// overflow. When the VL is a power-of-2, both the increment and uprounded
183 /// tripcount will overflow to 0, which does not require a runtime check
184 /// since the loop is exited when the loop induction variable equals the
185 /// uprounded trip-count, which are both 0.
187 /// Same as Data, but avoids using the get.active.lane.mask intrinsic to
188 /// calculate the mask and instead implements this with a
189 /// splat/stepvector/cmp.
190 /// FIXME: Can this kind be removed now that SelectionDAGBuilder expands the
191 /// active.lane.mask intrinsic when it is not natively supported?
193 /// Use predicate to control both data and control flow.
194 /// This method always requires a runtime overflow check for the i + VL
195 /// increment inside the loop, because it uses the result direclty in the
196 /// active.lane.mask to calculate the mask for the next iteration. If the
197 /// increment overflows, the mask is no longer correct.
199 /// Use predicate to control both data and control flow, but modify
200 /// the trip count so that a runtime overflow check can be avoided
201 /// and such that the scalar epilogue loop can always be removed.
203 /// Use predicated EVL instructions for tail-folding.
204 /// Indicates that VP intrinsics should be used.
206};
207
216
217class TargetTransformInfo;
220
221/// This pass provides access to the codegen interfaces that are needed
222/// for IR-level transformations.
224public:
226
227 /// Get the kind of extension that an instruction represents.
230
231 /// Construct a TTI object using a type implementing the \c Concept
232 /// API below.
233 ///
234 /// This is used by targets to construct a TTI wrapping their target-specific
235 /// implementation that encodes appropriate costs for their target.
237 std::unique_ptr<const TargetTransformInfoImplBase> Impl);
238
239 /// Construct a baseline TTI object using a minimal implementation of
240 /// the \c Concept API below.
241 ///
242 /// The TTI implementation will reflect the information in the DataLayout
243 /// provided if non-null.
244 LLVM_ABI explicit TargetTransformInfo(const DataLayout &DL);
245
246 // Provide move semantics.
249
250 // We need to define the destructor out-of-line to define our sub-classes
251 // out-of-line.
253
254 /// Handle the invalidation of this information.
255 ///
256 /// When used as a result of \c TargetIRAnalysis this method will be called
257 /// when the function this was computed for changes. When it returns false,
258 /// the information is preserved across those changes.
260 FunctionAnalysisManager::Invalidator &) {
261 // FIXME: We should probably in some way ensure that the subtarget
262 // information for a function hasn't changed.
263 return false;
264 }
265
266 /// \name Generic Target Information
267 /// @{
268
269 /// The kind of cost model.
270 ///
271 /// There are several different cost models that can be customized by the
272 /// target. The normalization of each cost model may be target specific.
273 /// e.g. TCK_SizeAndLatency should be comparable to target thresholds such as
274 /// those derived from MCSchedModel::LoopMicroOpBufferSize etc.
276 TCK_RecipThroughput, ///< Reciprocal throughput.
277 TCK_Latency, ///< The latency of instruction.
278 TCK_CodeSize, ///< Instruction code size.
279 TCK_SizeAndLatency ///< The weighted sum of size and latency.
280 };
281
282 /// Underlying constants for 'cost' values in this interface.
283 ///
284 /// Many APIs in this interface return a cost. This enum defines the
285 /// fundamental values that should be used to interpret (and produce) those
286 /// costs. The costs are returned as an int rather than a member of this
287 /// enumeration because it is expected that the cost of one IR instruction
288 /// may have a multiplicative factor to it or otherwise won't fit directly
289 /// into the enum. Moreover, it is common to sum or average costs which works
290 /// better as simple integral values. Thus this enum only provides constants.
291 /// Also note that the returned costs are signed integers to make it natural
292 /// to add, subtract, and test with zero (a common boundary condition). It is
293 /// not expected that 2^32 is a realistic cost to be modeling at any point.
294 ///
295 /// Note that these costs should usually reflect the intersection of code-size
296 /// cost and execution cost. A free instruction is typically one that folds
297 /// into another instruction. For example, reg-to-reg moves can often be
298 /// skipped by renaming the registers in the CPU, but they still are encoded
299 /// and thus wouldn't be considered 'free' here.
301 TCC_Free = 0, ///< Expected to fold away in lowering.
302 TCC_Basic = 1, ///< The cost of a typical 'add' instruction.
303 TCC_Expensive = 4 ///< The cost of a 'div' instruction on x86.
304 };
305
306 /// Estimate the cost of a GEP operation when lowered.
307 ///
308 /// \p PointeeType is the source element type of the GEP.
309 /// \p Ptr is the base pointer operand.
310 /// \p Operands is the list of indices following the base pointer.
311 ///
312 /// \p AccessType is a hint as to what type of memory might be accessed by
313 /// users of the GEP. getGEPCost will use it to determine if the GEP can be
314 /// folded into the addressing mode of a load/store. If AccessType is null,
315 /// then the resulting target type based off of PointeeType will be used as an
316 /// approximation.
318 getGEPCost(Type *PointeeType, const Value *Ptr,
319 ArrayRef<const Value *> Operands, Type *AccessType = nullptr,
320 TargetCostKind CostKind = TCK_SizeAndLatency) const;
321
322 /// Describe known properties for a set of pointers.
324 /// All the GEPs in a set have same base address.
325 unsigned IsSameBaseAddress : 1;
326 /// These properties only valid if SameBaseAddress is set.
327 /// True if all pointers are separated by a unit stride.
328 unsigned IsUnitStride : 1;
329 /// True if distance between any two neigbouring pointers is a known value.
330 unsigned IsKnownStride : 1;
331 unsigned Reserved : 29;
332
333 bool isSameBase() const { return IsSameBaseAddress; }
334 bool isUnitStride() const { return IsSameBaseAddress && IsUnitStride; }
336
338 return {/*IsSameBaseAddress=*/1, /*IsUnitStride=*/1,
339 /*IsKnownStride=*/1, 0};
340 }
342 return {/*IsSameBaseAddress=*/1, /*IsUnitStride=*/0,
343 /*IsKnownStride=*/1, 0};
344 }
346 return {/*IsSameBaseAddress=*/1, /*IsUnitStride=*/0,
347 /*IsKnownStride=*/0, 0};
348 }
349 };
350 static_assert(sizeof(PointersChainInfo) == 4, "Was size increase justified?");
351
352 /// Estimate the cost of a chain of pointers (typically pointer operands of a
353 /// chain of loads or stores within same block) operations set when lowered.
354 /// \p AccessTy is the type of the loads/stores that will ultimately use the
355 /// \p Ptrs.
358 const PointersChainInfo &Info, Type *AccessTy,
359 TargetCostKind CostKind = TTI::TCK_RecipThroughput) const;
360
361 /// \returns A value by which our inlining threshold should be multiplied.
362 /// This is primarily used to bump up the inlining threshold wholesale on
363 /// targets where calls are unusually expensive.
364 ///
365 /// TODO: This is a rather blunt instrument. Perhaps altering the costs of
366 /// individual classes of instructions would be better.
368
371
372 /// \returns The bonus of inlining the last call to a static function.
374
375 /// \returns A value to be added to the inlining threshold.
376 LLVM_ABI unsigned adjustInliningThreshold(const CallBase *CB) const;
377
378 /// \returns The cost of having an Alloca in the caller if not inlined, to be
379 /// added to the threshold
380 LLVM_ABI unsigned getCallerAllocaCost(const CallBase *CB,
381 const AllocaInst *AI) const;
382
383 /// \returns Vector bonus in percent.
384 ///
385 /// Vector bonuses: We want to more aggressively inline vector-dense kernels
386 /// and apply this bonus based on the percentage of vector instructions. A
387 /// bonus is applied if the vector instructions exceed 50% and half that
388 /// amount is applied if it exceeds 10%. Note that these bonuses are some what
389 /// arbitrary and evolved over time by accident as much as because they are
390 /// principled bonuses.
391 /// FIXME: It would be nice to base the bonus values on something more
392 /// scientific. A target may has no bonus on vector instructions.
394
395 /// \return the expected cost of a memcpy, which could e.g. depend on the
396 /// source/destination type and alignment and the number of bytes copied.
398
399 /// Returns the maximum memset / memcpy size in bytes that still makes it
400 /// profitable to inline the call.
402
403 /// \return The estimated number of case clusters when lowering \p 'SI'.
404 /// \p JTSize Set a jump table size only when \p SI is suitable for a jump
405 /// table.
406 LLVM_ABI unsigned
407 getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize,
409 BlockFrequencyInfo *BFI) const;
410
411 /// Estimate the cost of a given IR user when lowered.
412 ///
413 /// This can estimate the cost of either a ConstantExpr or Instruction when
414 /// lowered.
415 ///
416 /// \p Operands is a list of operands which can be a result of transformations
417 /// of the current operands. The number of the operands on the list must equal
418 /// to the number of the current operands the IR user has. Their order on the
419 /// list must be the same as the order of the current operands the IR user
420 /// has.
421 ///
422 /// The returned cost is defined in terms of \c TargetCostConstants, see its
423 /// comments for a detailed explanation of the cost values.
426 TargetCostKind CostKind) const;
427
428 /// This is a helper function which calls the three-argument
429 /// getInstructionCost with \p Operands which are the current operands U has.
435
436 /// If a branch or a select condition is skewed in one direction by more than
437 /// this factor, it is very likely to be predicted correctly.
439
440 /// Returns estimated penalty of a branch misprediction in latency. Indicates
441 /// how aggressive the target wants for eliminating unpredictable branches. A
442 /// zero return value means extra optimization applied to them should be
443 /// minimal.
445
446 /// Return true if branch divergence exists.
447 ///
448 /// Branch divergence has a significantly negative impact on GPU performance
449 /// when threads in the same wavefront take different paths due to conditional
450 /// branches.
451 ///
452 /// If \p F is passed, provides a context function. If \p F is known to only
453 /// execute in a single threaded environment, the target may choose to skip
454 /// uniformity analysis and assume all values are uniform.
455 LLVM_ABI bool hasBranchDivergence(const Function *F = nullptr) const;
456
457 /// Returns whether V is a source of divergence.
458 ///
459 /// This function provides the target-dependent information for
460 /// the target-independent UniformityAnalysis.
461 LLVM_ABI bool isSourceOfDivergence(const Value *V) const;
462
463 // Returns true for the target specific
464 // set of operations which produce uniform result
465 // even taking non-uniform arguments
466 LLVM_ABI bool isAlwaysUniform(const Value *V) const;
467
468 /// Query the target whether the specified address space cast from FromAS to
469 /// ToAS is valid.
470 LLVM_ABI bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const;
471
472 /// Return false if a \p AS0 address cannot possibly alias a \p AS1 address.
473 LLVM_ABI bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const;
474
475 /// Returns the address space ID for a target's 'flat' address space. Note
476 /// this is not necessarily the same as addrspace(0), which LLVM sometimes
477 /// refers to as the generic address space. The flat address space is a
478 /// generic address space that can be used access multiple segments of memory
479 /// with different address spaces. Access of a memory location through a
480 /// pointer with this address space is expected to be legal but slower
481 /// compared to the same memory location accessed through a pointer with a
482 /// different address space.
483 //
484 /// This is for targets with different pointer representations which can
485 /// be converted with the addrspacecast instruction. If a pointer is converted
486 /// to this address space, optimizations should attempt to replace the access
487 /// with the source address space.
488 ///
489 /// \returns ~0u if the target does not have such a flat address space to
490 /// optimize away.
491 LLVM_ABI unsigned getFlatAddressSpace() const;
492
493 /// Return any intrinsic address operand indexes which may be rewritten if
494 /// they use a flat address space pointer.
495 ///
496 /// \returns true if the intrinsic was handled.
498 Intrinsic::ID IID) const;
499
500 LLVM_ABI bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const;
501
502 /// Return true if globals in this address space can have initializers other
503 /// than `undef`.
504 LLVM_ABI bool
506
507 LLVM_ABI unsigned getAssumedAddrSpace(const Value *V) const;
508
509 LLVM_ABI bool isSingleThreaded() const;
510
511 LLVM_ABI std::pair<const Value *, unsigned>
512 getPredicatedAddrSpace(const Value *V) const;
513
514 /// Rewrite intrinsic call \p II such that \p OldV will be replaced with \p
515 /// NewV, which has a different address space. This should happen for every
516 /// operand index that collectFlatAddressOperands returned for the intrinsic.
517 /// \returns nullptr if the intrinsic was not handled. Otherwise, returns the
518 /// new value (which may be the original \p II with modified operands).
520 Value *OldV,
521 Value *NewV) const;
522
523 /// Test whether calls to a function lower to actual program function
524 /// calls.
525 ///
526 /// The idea is to test whether the program is likely to require a 'call'
527 /// instruction or equivalent in order to call the given function.
528 ///
529 /// FIXME: It's not clear that this is a good or useful query API. Client's
530 /// should probably move to simpler cost metrics using the above.
531 /// Alternatively, we could split the cost interface into distinct code-size
532 /// and execution-speed costs. This would allow modelling the core of this
533 /// query more accurately as a call is a single small instruction, but
534 /// incurs significant execution cost.
535 LLVM_ABI bool isLoweredToCall(const Function *F) const;
536
537 struct LSRCost {
538 /// TODO: Some of these could be merged. Also, a lexical ordering
539 /// isn't always optimal.
540 unsigned Insns;
541 unsigned NumRegs;
542 unsigned AddRecCost;
543 unsigned NumIVMuls;
544 unsigned NumBaseAdds;
545 unsigned ImmCost;
546 unsigned SetupCost;
547 unsigned ScaleCost;
548 };
549
550 /// Parameters that control the generic loop unrolling transformation.
552 /// The cost threshold for the unrolled loop. Should be relative to the
553 /// getInstructionCost values returned by this API, and the expectation is
554 /// that the unrolled loop's instructions when run through that interface
555 /// should not exceed this cost. However, this is only an estimate. Also,
556 /// specific loops may be unrolled even with a cost above this threshold if
557 /// deemed profitable. Set this to UINT_MAX to disable the loop body cost
558 /// restriction.
559 unsigned Threshold;
560 /// If complete unrolling will reduce the cost of the loop, we will boost
561 /// the Threshold by a certain percent to allow more aggressive complete
562 /// unrolling. This value provides the maximum boost percentage that we
563 /// can apply to Threshold (The value should be no less than 100).
564 /// BoostedThreshold = Threshold * min(RolledCost / UnrolledCost,
565 /// MaxPercentThresholdBoost / 100)
566 /// E.g. if complete unrolling reduces the loop execution time by 50%
567 /// then we boost the threshold by the factor of 2x. If unrolling is not
568 /// expected to reduce the running time, then we do not increase the
569 /// threshold.
571 /// The cost threshold for the unrolled loop when optimizing for size (set
572 /// to UINT_MAX to disable).
574 /// The cost threshold for the unrolled loop, like Threshold, but used
575 /// for partial/runtime unrolling (set to UINT_MAX to disable).
577 /// The cost threshold for the unrolled loop when optimizing for size, like
578 /// OptSizeThreshold, but used for partial/runtime unrolling (set to
579 /// UINT_MAX to disable).
581 /// A forced unrolling factor (the number of concatenated bodies of the
582 /// original loop in the unrolled loop body). When set to 0, the unrolling
583 /// transformation will select an unrolling factor based on the current cost
584 /// threshold and other factors.
585 unsigned Count;
586 /// Default unroll count for loops with run-time trip count.
588 // Set the maximum unrolling factor. The unrolling factor may be selected
589 // using the appropriate cost threshold, but may not exceed this number
590 // (set to UINT_MAX to disable). This does not apply in cases where the
591 // loop is being fully unrolled.
592 unsigned MaxCount;
593 /// Set the maximum upper bound of trip count. Allowing the MaxUpperBound
594 /// to be overrided by a target gives more flexiblity on certain cases.
595 /// By default, MaxUpperBound uses UnrollMaxUpperBound which value is 8.
597 /// Set the maximum unrolling factor for full unrolling. Like MaxCount, but
598 /// applies even if full unrolling is selected. This allows a target to fall
599 /// back to Partial unrolling if full unrolling is above FullUnrollMaxCount.
601 // Represents number of instructions optimized when "back edge"
602 // becomes "fall through" in unrolled loop.
603 // For now we count a conditional branch on a backedge and a comparison
604 // feeding it.
605 unsigned BEInsns;
606 /// Allow partial unrolling (unrolling of loops to expand the size of the
607 /// loop body, not only to eliminate small constant-trip-count loops).
609 /// Allow runtime unrolling (unrolling of loops to expand the size of the
610 /// loop body even when the number of loop iterations is not known at
611 /// compile time).
613 /// Allow generation of a loop remainder (extra iterations after unroll).
615 /// Allow emitting expensive instructions (such as divisions) when computing
616 /// the trip count of a loop for runtime unrolling.
618 /// Apply loop unroll on any kind of loop
619 /// (mainly to loops that fail runtime unrolling).
620 bool Force;
621 /// Allow using trip count upper bound to unroll loops.
623 /// Allow unrolling of all the iterations of the runtime loop remainder.
625 /// Allow unroll and jam. Used to enable unroll and jam for the target.
627 /// Threshold for unroll and jam, for inner loop size. The 'Threshold'
628 /// value above is used during unroll and jam for the outer loop size.
629 /// This value is used in the same manner to limit the size of the inner
630 /// loop.
632 /// Don't allow loop unrolling to simulate more than this number of
633 /// iterations when checking full unroll profitability
635 /// Don't disable runtime unroll for the loops which were vectorized.
637 /// Don't allow runtime unrolling if expanding the trip count takes more
638 /// than SCEVExpansionBudget.
640 /// Allow runtime unrolling multi-exit loops. Should only be set if the
641 /// target determined that multi-exit unrolling is profitable for the loop.
642 /// Fall back to the generic logic to determine whether multi-exit unrolling
643 /// is profitable if set to false.
645 /// Allow unrolling to add parallel reduction phis.
647 };
648
649 /// Get target-customized preferences for the generic loop unrolling
650 /// transformation. The caller will initialize UP with the current
651 /// target-independent defaults.
654 OptimizationRemarkEmitter *ORE) const;
655
656 /// Query the target whether it would be profitable to convert the given loop
657 /// into a hardware loop.
659 AssumptionCache &AC,
660 TargetLibraryInfo *LibInfo,
661 HardwareLoopInfo &HWLoopInfo) const;
662
663 // Query the target for which minimum vectorization factor epilogue
664 // vectorization should be considered.
666
667 /// Query the target whether it would be prefered to create a predicated
668 /// vector loop, which can avoid the need to emit a scalar epilogue loop.
670
671 /// Query the target what the preferred style of tail folding is.
672 /// \param IVUpdateMayOverflow Tells whether it is known if the IV update
673 /// may (or will never) overflow for the suggested VF/UF in the given loop.
674 /// Targets can use this information to select a more optimal tail folding
675 /// style. The value conservatively defaults to true, such that no assumptions
676 /// are made on overflow.
678 getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const;
679
680 // Parameters that control the loop peeling transformation
682 /// A forced peeling factor (the number of bodied of the original loop
683 /// that should be peeled off before the loop body). When set to 0, the
684 /// a peeling factor based on profile information and other factors.
685 unsigned PeelCount;
686 /// Allow peeling off loop iterations.
688 /// Allow peeling off loop iterations for loop nests.
690 /// Allow peeling basing on profile. Uses to enable peeling off all
691 /// iterations basing on provided profile.
692 /// If the value is true the peeling cost model can decide to peel only
693 /// some iterations and in this case it will set this to false.
695
696 /// Peel off the last PeelCount loop iterations.
698 };
699
700 /// Get target-customized preferences for the generic loop peeling
701 /// transformation. The caller will initialize \p PP with the current
702 /// target-independent defaults with information from \p L and \p SE.
704 PeelingPreferences &PP) const;
705
706 /// Targets can implement their own combinations for target-specific
707 /// intrinsics. This function will be called from the InstCombine pass every
708 /// time a target-specific intrinsic is encountered.
709 ///
710 /// \returns std::nullopt to not do anything target specific or a value that
711 /// will be returned from the InstCombiner. It is possible to return null and
712 /// stop further processing of the intrinsic by returning nullptr.
713 LLVM_ABI std::optional<Instruction *>
715 /// Can be used to implement target-specific instruction combining.
716 /// \see instCombineIntrinsic
717 LLVM_ABI std::optional<Value *>
719 APInt DemandedMask, KnownBits &Known,
720 bool &KnownBitsComputed) const;
721 /// Can be used to implement target-specific instruction combining.
722 /// \see instCombineIntrinsic
723 LLVM_ABI std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
724 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
725 APInt &UndefElts2, APInt &UndefElts3,
726 std::function<void(Instruction *, unsigned, APInt, APInt &)>
727 SimplifyAndSetOp) const;
728 /// @}
729
730 /// \name Scalar Target Information
731 /// @{
732
733 /// Flags indicating the kind of support for population count.
734 ///
735 /// Compared to the SW implementation, HW support is supposed to
736 /// significantly boost the performance when the population is dense, and it
737 /// may or may not degrade performance if the population is sparse. A HW
738 /// support is considered as "Fast" if it can outperform, or is on a par
739 /// with, SW implementation when the population is sparse; otherwise, it is
740 /// considered as "Slow".
742
743 /// Return true if the specified immediate is legal add immediate, that
744 /// is the target has add instructions which can add a register with the
745 /// immediate without having to materialize the immediate into a register.
746 LLVM_ABI bool isLegalAddImmediate(int64_t Imm) const;
747
748 /// Return true if adding the specified scalable immediate is legal, that is
749 /// the target has add instructions which can add a register with the
750 /// immediate (multiplied by vscale) without having to materialize the
751 /// immediate into a register.
752 LLVM_ABI bool isLegalAddScalableImmediate(int64_t Imm) const;
753
754 /// Return true if the specified immediate is legal icmp immediate,
755 /// that is the target has icmp instructions which can compare a register
756 /// against the immediate without having to materialize the immediate into a
757 /// register.
758 LLVM_ABI bool isLegalICmpImmediate(int64_t Imm) const;
759
760 /// Return true if the addressing mode represented by AM is legal for
761 /// this target, for a load/store of the specified type.
762 /// The type may be VoidTy, in which case only return true if the addressing
763 /// mode is legal for a load/store of any legal type.
764 /// If target returns true in LSRWithInstrQueries(), I may be valid.
765 /// \param ScalableOffset represents a quantity of bytes multiplied by vscale,
766 /// an invariant value known only at runtime. Most targets should not accept
767 /// a scalable offset.
768 ///
769 /// TODO: Handle pre/postinc as well.
771 int64_t BaseOffset, bool HasBaseReg,
772 int64_t Scale, unsigned AddrSpace = 0,
773 Instruction *I = nullptr,
774 int64_t ScalableOffset = 0) const;
775
776 /// Return true if LSR cost of C1 is lower than C2.
778 const TargetTransformInfo::LSRCost &C2) const;
779
780 /// Return true if LSR major cost is number of registers. Targets which
781 /// implement their own isLSRCostLess and unset number of registers as major
782 /// cost should return false, otherwise return true.
784
785 /// Return true if LSR should drop a found solution if it's calculated to be
786 /// less profitable than the baseline.
788
789 /// \returns true if LSR should not optimize a chain that includes \p I.
791
792 /// Return true if the target can fuse a compare and branch.
793 /// Loop-strength-reduction (LSR) uses that knowledge to adjust its cost
794 /// calculation for the instructions in a loop.
795 LLVM_ABI bool canMacroFuseCmp() const;
796
797 /// Return true if the target can save a compare for loop count, for example
798 /// hardware loop saves a compare.
801 TargetLibraryInfo *LibInfo) const;
802
803 /// Which addressing mode Loop Strength Reduction will try to generate.
805 AMK_None = 0x0, ///< Don't prefer any addressing mode
806 AMK_PreIndexed = 0x1, ///< Prefer pre-indexed addressing mode
807 AMK_PostIndexed = 0x2, ///< Prefer post-indexed addressing mode
808 AMK_All = 0x3, ///< Consider all addressing modes
809 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/AMK_All)
810 };
811
812 /// Return the preferred addressing mode LSR should make efforts to generate.
815
816 /// Return true if the target supports masked store.
817 LLVM_ABI bool isLegalMaskedStore(Type *DataType, Align Alignment,
818 unsigned AddressSpace) const;
819 /// Return true if the target supports masked load.
820 LLVM_ABI bool isLegalMaskedLoad(Type *DataType, Align Alignment,
821 unsigned AddressSpace) const;
822
823 /// Return true if the target supports nontemporal store.
824 LLVM_ABI bool isLegalNTStore(Type *DataType, Align Alignment) const;
825 /// Return true if the target supports nontemporal load.
826 LLVM_ABI bool isLegalNTLoad(Type *DataType, Align Alignment) const;
827
828 /// \Returns true if the target supports broadcasting a load to a vector of
829 /// type <NumElements x ElementTy>.
830 LLVM_ABI bool isLegalBroadcastLoad(Type *ElementTy,
831 ElementCount NumElements) const;
832
833 /// Return true if the target supports masked scatter.
834 LLVM_ABI bool isLegalMaskedScatter(Type *DataType, Align Alignment) const;
835 /// Return true if the target supports masked gather.
836 LLVM_ABI bool isLegalMaskedGather(Type *DataType, Align Alignment) const;
837 /// Return true if the target forces scalarizing of llvm.masked.gather
838 /// intrinsics.
840 Align Alignment) const;
841 /// Return true if the target forces scalarizing of llvm.masked.scatter
842 /// intrinsics.
844 Align Alignment) const;
845
846 /// Return true if the target supports masked compress store.
848 Align Alignment) const;
849 /// Return true if the target supports masked expand load.
850 LLVM_ABI bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const;
851
852 /// Return true if the target supports strided load.
853 LLVM_ABI bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const;
854
855 /// Return true is the target supports interleaved access for the given vector
856 /// type \p VTy, interleave factor \p Factor, alignment \p Alignment and
857 /// address space \p AddrSpace.
858 LLVM_ABI bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
859 Align Alignment,
860 unsigned AddrSpace) const;
861
862 // Return true if the target supports masked vector histograms.
864 Type *DataType) const;
865
866 /// Return true if this is an alternating opcode pattern that can be lowered
867 /// to a single instruction on the target. In X86 this is for the addsub
868 /// instruction which corrsponds to a Shuffle + Fadd + FSub pattern in IR.
869 /// This function expectes two opcodes: \p Opcode1 and \p Opcode2 being
870 /// selected by \p OpcodeMask. The mask contains one bit per lane and is a `0`
871 /// when \p Opcode0 is selected and `1` when Opcode1 is selected.
872 /// \p VecTy is the vector type of the instruction to be generated.
873 LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0,
874 unsigned Opcode1,
875 const SmallBitVector &OpcodeMask) const;
876
877 /// Return true if we should be enabling ordered reductions for the target.
879
880 /// Return true if the target has a unified operation to calculate division
881 /// and remainder. If so, the additional implicit multiplication and
882 /// subtraction required to calculate a remainder from division are free. This
883 /// can enable more aggressive transformations for division and remainder than
884 /// would typically be allowed using throughput or size cost models.
885 LLVM_ABI bool hasDivRemOp(Type *DataType, bool IsSigned) const;
886
887 /// Return true if the given instruction (assumed to be a memory access
888 /// instruction) has a volatile variant. If that's the case then we can avoid
889 /// addrspacecast to generic AS for volatile loads/stores. Default
890 /// implementation returns false, which prevents address space inference for
891 /// volatile loads/stores.
892 LLVM_ABI bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const;
893
894 /// Return true if target doesn't mind addresses in vectors.
896
897 /// Return the cost of the scaling factor used in the addressing
898 /// mode represented by AM for this target, for a load/store
899 /// of the specified type.
900 /// If the AM is supported, the return value must be >= 0.
901 /// If the AM is not supported, it returns a negative value.
902 /// TODO: Handle pre/postinc as well.
904 StackOffset BaseOffset,
905 bool HasBaseReg, int64_t Scale,
906 unsigned AddrSpace = 0) const;
907
908 /// Return true if the loop strength reduce pass should make
909 /// Instruction* based TTI queries to isLegalAddressingMode(). This is
910 /// needed on SystemZ, where e.g. a memcpy can only have a 12 bit unsigned
911 /// immediate offset and no index register.
912 LLVM_ABI bool LSRWithInstrQueries() const;
913
914 /// Return true if it's free to truncate a value of type Ty1 to type
915 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
916 /// by referencing its sub-register AX.
917 LLVM_ABI bool isTruncateFree(Type *Ty1, Type *Ty2) const;
918
919 /// Return true if it is profitable to hoist instruction in the
920 /// then/else to before if.
922
923 LLVM_ABI bool useAA() const;
924
925 /// Return true if this type is legal.
926 LLVM_ABI bool isTypeLegal(Type *Ty) const;
927
928 /// Returns the estimated number of registers required to represent \p Ty.
929 LLVM_ABI unsigned getRegUsageForType(Type *Ty) const;
930
931 /// Return true if switches should be turned into lookup tables for the
932 /// target.
934
935 /// Return true if switches should be turned into lookup tables
936 /// containing this constant value for the target.
938
939 /// Return true if lookup tables should be turned into relative lookup tables.
941
942 /// Return true if the input function which is cold at all call sites,
943 /// should use coldcc calling convention.
945
947
948 /// Identifies if the vector form of the intrinsic has a scalar operand.
950 unsigned ScalarOpdIdx) const;
951
952 /// Identifies if the vector form of the intrinsic is overloaded on the type
953 /// of the operand at index \p OpdIdx, or on the return type if \p OpdIdx is
954 /// -1.
956 int OpdIdx) const;
957
958 /// Identifies if the vector form of the intrinsic that returns a struct is
959 /// overloaded at the struct element index \p RetIdx.
960 LLVM_ABI bool
962 int RetIdx) const;
963
964 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
965 /// are set if the demanded result elements need to be inserted and/or
966 /// extracted from vectors. The involved values may be passed in VL if
967 /// Insert is true.
969 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
970 TTI::TargetCostKind CostKind, bool ForPoisonSrc = true,
971 ArrayRef<Value *> VL = {}) const;
972
973 /// Estimate the overhead of scalarizing operands with the given types. The
974 /// (potentially vector) types to use for each of argument are passes via Tys.
977
978 /// If target has efficient vector element load/store instructions, it can
979 /// return true here so that insertion/extraction costs are not added to
980 /// the scalarization cost of a load/store.
982
983 /// If the target supports tail calls.
984 LLVM_ABI bool supportsTailCalls() const;
985
986 /// If target supports tail call on \p CB
987 LLVM_ABI bool supportsTailCallFor(const CallBase *CB) const;
988
989 /// Don't restrict interleaved unrolling to small loops.
990 LLVM_ABI bool enableAggressiveInterleaving(bool LoopHasReductions) const;
991
992 /// Returns options for expansion of memcmp. IsZeroCmp is
993 // true if this is the expansion of memcmp(p1, p2, s) == 0.
995 // Return true if memcmp expansion is enabled.
996 operator bool() const { return MaxNumLoads > 0; }
997
998 // Maximum number of load operations.
999 unsigned MaxNumLoads = 0;
1000
1001 // The list of available load sizes (in bytes), sorted in decreasing order.
1003
1004 // For memcmp expansion when the memcmp result is only compared equal or
1005 // not-equal to 0, allow up to this number of load pairs per block. As an
1006 // example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1007 // a0 = load2bytes &a[0]
1008 // b0 = load2bytes &b[0]
1009 // a2 = load1byte &a[2]
1010 // b2 = load1byte &b[2]
1011 // r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1012 unsigned NumLoadsPerBlock = 1;
1013
1014 // Set to true to allow overlapping loads. For example, 7-byte compares can
1015 // be done with two 4-byte compares instead of 4+2+1-byte compares. This
1016 // requires all loads in LoadSizes to be doable in an unaligned way.
1018
1019 // Sometimes, the amount of data that needs to be compared is smaller than
1020 // the standard register size, but it cannot be loaded with just one load
1021 // instruction. For example, if the size of the memory comparison is 6
1022 // bytes, we can handle it more efficiently by loading all 6 bytes in a
1023 // single block and generating an 8-byte number, instead of generating two
1024 // separate blocks with conditional jumps for 4 and 2 byte loads. This
1025 // approach simplifies the process and produces the comparison result as
1026 // normal. This array lists the allowed sizes of memcmp tails that can be
1027 // merged into one block
1029 };
1031 bool IsZeroCmp) const;
1032
1033 /// Should the Select Optimization pass be enabled and ran.
1034 LLVM_ABI bool enableSelectOptimize() const;
1035
1036 /// Should the Select Optimization pass treat the given instruction like a
1037 /// select, potentially converting it to a conditional branch. This can
1038 /// include select-like instructions like or(zext(c), x) that can be converted
1039 /// to selects.
1041
1042 /// Enable matching of interleaved access groups.
1044
1045 /// Enable matching of interleaved access groups that contain predicated
1046 /// accesses or gaps and therefore vectorized using masked
1047 /// vector loads/stores.
1049
1050 /// Indicate that it is potentially unsafe to automatically vectorize
1051 /// floating-point operations because the semantics of vector and scalar
1052 /// floating-point semantics may differ. For example, ARM NEON v7 SIMD math
1053 /// does not support IEEE-754 denormal numbers, while depending on the
1054 /// platform, scalar floating-point math does.
1055 /// This applies to floating-point math operations and calls, not memory
1056 /// operations, shuffles, or casts.
1058
1059 /// Determine if the target supports unaligned memory accesses.
1061 unsigned BitWidth,
1062 unsigned AddressSpace = 0,
1063 Align Alignment = Align(1),
1064 unsigned *Fast = nullptr) const;
1065
1066 /// Return hardware support for population count.
1067 LLVM_ABI PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
1068
1069 /// Return true if the hardware has a fast square-root instruction.
1070 LLVM_ABI bool haveFastSqrt(Type *Ty) const;
1071
1072 /// Return true if the cost of the instruction is too high to speculatively
1073 /// execute and should be kept behind a branch.
1074 /// This normally just wraps around a getInstructionCost() call, but some
1075 /// targets might report a low TCK_SizeAndLatency value that is incompatible
1076 /// with the fixed TCC_Expensive value.
1077 /// NOTE: This assumes the instruction passes isSafeToSpeculativelyExecute().
1079
1080 /// Return true if it is faster to check if a floating-point value is NaN
1081 /// (or not-NaN) versus a comparison against a constant FP zero value.
1082 /// Targets should override this if materializing a 0.0 for comparison is
1083 /// generally as cheap as checking for ordered/unordered.
1085
1086 /// Return the expected cost of supporting the floating point operation
1087 /// of the specified type.
1089
1090 /// Return the expected cost of materializing for the given integer
1091 /// immediate of the specified type.
1093 TargetCostKind CostKind) const;
1094
1095 /// Return the expected cost of materialization for the given integer
1096 /// immediate of the specified type for a given instruction. The cost can be
1097 /// zero if the immediate can be folded into the specified instruction.
1098 LLVM_ABI InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx,
1099 const APInt &Imm, Type *Ty,
1101 Instruction *Inst = nullptr) const;
1103 const APInt &Imm, Type *Ty,
1104 TargetCostKind CostKind) const;
1105
1106 /// Return the expected cost for the given integer when optimising
1107 /// for size. This is different than the other integer immediate cost
1108 /// functions in that it is subtarget agnostic. This is useful when you e.g.
1109 /// target one ISA such as Aarch32 but smaller encodings could be possible
1110 /// with another such as Thumb. This return value is used as a penalty when
1111 /// the total costs for a constant is calculated (the bigger the cost, the
1112 /// more beneficial constant hoisting is).
1113 LLVM_ABI InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,
1114 const APInt &Imm,
1115 Type *Ty) const;
1116
1117 /// It can be advantageous to detach complex constants from their uses to make
1118 /// their generation cheaper. This hook allows targets to report when such
1119 /// transformations might negatively effect the code generation of the
1120 /// underlying operation. The motivating example is divides whereby hoisting
1121 /// constants prevents the code generator's ability to transform them into
1122 /// combinations of simpler operations.
1124 const Function &Fn) const;
1125
1126 /// @}
1127
1128 /// \name Vector Target Information
1129 /// @{
1130
1131 /// The various kinds of shuffle patterns for vector queries.
1133 SK_Broadcast, ///< Broadcast element 0 to all other elements.
1134 SK_Reverse, ///< Reverse the order of the vector.
1135 SK_Select, ///< Selects elements from the corresponding lane of
1136 ///< either source operand. This is equivalent to a
1137 ///< vector select with a constant condition operand.
1138 SK_Transpose, ///< Transpose two vectors.
1139 SK_InsertSubvector, ///< InsertSubvector. Index indicates start offset.
1140 SK_ExtractSubvector, ///< ExtractSubvector Index indicates start offset.
1141 SK_PermuteTwoSrc, ///< Merge elements from two source vectors into one
1142 ///< with any shuffle mask.
1143 SK_PermuteSingleSrc, ///< Shuffle elements of single source vector with any
1144 ///< shuffle mask.
1145 SK_Splice ///< Concatenates elements from the first input vector
1146 ///< with elements of the second input vector. Returning
1147 ///< a vector of the same type as the input vectors.
1148 ///< Index indicates start offset in first input vector.
1149 };
1150
1151 /// Additional information about an operand's possible values.
1153 OK_AnyValue, // Operand can have any value.
1154 OK_UniformValue, // Operand is uniform (splat of a value).
1155 OK_UniformConstantValue, // Operand is uniform constant.
1156 OK_NonUniformConstantValue // Operand is a non uniform constant value.
1157 };
1158
1159 /// Additional properties of an operand's values.
1165
1166 // Describe the values an operand can take. We're in the process
1167 // of migrating uses of OperandValueKind and OperandValueProperties
1168 // to use this class, and then will change the internal representation.
1172
1173 bool isConstant() const {
1175 }
1176 bool isUniform() const {
1178 }
1179 bool isPowerOf2() const {
1180 return Properties == OP_PowerOf2;
1181 }
1182 bool isNegatedPowerOf2() const {
1184 }
1185
1187 return {Kind, OP_None};
1188 }
1189 };
1190
1191 /// \return the number of registers in the target-provided register class.
1192 LLVM_ABI unsigned getNumberOfRegisters(unsigned ClassID) const;
1193
1194 /// \return true if the target supports load/store that enables fault
1195 /// suppression of memory operands when the source condition is false.
1196 LLVM_ABI bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const;
1197
1198 /// \return the target-provided register class ID for the provided type,
1199 /// accounting for type promotion and other type-legalization techniques that
1200 /// the target might apply. However, it specifically does not account for the
1201 /// scalarization or splitting of vector types. Should a vector type require
1202 /// scalarization or splitting into multiple underlying vector registers, that
1203 /// type should be mapped to a register class containing no registers.
1204 /// Specifically, this is designed to provide a simple, high-level view of the
1205 /// register allocation later performed by the backend. These register classes
1206 /// don't necessarily map onto the register classes used by the backend.
1207 /// FIXME: It's not currently possible to determine how many registers
1208 /// are used by the provided type.
1210 Type *Ty = nullptr) const;
1211
1212 /// \return the target-provided register class name
1213 LLVM_ABI const char *getRegisterClassName(unsigned ClassID) const;
1214
1216
1217 /// \return The width of the largest scalar or vector register type.
1218 LLVM_ABI TypeSize getRegisterBitWidth(RegisterKind K) const;
1219
1220 /// \return The width of the smallest vector register type.
1221 LLVM_ABI unsigned getMinVectorRegisterBitWidth() const;
1222
1223 /// \return The maximum value of vscale if the target specifies an
1224 /// architectural maximum vector length, and std::nullopt otherwise.
1225 LLVM_ABI std::optional<unsigned> getMaxVScale() const;
1226
1227 /// \return the value of vscale to tune the cost model for.
1228 LLVM_ABI std::optional<unsigned> getVScaleForTuning() const;
1229
1230 /// \return true if vscale is known to be a power of 2
1232
1233 /// \return True if the vectorization factor should be chosen to
1234 /// make the vector of the smallest element type match the size of a
1235 /// vector register. For wider element types, this could result in
1236 /// creating vectors that span multiple vector registers.
1237 /// If false, the vectorization factor will be chosen based on the
1238 /// size of the widest element type.
1239 /// \p K Register Kind for vectorization.
1240 LLVM_ABI bool
1242
1243 /// \return The minimum vectorization factor for types of given element
1244 /// bit width, or 0 if there is no minimum VF. The returned value only
1245 /// applies when shouldMaximizeVectorBandwidth returns true.
1246 /// If IsScalable is true, the returned ElementCount must be a scalable VF.
1247 LLVM_ABI ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const;
1248
1249 /// \return The maximum vectorization factor for types of given element
1250 /// bit width and opcode, or 0 if there is no maximum VF.
1251 /// Currently only used by the SLP vectorizer.
1252 LLVM_ABI unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
1253
1254 /// \return The minimum vectorization factor for the store instruction. Given
1255 /// the initial estimation of the minimum vector factor and store value type,
1256 /// it tries to find possible lowest VF, which still might be profitable for
1257 /// the vectorization.
1258 /// \param VF Initial estimation of the minimum vector factor.
1259 /// \param ScalarMemTy Scalar memory type of the store operation.
1260 /// \param ScalarValTy Scalar type of the stored value.
1261 /// Currently only used by the SLP vectorizer.
1262 LLVM_ABI unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
1263 Type *ScalarValTy) const;
1264
1265 /// \return True if it should be considered for address type promotion.
1266 /// \p AllowPromotionWithoutCommonHeader Set true if promoting \p I is
1267 /// profitable without finding other extensions fed by the same input.
1269 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const;
1270
1271 /// \return The size of a cache line in bytes.
1272 LLVM_ABI unsigned getCacheLineSize() const;
1273
1274 /// The possible cache levels
1275 enum class CacheLevel {
1276 L1D, // The L1 data cache
1277 L2D, // The L2 data cache
1278
1279 // We currently do not model L3 caches, as their sizes differ widely between
1280 // microarchitectures. Also, we currently do not have a use for L3 cache
1281 // size modeling yet.
1282 };
1283
1284 /// \return The size of the cache level in bytes, if available.
1285 LLVM_ABI std::optional<unsigned> getCacheSize(CacheLevel Level) const;
1286
1287 /// \return The associativity of the cache level, if available.
1288 LLVM_ABI std::optional<unsigned>
1289 getCacheAssociativity(CacheLevel Level) const;
1290
1291 /// \return The minimum architectural page size for the target.
1292 LLVM_ABI std::optional<unsigned> getMinPageSize() const;
1293
1294 /// \return How much before a load we should place the prefetch
1295 /// instruction. This is currently measured in number of
1296 /// instructions.
1297 LLVM_ABI unsigned getPrefetchDistance() const;
1298
1299 /// Some HW prefetchers can handle accesses up to a certain constant stride.
1300 /// Sometimes prefetching is beneficial even below the HW prefetcher limit,
1301 /// and the arguments provided are meant to serve as a basis for deciding this
1302 /// for a particular loop.
1303 ///
1304 /// \param NumMemAccesses Number of memory accesses in the loop.
1305 /// \param NumStridedMemAccesses Number of the memory accesses that
1306 /// ScalarEvolution could find a known stride
1307 /// for.
1308 /// \param NumPrefetches Number of software prefetches that will be
1309 /// emitted as determined by the addresses
1310 /// involved and the cache line size.
1311 /// \param HasCall True if the loop contains a call.
1312 ///
1313 /// \return This is the minimum stride in bytes where it makes sense to start
1314 /// adding SW prefetches. The default is 1, i.e. prefetch with any
1315 /// stride.
1316 LLVM_ABI unsigned getMinPrefetchStride(unsigned NumMemAccesses,
1317 unsigned NumStridedMemAccesses,
1318 unsigned NumPrefetches,
1319 bool HasCall) const;
1320
1321 /// \return The maximum number of iterations to prefetch ahead. If
1322 /// the required number of iterations is more than this number, no
1323 /// prefetching is performed.
1324 LLVM_ABI unsigned getMaxPrefetchIterationsAhead() const;
1325
1326 /// \return True if prefetching should also be done for writes.
1327 LLVM_ABI bool enableWritePrefetching() const;
1328
1329 /// \return if target want to issue a prefetch in address space \p AS.
1330 LLVM_ABI bool shouldPrefetchAddressSpace(unsigned AS) const;
1331
1332 /// \return The cost of a partial reduction, which is a reduction from a
1333 /// vector to another vector with fewer elements of larger size. They are
1334 /// represented by the llvm.vector.partial.reduce.add intrinsic, which
1335 /// takes an accumulator of type \p AccumType and a second vector operand to
1336 /// be accumulated, whose element count is specified by \p VF. The type of
1337 /// reduction is specified by \p Opcode. The second operand passed to the
1338 /// intrinsic could be the result of an extend, such as sext or zext. In
1339 /// this case \p BinOp is nullopt, \p InputTypeA represents the type being
1340 /// extended and \p OpAExtend the operation, i.e. sign- or zero-extend.
1341 /// Also, \p InputTypeB should be nullptr and OpBExtend should be None.
1342 /// Alternatively, the second operand could be the result of a binary
1343 /// operation performed on two extends, i.e.
1344 /// mul(zext i8 %a -> i32, zext i8 %b -> i32).
1345 /// In this case \p BinOp may specify the opcode of the binary operation,
1346 /// \p InputTypeA and \p InputTypeB the types being extended, and
1347 /// \p OpAExtend, \p OpBExtend the form of extensions. An example of an
1348 /// operation that uses a partial reduction is a dot product, which reduces
1349 /// two vectors in binary mul operation to another of 4 times fewer and 4
1350 /// times larger elements.
1352 unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
1354 PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
1356
1357 /// \return The maximum interleave factor that any transform should try to
1358 /// perform for this target. This number depends on the level of parallelism
1359 /// and the number of execution units in the CPU.
1360 LLVM_ABI unsigned getMaxInterleaveFactor(ElementCount VF) const;
1361
1362 /// Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
1363 LLVM_ABI static OperandValueInfo getOperandInfo(const Value *V);
1364
1365 /// This is an approximation of reciprocal throughput of a math/logic op.
1366 /// A higher cost indicates less expected throughput.
1367 /// From Agner Fog's guides, reciprocal throughput is "the average number of
1368 /// clock cycles per instruction when the instructions are not part of a
1369 /// limiting dependency chain."
1370 /// Therefore, costs should be scaled to account for multiple execution units
1371 /// on the target that can process this type of instruction. For example, if
1372 /// there are 5 scalar integer units and 2 vector integer units that can
1373 /// calculate an 'add' in a single cycle, this model should indicate that the
1374 /// cost of the vector add instruction is 2.5 times the cost of the scalar
1375 /// add instruction.
1376 /// \p Args is an optional argument which holds the instruction operands
1377 /// values so the TTI can analyze those values searching for special
1378 /// cases or optimizations based on those values.
1379 /// \p CxtI is the optional original context instruction, if one exists, to
1380 /// provide even more information.
1381 /// \p TLibInfo is used to search for platform specific vector library
1382 /// functions for instructions that might be converted to calls (e.g. frem).
1384 unsigned Opcode, Type *Ty,
1388 ArrayRef<const Value *> Args = {}, const Instruction *CxtI = nullptr,
1389 const TargetLibraryInfo *TLibInfo = nullptr) const;
1390
1391 /// Returns the cost estimation for alternating opcode pattern that can be
1392 /// lowered to a single instruction on the target. In X86 this is for the
1393 /// addsub instruction which corrsponds to a Shuffle + Fadd + FSub pattern in
1394 /// IR. This function expects two opcodes: \p Opcode1 and \p Opcode2 being
1395 /// selected by \p OpcodeMask. The mask contains one bit per lane and is a `0`
1396 /// when \p Opcode0 is selected and `1` when Opcode1 is selected.
1397 /// \p VecTy is the vector type of the instruction to be generated.
1399 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1400 const SmallBitVector &OpcodeMask,
1402
1403 /// \return The cost of a shuffle instruction of kind Kind with inputs of type
1404 /// SrcTy, producing a vector of type DstTy. The exact mask may be passed as
1405 /// Mask, or else the array will be empty. The Index and SubTp parameters
1406 /// are used by the subvector insertions shuffle kinds to show the insert
1407 /// point and the type of the subvector being inserted. The operands of the
1408 /// shuffle can be passed through \p Args, which helps improve the cost
1409 /// estimation in some cases, like in broadcast loads.
1411 ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
1412 ArrayRef<int> Mask = {},
1414 VectorType *SubTp = nullptr, ArrayRef<const Value *> Args = {},
1415 const Instruction *CxtI = nullptr) const;
1416
1417 /// Represents a hint about the context in which a cast is used.
1418 ///
1419 /// For zext/sext, the context of the cast is the operand, which must be a
1420 /// load of some kind. For trunc, the context is of the cast is the single
1421 /// user of the instruction, which must be a store of some kind.
1422 ///
1423 /// This enum allows the vectorizer to give getCastInstrCost an idea of the
1424 /// type of cast it's dealing with, as not every cast is equal. For instance,
1425 /// the zext of a load may be free, but the zext of an interleaving load can
1426 //// be (very) expensive!
1427 ///
1428 /// See \c getCastContextHint to compute a CastContextHint from a cast
1429 /// Instruction*. Callers can use it if they don't need to override the
1430 /// context and just want it to be calculated from the instruction.
1431 ///
1432 /// FIXME: This handles the types of load/store that the vectorizer can
1433 /// produce, which are the cases where the context instruction is most
1434 /// likely to be incorrect. There are other situations where that can happen
1435 /// too, which might be handled here but in the long run a more general
1436 /// solution of costing multiple instructions at the same times may be better.
1438 None, ///< The cast is not used with a load/store of any kind.
1439 Normal, ///< The cast is used with a normal load/store.
1440 Masked, ///< The cast is used with a masked load/store.
1441 GatherScatter, ///< The cast is used with a gather/scatter.
1442 Interleave, ///< The cast is used with an interleaved load/store.
1443 Reversed, ///< The cast is used with a reversed load/store.
1444 };
1445
1446 /// Calculates a CastContextHint from \p I.
1447 /// This should be used by callers of getCastInstrCost if they wish to
1448 /// determine the context from some instruction.
1449 /// \returns the CastContextHint for ZExt/SExt/Trunc, None if \p I is nullptr,
1450 /// or if it's another type of cast.
1452
1453 /// \return The expected cost of cast instructions, such as bitcast, trunc,
1454 /// zext, etc. If there is an existing instruction that holds Opcode, it
1455 /// may be passed in the 'I' parameter.
1457 unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH,
1459 const Instruction *I = nullptr) const;
1460
1461 /// \return The expected cost of a sign- or zero-extended vector extract. Use
1462 /// Index = -1 to indicate that there is no information about the index value.
1464 getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
1465 unsigned Index, TTI::TargetCostKind CostKind) const;
1466
1467 /// \return The expected cost of control-flow related instructions such as
1468 /// Phi, Ret, Br, Switch.
1471 const Instruction *I = nullptr) const;
1472
1473 /// \returns The expected cost of compare and select instructions. If there
1474 /// is an existing instruction that holds Opcode, it may be passed in the
1475 /// 'I' parameter. The \p VecPred parameter can be used to indicate the select
1476 /// is using a compare with the specified predicate as condition. When vector
1477 /// types are passed, \p VecPred must be used for all lanes. For a
1478 /// comparison, the two operands are the natural values. For a select, the
1479 /// two operands are the *value* operands, not the condition operand.
1481 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1483 OperandValueInfo Op1Info = {OK_AnyValue, OP_None},
1484 OperandValueInfo Op2Info = {OK_AnyValue, OP_None},
1485 const Instruction *I = nullptr) const;
1486
1487 /// \return The expected cost of vector Insert and Extract.
1488 /// Use -1 to indicate that there is no information on the index value.
1489 /// This is used when the instruction is not available; a typical use
1490 /// case is to provision the cost of vectorization/scalarization in
1491 /// vectorizer passes.
1492 LLVM_ABI InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
1494 unsigned Index = -1,
1495 const Value *Op0 = nullptr,
1496 const Value *Op1 = nullptr) const;
1497
1498 /// \return The expected cost of vector Insert and Extract.
1499 /// Use -1 to indicate that there is no information on the index value.
1500 /// This is used when the instruction is not available; a typical use
1501 /// case is to provision the cost of vectorization/scalarization in
1502 /// vectorizer passes.
1503 /// \param ScalarUserAndIdx encodes the information about extracts from a
1504 /// vector with 'Scalar' being the value being extracted,'User' being the user
1505 /// of the extract(nullptr if user is not known before vectorization) and
1506 /// 'Idx' being the extract lane.
1508 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1509 Value *Scalar,
1510 ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx) const;
1511
1512 /// \return The expected cost of vector Insert and Extract.
1513 /// This is used when instruction is available, and implementation
1514 /// asserts 'I' is not nullptr.
1515 ///
1516 /// A typical suitable use case is cost estimation when vector instruction
1517 /// exists (e.g., from basic blocks during transformation).
1518 LLVM_ABI InstructionCost getVectorInstrCost(const Instruction &I, Type *Val,
1520 unsigned Index = -1) const;
1521
1522 /// \return The expected cost of inserting or extracting a lane that is \p
1523 /// Index elements from the end of a vector, i.e. the mathematical expression
1524 /// for the lane is (VF - 1 - Index). This is required for scalable vectors
1525 /// where the exact lane index is unknown at compile time.
1527 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind,
1528 unsigned Index) const;
1529
1530 /// \return The expected cost of aggregate inserts and extracts. This is
1531 /// used when the instruction is not available; a typical use case is to
1532 /// provision the cost of vectorization/scalarization in vectorizer passes.
1534 unsigned Opcode, TTI::TargetCostKind CostKind) const;
1535
1536 /// \return The cost of replication shuffle of \p VF elements typed \p EltTy
1537 /// \p ReplicationFactor times.
1538 ///
1539 /// For example, the mask for \p ReplicationFactor=3 and \p VF=4 is:
1540 /// <0,0,0,1,1,1,2,2,2,3,3,3>
1542 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1544
1545 /// \return The cost of Load and Store instructions. The operand info
1546 /// \p OpdInfo should refer to the stored value for stores and the address
1547 /// for loads.
1549 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1552 const Instruction *I = nullptr) const;
1553
1554 /// \return The cost of VP Load and Store instructions.
1556 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1558 const Instruction *I = nullptr) const;
1559
1560 /// \return The cost of masked Load and Store instructions.
1562 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1564
1565 /// \return The cost of Gather or Scatter operation
1566 /// \p Opcode - is a type of memory access Load or Store
1567 /// \p DataTy - a vector type of the data to be loaded or stored
1568 /// \p Ptr - pointer [or vector of pointers] - address[es] in memory
1569 /// \p VariableMask - true when the memory access is predicated with a mask
1570 /// that is not a compile-time constant
1571 /// \p Alignment - alignment of single element
1572 /// \p I - the optional original context instruction, if one exists, e.g. the
1573 /// load/store to transform or the call to the gather/scatter intrinsic
1575 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1577 const Instruction *I = nullptr) const;
1578
1579 /// \return The cost of Expand Load or Compress Store operation
1580 /// \p Opcode - is a type of memory access Load or Store
1581 /// \p Src - a vector type of the data to be loaded or stored
1582 /// \p VariableMask - true when the memory access is predicated with a mask
1583 /// that is not a compile-time constant
1584 /// \p Alignment - alignment of single element
1585 /// \p I - the optional original context instruction, if one exists, e.g. the
1586 /// load/store to transform or the call to the gather/scatter intrinsic
1588 unsigned Opcode, Type *DataTy, bool VariableMask, Align Alignment,
1590 const Instruction *I = nullptr) const;
1591
1592 /// \return The cost of strided memory operations.
1593 /// \p Opcode - is a type of memory access Load or Store
1594 /// \p DataTy - a vector type of the data to be loaded or stored
1595 /// \p Ptr - pointer [or vector of pointers] - address[es] in memory
1596 /// \p VariableMask - true when the memory access is predicated with a mask
1597 /// that is not a compile-time constant
1598 /// \p Alignment - alignment of single element
1599 /// \p I - the optional original context instruction, if one exists, e.g. the
1600 /// load/store to transform or the call to the gather/scatter intrinsic
1602 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1604 const Instruction *I = nullptr) const;
1605
1606 /// \return The cost of the interleaved memory operation.
1607 /// \p Opcode is the memory operation code
1608 /// \p VecTy is the vector type of the interleaved access.
1609 /// \p Factor is the interleave factor
1610 /// \p Indices is the indices for interleaved load members (as interleaved
1611 /// load allows gaps)
1612 /// \p Alignment is the alignment of the memory operation
1613 /// \p AddressSpace is address space of the pointer.
1614 /// \p UseMaskForCond indicates if the memory access is predicated.
1615 /// \p UseMaskForGaps indicates if gaps should be masked.
1617 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1618 Align Alignment, unsigned AddressSpace,
1620 bool UseMaskForCond = false, bool UseMaskForGaps = false) const;
1621
1622 /// A helper function to determine the type of reduction algorithm used
1623 /// for a given \p Opcode and set of FastMathFlags \p FMF.
1624 static bool requiresOrderedReduction(std::optional<FastMathFlags> FMF) {
1625 return FMF && !(*FMF).allowReassoc();
1626 }
1627
1628 /// Calculate the cost of vector reduction intrinsics.
1629 ///
1630 /// This is the cost of reducing the vector value of type \p Ty to a scalar
1631 /// value using the operation denoted by \p Opcode. The FastMathFlags
1632 /// parameter \p FMF indicates what type of reduction we are performing:
1633 /// 1. Tree-wise. This is the typical 'fast' reduction performed that
1634 /// involves successively splitting a vector into half and doing the
1635 /// operation on the pair of halves until you have a scalar value. For
1636 /// example:
1637 /// (v0, v1, v2, v3)
1638 /// ((v0+v2), (v1+v3), undef, undef)
1639 /// ((v0+v2+v1+v3), undef, undef, undef)
1640 /// This is the default behaviour for integer operations, whereas for
1641 /// floating point we only do this if \p FMF indicates that
1642 /// reassociation is allowed.
1643 /// 2. Ordered. For a vector with N elements this involves performing N
1644 /// operations in lane order, starting with an initial scalar value, i.e.
1645 /// result = InitVal + v0
1646 /// result = result + v1
1647 /// result = result + v2
1648 /// result = result + v3
1649 /// This is only the case for FP operations and when reassociation is not
1650 /// allowed.
1651 ///
1653 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1655
1659
1660 /// Calculate the cost of an extended reduction pattern, similar to
1661 /// getArithmeticReductionCost of an Add/Sub reduction with multiply and
1662 /// optional extensions. This is the cost of as:
1663 /// * ResTy vecreduce.add/sub(mul (A, B)) or,
1664 /// * ResTy vecreduce.add/sub(mul(ext(Ty A), ext(Ty B)).
1666 bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty,
1668
1669 /// Calculate the cost of an extended reduction pattern, similar to
1670 /// getArithmeticReductionCost of a reduction with an extension.
1671 /// This is the cost of as:
1672 /// ResTy vecreduce.opcode(ext(Ty A)).
1674 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1675 std::optional<FastMathFlags> FMF,
1677
1678 /// \returns The cost of Intrinsic instructions. Analyses the real arguments.
1679 /// Three cases are handled: 1. scalar instruction 2. vector instruction
1680 /// 3. scalar instruction which is to be vectorized.
1683
1684 /// \returns The cost of Call instructions.
1686 Function *F, Type *RetTy, ArrayRef<Type *> Tys,
1688
1689 /// \returns The number of pieces into which the provided type must be
1690 /// split during legalization. Zero is returned when the answer is unknown.
1691 LLVM_ABI unsigned getNumberOfParts(Type *Tp) const;
1692
1693 /// \returns The cost of the address computation. For most targets this can be
1694 /// merged into the instruction indexing mode. Some targets might want to
1695 /// distinguish between address computation for memory operations with vector
1696 /// pointer types and scalar pointer types. Such targets should override this
1697 /// function. \p SE holds the pointer for the scalar evolution object which
1698 /// was used in order to get the Ptr step value. \p Ptr holds the SCEV of the
1699 /// access pointer.
1703
1704 /// \returns The cost, if any, of keeping values of the given types alive
1705 /// over a callsite.
1706 ///
1707 /// Some types may require the use of register classes that do not have
1708 /// any callee-saved registers, so would require a spill and fill.
1711
1712 /// \returns True if the intrinsic is a supported memory intrinsic. Info
1713 /// will contain additional information - whether the intrinsic may write
1714 /// or read to memory, volatility and the pointer. Info is undefined
1715 /// if false is returned.
1717 MemIntrinsicInfo &Info) const;
1718
1719 /// \returns The maximum element size, in bytes, for an element
1720 /// unordered-atomic memory intrinsic.
1722
1723 /// \returns A value which is the result of the given memory intrinsic. If \p
1724 /// CanCreate is true, new instructions may be created to extract the result
1725 /// from the given intrinsic memory operation. Returns nullptr if the target
1726 /// cannot create a result from the given intrinsic.
1727 LLVM_ABI Value *
1729 bool CanCreate = true) const;
1730
1731 /// \returns The type to use in a loop expansion of a memcpy call.
1733 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1734 unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
1735 std::optional<uint32_t> AtomicElementSize = std::nullopt) const;
1736
1737 /// \param[out] OpsOut The operand types to copy RemainingBytes of memory.
1738 /// \param RemainingBytes The number of bytes to copy.
1739 ///
1740 /// Calculates the operand types to use when copying \p RemainingBytes of
1741 /// memory, where source and destination alignments are \p SrcAlign and
1742 /// \p DestAlign respectively.
1744 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1745 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1746 Align SrcAlign, Align DestAlign,
1747 std::optional<uint32_t> AtomicCpySize = std::nullopt) const;
1748
1749 /// \returns True if the two functions have compatible attributes for inlining
1750 /// purposes.
1751 LLVM_ABI bool areInlineCompatible(const Function *Caller,
1752 const Function *Callee) const;
1753
1754 /// Returns a penalty for invoking call \p Call in \p F.
1755 /// For example, if a function F calls a function G, which in turn calls
1756 /// function H, then getInlineCallPenalty(F, H()) would return the
1757 /// penalty of calling H from F, e.g. after inlining G into F.
1758 /// \p DefaultCallPenalty is passed to give a default penalty that
1759 /// the target can amend or override.
1760 LLVM_ABI unsigned getInlineCallPenalty(const Function *F,
1761 const CallBase &Call,
1762 unsigned DefaultCallPenalty) const;
1763
1764 /// \returns True if the caller and callee agree on how \p Types will be
1765 /// passed to or returned from the callee.
1766 /// to the callee.
1767 /// \param Types List of types to check.
1768 LLVM_ABI bool areTypesABICompatible(const Function *Caller,
1769 const Function *Callee,
1770 const ArrayRef<Type *> &Types) const;
1771
1772 /// The type of load/store indexing.
1774 MIM_Unindexed, ///< No indexing.
1775 MIM_PreInc, ///< Pre-incrementing.
1776 MIM_PreDec, ///< Pre-decrementing.
1777 MIM_PostInc, ///< Post-incrementing.
1778 MIM_PostDec ///< Post-decrementing.
1779 };
1780
1781 /// \returns True if the specified indexed load for the given type is legal.
1782 LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const;
1783
1784 /// \returns True if the specified indexed store for the given type is legal.
1785 LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const;
1786
1787 /// \returns The bitwidth of the largest vector type that should be used to
1788 /// load/store in the given address space.
1789 LLVM_ABI unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
1790
1791 /// \returns True if the load instruction is legal to vectorize.
1793
1794 /// \returns True if the store instruction is legal to vectorize.
1796
1797 /// \returns True if it is legal to vectorize the given load chain.
1798 LLVM_ABI bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
1799 Align Alignment,
1800 unsigned AddrSpace) const;
1801
1802 /// \returns True if it is legal to vectorize the given store chain.
1803 LLVM_ABI bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
1804 Align Alignment,
1805 unsigned AddrSpace) const;
1806
1807 /// \returns True if it is legal to vectorize the given reduction kind.
1809 ElementCount VF) const;
1810
1811 /// \returns True if the given type is supported for scalable vectors
1813
1814 /// \returns The new vector factor value if the target doesn't support \p
1815 /// SizeInBytes loads or has a better vector factor.
1816 LLVM_ABI unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
1817 unsigned ChainSizeInBytes,
1818 VectorType *VecTy) const;
1819
1820 /// \returns The new vector factor value if the target doesn't support \p
1821 /// SizeInBytes stores or has a better vector factor.
1822 LLVM_ABI unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
1823 unsigned ChainSizeInBytes,
1824 VectorType *VecTy) const;
1825
1826 /// \returns True if the target prefers fixed width vectorization if the
1827 /// loop vectorizer's cost-model assigns an equal cost to the fixed and
1828 /// scalable version of the vectorized loop.
1829 /// \p IsEpilogue is true if the decision is for the epilogue loop.
1830 LLVM_ABI bool preferFixedOverScalableIfEqualCost(bool IsEpilogue) const;
1831
1832 /// \returns True if target prefers SLP vectorizer with altermate opcode
1833 /// vectorization, false - otherwise.
1835
1836 /// \returns True if the target prefers reductions of \p Kind to be performed
1837 /// in the loop.
1838 LLVM_ABI bool preferInLoopReduction(RecurKind Kind, Type *Ty) const;
1839
1840 /// \returns True if the target prefers reductions select kept in the loop
1841 /// when tail folding. i.e.
1842 /// loop:
1843 /// p = phi (0, s)
1844 /// a = add (p, x)
1845 /// s = select (mask, a, p)
1846 /// vecreduce.add(s)
1847 ///
1848 /// As opposed to the normal scheme of p = phi (0, a) which allows the select
1849 /// to be pulled out of the loop. If the select(.., add, ..) can be predicated
1850 /// by the target, this can lead to cleaner code generation.
1852
1853 /// Return true if the loop vectorizer should consider vectorizing an
1854 /// otherwise scalar epilogue loop.
1856
1857 /// \returns True if the loop vectorizer should discard any VFs where the
1858 /// maximum register pressure exceeds getNumberOfRegisters.
1860
1861 /// \returns True if the target wants to expand the given reduction intrinsic
1862 /// into a shuffle sequence.
1864
1866
1867 /// \returns The shuffle sequence pattern used to expand the given reduction
1868 /// intrinsic.
1871
1872 /// \returns the size cost of rematerializing a GlobalValue address relative
1873 /// to a stack reload.
1874 LLVM_ABI unsigned getGISelRematGlobalCost() const;
1875
1876 /// \returns the lower bound of a trip count to decide on vectorization
1877 /// while tail-folding.
1879
1880 /// \returns True if the target supports scalable vectors.
1881 LLVM_ABI bool supportsScalableVectors() const;
1882
1883 /// \return true when scalable vectorization is preferred.
1885
1886 /// \name Vector Predication Information
1887 /// @{
1888 /// Whether the target supports the %evl parameter of VP intrinsic efficiently
1889 /// in hardware. (see LLVM Language Reference - "Vector Predication
1890 /// Intrinsics"). Use of %evl is discouraged when that is not the case.
1891 LLVM_ABI bool hasActiveVectorLength() const;
1892
1893 /// Return true if sinking I's operands to the same basic block as I is
1894 /// profitable, e.g. because the operands can be folded into a target
1895 /// instruction during instruction selection. After calling the function
1896 /// \p Ops contains the Uses to sink ordered by dominance (dominating users
1897 /// come first).
1900
1901 /// Return true if it's significantly cheaper to shift a vector by a uniform
1902 /// scalar than by an amount which will vary across each lane. On x86 before
1903 /// AVX2 for example, there is a "psllw" instruction for the former case, but
1904 /// no simple instruction for a general "a << b" operation on vectors.
1905 /// This should also apply to lowering for vector funnel shifts (rotates).
1907
1910 // keep the predicating parameter
1912 // where legal, discard the predicate parameter
1914 // transform into something else that is also predicating
1916 };
1917
1918 // How to transform the EVL parameter.
1919 // Legal: keep the EVL parameter as it is.
1920 // Discard: Ignore the EVL parameter where it is safe to do so.
1921 // Convert: Fold the EVL into the mask parameter.
1923
1924 // How to transform the operator.
1925 // Legal: The target supports this operator.
1926 // Convert: Convert this to a non-VP operation.
1927 // The 'Discard' strategy is invalid.
1929
1930 bool shouldDoNothing() const {
1931 return (EVLParamStrategy == Legal) && (OpStrategy == Legal);
1932 }
1935 };
1936
1937 /// \returns How the target needs this vector-predicated operation to be
1938 /// transformed.
1940 getVPLegalizationStrategy(const VPIntrinsic &PI) const;
1941 /// @}
1942
1943 /// \returns Whether a 32-bit branch instruction is available in Arm or Thumb
1944 /// state.
1945 ///
1946 /// Used by the LowerTypeTests pass, which constructs an IR inline assembler
1947 /// node containing a jump table in a format suitable for the target, so it
1948 /// needs to know what format of jump table it can legally use.
1949 ///
1950 /// For non-Arm targets, this function isn't used. It defaults to returning
1951 /// false, but it shouldn't matter what it returns anyway.
1952 LLVM_ABI bool hasArmWideBranch(bool Thumb) const;
1953
1954 /// Returns a bitmask constructed from the target-features or fmv-features
1955 /// metadata of a function.
1956 LLVM_ABI APInt getFeatureMask(const Function &F) const;
1957
1958 /// Returns true if this is an instance of a function with multiple versions.
1959 LLVM_ABI bool isMultiversionedFunction(const Function &F) const;
1960
1961 /// \return The maximum number of function arguments the target supports.
1962 LLVM_ABI unsigned getMaxNumArgs() const;
1963
1964 /// \return For an array of given Size, return alignment boundary to
1965 /// pad to. Default is no padding.
1966 LLVM_ABI unsigned getNumBytesToPadGlobalArray(unsigned Size,
1967 Type *ArrayType) const;
1968
1969 /// @}
1970
1971 /// Collect kernel launch bounds for \p F into \p LB.
1973 const Function &F,
1974 SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const;
1975
1976 /// Returns true if GEP should not be used to index into vectors for this
1977 /// target.
1979
1980private:
1981 std::unique_ptr<const TargetTransformInfoImplBase> TTIImpl;
1982};
1983
1984/// Analysis pass providing the \c TargetTransformInfo.
1985///
1986/// The core idea of the TargetIRAnalysis is to expose an interface through
1987/// which LLVM targets can analyze and provide information about the middle
1988/// end's target-independent IR. This supports use cases such as target-aware
1989/// cost modeling of IR constructs.
1990///
1991/// This is a function analysis because much of the cost modeling for targets
1992/// is done in a subtarget specific way and LLVM supports compiling different
1993/// functions targeting different subtargets in order to support runtime
1994/// dispatch according to the observed subtarget.
1995class TargetIRAnalysis : public AnalysisInfoMixin<TargetIRAnalysis> {
1996public:
1998
1999 /// Default construct a target IR analysis.
2000 ///
2001 /// This will use the module's datalayout to construct a baseline
2002 /// conservative TTI result.
2004
2005 /// Construct an IR analysis pass around a target-provide callback.
2006 ///
2007 /// The callback will be called with a particular function for which the TTI
2008 /// is needed and must return a TTI object for that function.
2009 LLVM_ABI
2010 TargetIRAnalysis(std::function<Result(const Function &)> TTICallback);
2011
2012 // Value semantics. We spell out the constructors for MSVC.
2014 : TTICallback(Arg.TTICallback) {}
2016 : TTICallback(std::move(Arg.TTICallback)) {}
2018 TTICallback = RHS.TTICallback;
2019 return *this;
2020 }
2022 TTICallback = std::move(RHS.TTICallback);
2023 return *this;
2024 }
2025
2027
2028private:
2030 LLVM_ABI static AnalysisKey Key;
2031
2032 /// The callback used to produce a result.
2033 ///
2034 /// We use a completely opaque callback so that targets can provide whatever
2035 /// mechanism they desire for constructing the TTI for a given function.
2036 ///
2037 /// FIXME: Should we really use std::function? It's relatively inefficient.
2038 /// It might be possible to arrange for even stateful callbacks to outlive
2039 /// the analysis and thus use a function_ref which would be lighter weight.
2040 /// This may also be less error prone as the callback is likely to reference
2041 /// the external TargetMachine, and that reference needs to never dangle.
2042 std::function<Result(const Function &)> TTICallback;
2043
2044 /// Helper function used as the callback in the default constructor.
2045 static Result getDefaultTTI(const Function &F);
2046};
2047
2048/// Wrapper pass for TargetTransformInfo.
2049///
2050/// This pass can be constructed from a TTI object which it stores internally
2051/// and is queried by passes.
2053 TargetIRAnalysis TIRA;
2054 std::optional<TargetTransformInfo> TTI;
2055
2056 virtual void anchor();
2057
2058public:
2059 static char ID;
2060
2061 /// We must provide a default constructor for the pass but it should
2062 /// never be used.
2063 ///
2064 /// Use the constructor below or call one of the creation routines.
2066
2068
2070};
2071
2072/// Create an analysis pass wrapper around a TTI object.
2073///
2074/// This analysis pass just holds the TTI instance and makes it available to
2075/// clients.
2078
2079} // namespace llvm
2080
2081#endif
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
Analysis containing CSE Info
Definition CSEInfo.cpp:27
#define LLVM_ABI
Definition Compiler.h:213
static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))
TargetTransformInfo::VPLegalization VPLegalization
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This header defines various interfaces for pass management in LLVM.
This file defines an InstructionCost class that is used when calculating the cost of an instruction,...
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
#define F(x, y, z)
Definition MD5.cpp:55
#define I(x, y, z)
Definition MD5.cpp:58
mir Rename Register Operands
uint64_t IntrinsicInst * II
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
Value * RHS
Class for arbitrary precision integers.
Definition APInt.h:78
an instruction to allocate memory on the stack
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
Class to represent array types.
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
Definition BasicBlock.h:62
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:678
This is an important base class in LLVM.
Definition Constant.h:43
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:63
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition Dominators.h:165
Convenience struct for specifying and reasoning about fast-math flags.
Definition FMF.h:22
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition Pass.h:285
ImmutablePass(char &pid)
Definition Pass.h:287
The core instruction combiner logic.
static InstructionCost getInvalid(CostType Val=0)
Class to represent integer types.
Drive the analysis of interleaved memory accesses in the loop.
const TargetLibraryInfo * getLibInfo() const
const SmallVectorImpl< Type * > & getArgTypes() const
const SmallVectorImpl< const Value * > & getArgs() const
LLVM_ABI IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false, TargetLibraryInfo const *LibInfo=nullptr)
InstructionCost getScalarizationCost() const
const IntrinsicInst * getInst() const
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
An instruction for reading from memory.
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
The optimization diagnostic interface.
A set of analyses that are preserved following a run of a transformation pass.
Definition Analysis.h:112
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:31
An instruction for storing to memory.
Multiway switch.
Analysis pass providing the TargetTransformInfo.
TargetIRAnalysis(const TargetIRAnalysis &Arg)
TargetIRAnalysis & operator=(const TargetIRAnalysis &RHS)
LLVM_ABI Result run(const Function &F, FunctionAnalysisManager &)
LLVM_ABI TargetIRAnalysis()
Default construct a target IR analysis.
TargetIRAnalysis & operator=(TargetIRAnalysis &&RHS)
TargetIRAnalysis(TargetIRAnalysis &&Arg)
Provides information about what library functions are available for the current target.
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
LLVM_ABI bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
LLVM_ABI Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate=true) const
LLVM_ABI bool isLegalToVectorizeLoad(LoadInst *LI) const
LLVM_ABI std::optional< unsigned > getVScaleForTuning() const
static LLVM_ABI CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
LLVM_ABI unsigned getMaxNumArgs() const
LLVM_ABI bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
LLVM_ABI bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
LLVM_ABI InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
LLVM_ABI bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
LLVM_ABI bool isLegalToVectorizeStore(StoreInst *SI) const
LLVM_ABI InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, const Value *Op0=nullptr, const Value *Op1=nullptr) const
LLVM_ABI InstructionCost getMulAccReductionCost(bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add/...
LLVM_ABI bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
LLVM_ABI InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, bool ForPoisonSrc=true, ArrayRef< Value * > VL={}) const
Estimate the overhead of scalarizing an instruction.
LLVM_ABI bool isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned AddressSpace) const
Return true if the target supports masked load.
LLVM_ABI bool isMultiversionedFunction(const Function &F) const
Returns true if this is an instance of a function with multiple versions.
LLVM_ABI bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
LLVM_ABI bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
LLVM_ABI bool isAlwaysUniform(const Value *V) const
LLVM_ABI unsigned getAssumedAddrSpace(const Value *V) const
LLVM_ABI bool preferAlternateOpcodeVectorization() const
LLVM_ABI bool shouldDropLSRSolutionIfLessProfitable() const
Return true if LSR should drop a found solution if it's calculated to be less profitable than the bas...
LLVM_ABI bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
LLVM_ABI unsigned getPrefetchDistance() const
LLVM_ABI Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
LLVM_ABI bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
LLVM_ABI bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
LLVM_ABI InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo Op1Info={OK_AnyValue, OP_None}, OperandValueInfo Op2Info={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
LLVM_ABI MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
bool invalidate(Function &, const PreservedAnalyses &, FunctionAnalysisManager::Invalidator &)
Handle the invalidation of this information.
LLVM_ABI void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
LLVM_ABI bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
LLVM_ABI bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
LLVM_ABI std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
LLVM_ABI bool isProfitableLSRChainElement(Instruction *I) const
LLVM_ABI TypeSize getRegisterBitWidth(RegisterKind K) const
LLVM_ABI unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
LLVM_ABI bool hasActiveVectorLength() const
LLVM_ABI bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
LLVM_ABI bool preferFixedOverScalableIfEqualCost(bool IsEpilogue) const
LLVM_ABI bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
LLVM_ABI InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI std::optional< unsigned > getMaxVScale() const
LLVM_ABI InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const
LLVM_ABI bool allowVectorElementIndexingUsingGEP() const
Returns true if GEP should not be used to index into vectors for this target.
LLVM_ABI InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
LLVM_ABI bool isSingleThreaded() const
LLVM_ABI std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
InstructionCost getInstructionCost(const User *U, TargetCostKind CostKind) const
This is a helper function which calls the three-argument getInstructionCost with Operands which are t...
LLVM_ABI unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
LLVM_ABI InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, ArrayRef< int > Mask={}, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const
LLVM_ABI InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
LLVM_ABI unsigned getAtomicMemIntrinsicMaxElementSize() const
LLVM_ABI InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
LLVM_ABI bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
LLVM_ABI unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
static LLVM_ABI PartialReductionExtendKind getPartialReductionExtendKind(Instruction *I)
Get the kind of extension that an instruction represents.
LLVM_ABI bool shouldConsiderVectorizationRegPressure() const
LLVM_ABI bool enableWritePrefetching() const
LLVM_ABI bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
LLVM_ABI bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
LLVM_ABI bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
LLVM_ABI TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
Query the target what the preferred style of tail folding is.
LLVM_ABI InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType=nullptr, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
LLVM_ABI bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
Return true is the target supports interleaved access for the given vector type VTy,...
LLVM_ABI unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
LLVM_ABI bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
LLVM_ABI InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
LLVM_ABI unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
LLVM_ABI ReductionShuffle getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const
static LLVM_ABI OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
LLVM_ABI unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
LLVM_ABI bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_ABI PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
LLVM_ABI unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
LLVM_ABI bool isElementTypeLegalForScalableVector(Type *Ty) const
LLVM_ABI bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
LLVM_ABI unsigned getMaxPrefetchIterationsAhead() const
LLVM_ABI bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
LLVM_ABI ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
LLVM_ABI InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
LLVM_ABI bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
LLVM_ABI InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
LLVM_ABI bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
LLVM_ABI TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
LLVM_ABI InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF=FastMathFlags(), TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
@ TCK_CodeSize
Instruction code size.
@ TCK_SizeAndLatency
The weighted sum of size and latency.
@ TCK_Latency
The latency of instruction.
LLVM_ABI InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
LLVM_ABI bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
LLVM_ABI bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
LLVM_ABI bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
LLVM_ABI int getInliningLastCallToStaticBonus() const
LLVM_ABI InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
LLVM_ABI bool isVScaleKnownToBeAPowerOfTwo() const
LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
LLVM_ABI bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
LLVM_ABI bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
LLVM_ABI bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
static bool requiresOrderedReduction(std::optional< FastMathFlags > FMF)
A helper function to determine the type of reduction algorithm used for a given Opcode and set of Fas...
LLVM_ABI bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
LLVM_ABI std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
LLVM_ABI bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
LLVM_ABI InstructionCost getMemcpyCost(const Instruction *I) const
LLVM_ABI unsigned adjustInliningThreshold(const CallBase *CB) const
LLVM_ABI bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LLVM_ABI bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, int RetIdx) const
Identifies if the vector form of the intrinsic that returns a struct is overloaded at the struct elem...
LLVM_ABI unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
LLVM_ABI bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
LLVM_ABI bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const
LLVM_ABI Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
LLVM_ABI InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
LLVM_ABI unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
LLVM_ABI bool shouldPrefetchAddressSpace(unsigned AS) const
LLVM_ABI InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
LLVM_ABI unsigned getMinVectorRegisterBitWidth() const
LLVM_ABI InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr, TTI::TargetCostKind CostKind) const
LLVM_ABI bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
LLVM_ABI InstructionCost getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, ElementCount VF, PartialReductionExtendKind OpAExtend, PartialReductionExtendKind OpBExtend, std::optional< unsigned > BinOp, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
LLVM_ABI bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
LLVM_ABI bool hasArmWideBranch(bool Thumb) const
LLVM_ABI const char * getRegisterClassName(unsigned ClassID) const
LLVM_ABI bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
LLVM_ABI bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
LLVM_ABI BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
LLVM_ABI TargetTransformInfo(std::unique_ptr< const TargetTransformInfoImplBase > Impl)
Construct a TTI object using a type implementing the Concept API below.
LLVM_ABI bool preferInLoopReduction(RecurKind Kind, Type *Ty) const
LLVM_ABI unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
LLVM_ABI bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const
LLVM_ABI unsigned getCacheLineSize() const
LLVM_ABI bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
LLVM_ABI InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
LLVM_ABI int getInlinerVectorBonusPercent() const
LLVM_ABI unsigned getEpilogueVectorizationMinVF() const
LLVM_ABI void collectKernelLaunchBounds(const Function &F, SmallVectorImpl< std::pair< StringRef, int64_t > > &LB) const
Collect kernel launch bounds for F into LB.
PopcntSupportKind
Flags indicating the kind of support for population count.
LLVM_ABI bool preferPredicatedReductionSelect() const
LLVM_ABI InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
LLVM_ABI AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
LLVM_ABI bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
LLVM_ABI bool isLegalMaskedStore(Type *DataType, Align Alignment, unsigned AddressSpace) const
Return true if the target supports masked store.
LLVM_ABI bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
LLVM_ABI unsigned getInliningThresholdMultiplier() const
LLVM_ABI InstructionCost getBranchMispredictPenalty() const
Returns estimated penalty of a branch misprediction in latency.
LLVM_ABI unsigned getNumberOfRegisters(unsigned ClassID) const
LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
LLVM_ABI bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
LLVM_ABI bool supportsScalableVectors() const
LLVM_ABI bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
LLVM_ABI bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
LLVM_ABI std::optional< unsigned > getMinPageSize() const
LLVM_ABI bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
LLVM_ABI InstructionCost getInsertExtractValueCost(unsigned Opcode, TTI::TargetCostKind CostKind) const
LLVM_ABI bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
LLVM_ABI unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
LLVM_ABI std::optional< unsigned > getCacheSize(CacheLevel Level) const
LLVM_ABI std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
LLVM_ABI bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx) const
Identifies if the vector form of the intrinsic has a scalar operand.
LLVM_ABI bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
LLVM_ABI InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
TargetCostConstants
Underlying constants for 'cost' values in this interface.
@ TCC_Expensive
The cost of a 'div' instruction on x86.
@ TCC_Free
Expected to fold away in lowering.
@ TCC_Basic
The cost of a typical 'add' instruction.
LLVM_ABI bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
LLVM_ABI unsigned getMinTripCountTailFoldingThreshold() const
LLVM_ABI InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
LLVM_ABI unsigned getMaxInterleaveFactor(ElementCount VF) const
LLVM_ABI bool enableScalableVectorization() const
LLVM_ABI bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
LLVM_ABI bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
LLVM_ABI unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
LLVM_ABI bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
LLVM_ABI InstructionCost getExpandCompressMemoryOpCost(unsigned Opcode, Type *DataTy, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
LLVM_ABI unsigned getGISelRematGlobalCost() const
LLVM_ABI unsigned getNumBytesToPadGlobalArray(unsigned Size, Type *ArrayType) const
MemIndexedMode
The type of load/store indexing.
LLVM_ABI InstructionCost getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
LLVM_ABI bool areInlineCompatible(const Function *Caller, const Function *Callee) const
LLVM_ABI bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
LLVM_ABI InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
LLVM_ABI bool supportsTailCalls() const
If the target supports tail calls.
LLVM_ABI bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
LLVM_ABI bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
LLVM_ABI unsigned getNumberOfParts(Type *Tp) const
LLVM_ABI InstructionCost getOperandsScalarizationOverhead(ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing operands with the given types.
AddressingModeKind
Which addressing mode Loop Strength Reduction will try to generate.
@ AMK_PostIndexed
Prefer post-indexed addressing mode.
@ AMK_All
Consider all addressing modes.
@ AMK_PreIndexed
Prefer pre-indexed addressing mode.
@ AMK_None
Don't prefer any addressing mode.
LLVM_ABI InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
LLVM_ABI InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
LLVM_ABI bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
LLVM_ABI bool isProfitableToSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const
Return true if sinking I's operands to the same basic block as I is profitable, e....
LLVM_ABI void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
LLVM_ABI bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
LLVM_ABI bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
LLVM_ABI bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx) const
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
LLVM_ABI bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
LLVM_ABI bool shouldExpandReduction(const IntrinsicInst *II) const
LLVM_ABI uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
@ SK_Select
Selects elements from the corresponding lane of either source operand.
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
@ SK_Transpose
Transpose two vectors.
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
@ SK_Broadcast
Broadcast element 0 to all other elements.
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
@ SK_Reverse
Reverse the order of the vector.
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
LLVM_ABI APInt getFeatureMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function.
LLVM_ABI void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
LLVM_ABI InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
LLVM_ABI InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
CastContextHint
Represents a hint about the context in which a cast is used.
@ Reversed
The cast is used with a reversed load/store.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ Interleave
The cast is used with an interleaved load/store.
@ GatherScatter
The cast is used with a gather/scatter.
LLVM_ABI InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index, TTI::TargetCostKind CostKind) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition Value.h:75
Base class of all SIMD vector types.
CallInst * Call
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition CallingConv.h:34
This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.
friend class Instruction
Iterator for Instructions in a `BasicBlock.
Definition BasicBlock.h:73
This is an optimization pass for GlobalISel generic memory operations.
@ Length
Definition DWP.cpp:477
FunctionAddr VTableAddr Value
Definition InstrProf.h:137
LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ LLVM_MARK_AS_BITMASK_ENUM
Definition ModRef.h:37
TargetTransformInfo TTI
FunctionAddr VTableAddr uintptr_t uintptr_t Data
Definition InstrProf.h:189
LLVM_ABI ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
RecurKind
These are the kinds of recurrences that we support.
ArrayRef(const T &OneElt) -> ArrayRef< T >
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1847
@ DataAndControlFlowWithoutRuntimeCheck
Use predicate to control both data and control flow, but modify the trip count so that a runtime over...
@ DataWithEVL
Use predicated EVL instructions for tail-folding.
@ DataAndControlFlow
Use predicate to control both data and control flow.
@ DataWithoutLaneMask
Same as Data, but avoids using the get.active.lane.mask intrinsic to calculate the mask and instead i...
AnalysisManager< Function > FunctionAnalysisManager
Convenience typedef for the Function analysis manager.
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:851
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
A CRTP mix-in that provides informational APIs needed for analysis passes.
Definition PassManager.h:93
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition Analysis.h:29
Attributes of a target dependent hardware loop.
LLVM_ABI bool canAnalyze(LoopInfo &LI)
LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
SmallVector< InterestingMemoryOperand, 1 > InterestingOperands
Value * PtrVal
This is the pointer that the intrinsic is loading from or storing to.
InterleavedAccessInfo * IAI
TailFoldingInfo(TargetLibraryInfo *TLI, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI)
TargetLibraryInfo * TLI
LoopVectorizationLegality * LVL
unsigned Insns
TODO: Some of these could be merged.
Returns options for expansion of memcmp. IsZeroCmp is.
bool AllowPeeling
Allow peeling off loop iterations.
bool AllowLoopNestsPeeling
Allow peeling off loop iterations for loop nests.
bool PeelLast
Peel off the last PeelCount loop iterations.
bool PeelProfiledIterations
Allow peeling basing on profile.
unsigned PeelCount
A forced peeling factor (the number of bodied of the original loop that should be peeled off before t...
Describe known properties for a set of pointers.
unsigned IsKnownStride
True if distance between any two neigbouring pointers is a known value.
unsigned IsUnitStride
These properties only valid if SameBaseAddress is set.
unsigned IsSameBaseAddress
All the GEPs in a set have same base address.
Parameters that control the generic loop unrolling transformation.
unsigned Count
A forced unrolling factor (the number of concatenated bodies of the original loop in the unrolled loo...
bool UpperBound
Allow using trip count upper bound to unroll loops.
unsigned Threshold
The cost threshold for the unrolled loop.
bool Force
Apply loop unroll on any kind of loop (mainly to loops that fail runtime unrolling).
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold,...
bool UnrollVectorizedLoop
Don't disable runtime unroll for the loops which were vectorized.
unsigned DefaultUnrollRuntimeCount
Default unroll count for loops with run-time trip count.
unsigned MaxPercentThresholdBoost
If complete unrolling will reduce the cost of the loop, we will boost the Threshold by a certain perc...
bool RuntimeUnrollMultiExit
Allow runtime unrolling multi-exit loops.
unsigned SCEVExpansionBudget
Don't allow runtime unrolling if expanding the trip count takes more than SCEVExpansionBudget.
bool AddAdditionalAccumulators
Allow unrolling to add parallel reduction phis.
unsigned UnrollAndJamInnerLoopThreshold
Threshold for unroll and jam, for inner loop size.
unsigned MaxIterationsCountToAnalyze
Don't allow loop unrolling to simulate more than this number of iterations when checking full unroll ...
bool AllowRemainder
Allow generation of a loop remainder (extra iterations after unroll).
bool UnrollAndJam
Allow unroll and jam. Used to enable unroll and jam for the target.
bool UnrollRemainder
Allow unrolling of all the iterations of the runtime loop remainder.
unsigned FullUnrollMaxCount
Set the maximum unrolling factor for full unrolling.
unsigned PartialThreshold
The cost threshold for the unrolled loop, like Threshold, but used for partial/runtime unrolling (set...
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
unsigned OptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size (set to UINT_MAX to disable).
bool AllowExpensiveTripCount
Allow emitting expensive instructions (such as divisions) when computing the trip count of a loop for...
unsigned MaxUpperBound
Set the maximum upper bound of trip count.
VPLegalization(VPTransform EVLParamStrategy, VPTransform OpStrategy)