This file implements the lowering of LLVM calls to DAG nodes. More...

#include "MCTargetDesc/X86MCAsmInfo.h"
#include "X86.h"
#include "X86CallingConv.h"
#include "X86FrameLowering.h"
#include "X86ISelLowering.h"
#include "X86InstrBuilder.h"
#include "X86MachineFunctionInfo.h"
#include "X86TargetMachine.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/ObjCARCUtil.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Module.h"

Macros
#define	DEBUG_TYPE "x86-isel"

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static void	errorUnsupported (SelectionDAG &DAG, const SDLoc &dl, const char *Msg)
	Call this when the user attempts to do something unsupported, like returning a double without SSE2 enabled on x86_64.
static bool	shouldDisableRetRegFromCSR (CallingConv::ID CC)
	Returns true if a CC can dynamically exclude a register from the list of callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on the return registers.
static bool	shouldDisableArgRegFromCSR (CallingConv::ID CC)
	Returns true if a CC can dynamically exclude a register from the list of callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on the parameters.
static std::pair< MVT, unsigned >	handleMaskRegisterForCallingConv (unsigned NumElts, CallingConv::ID CC, const X86Subtarget &Subtarget)
static void	getMaxByValAlign (Type *Ty, Align &MaxAlign)
	Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.
static bool	isBitAligned (Align Alignment, uint64_t SizeInBits)
static bool	hasStackGuardSlotTLS (const Triple &TargetTriple)
static Constant *	SegmentOffset (IRBuilderBase &IRB, int Offset, unsigned AddressSpace)
static SDValue	lowerMasksToReg (const SDValue &ValArg, const EVT &ValLoc, const SDLoc &DL, SelectionDAG &DAG)
	Lowers masks values (v*i1) to the local register values.
static void	Passv64i1ArgInRegs (const SDLoc &DL, SelectionDAG &DAG, SDValue &Arg, SmallVectorImpl< std::pair< Register, SDValue > > &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget)
	Breaks v64i1 value into two registers and adds the new node to the DAG.
static SDValue	getv64i1Argument (CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &DL, const X86Subtarget &Subtarget, SDValue *InGlue=nullptr)
	Reads two 32 bit registers and creates a 64 bit mask value.
static SDValue	lowerRegToMasks (const SDValue &ValArg, const EVT &ValVT, const EVT &ValLoc, const SDLoc &DL, SelectionDAG &DAG)
	The function will lower a register of various sizes (8/16/32/64) to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
static SDValue	getPopFromX87Reg (SelectionDAG &DAG, SDValue Chain, const SDLoc &dl, Register Reg, EVT VT, SDValue Glue)
template<typename T>
static bool	hasCalleePopSRet (const SmallVectorImpl< T > &Args, const X86Subtarget &Subtarget)
	Determines whether Args, either a set of outgoing arguments to a call, or a set of incoming args of a call, contains an sret pointer that the callee pops.
static SDValue	CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
	Make a copy of an aggregate at address specified by "Src" to address "Dst" with size and alignment information specified by the specific parameter attribute.
static bool	canGuaranteeTCO (CallingConv::ID CC)
	Return true if the calling convention is one that we can guarantee TCO for.
static bool	mayTailCallThisCC (CallingConv::ID CC)
	Return true if we might ever do TCO for calls with this calling convention.
static bool	shouldGuaranteeTCO (CallingConv::ID CC, bool GuaranteedTailCallOpt)
	Return true if the function is being made into a tailcall target by changing its ABI.
static ArrayRef< MCPhysReg >	get64BitArgumentGPRs (CallingConv::ID CallConv, const X86Subtarget &Subtarget)
static ArrayRef< MCPhysReg >	get64BitArgumentXMMs (MachineFunction &MF, CallingConv::ID CallConv, const X86Subtarget &Subtarget)
static bool	isSortedByValueNo (ArrayRef< CCValAssign > ArgLocs)
static SDValue	EmitTailCallStoreRetAddr (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &dl)
	Emit a store of the return address if tail call optimization is performed and it is required (FPDiff!=0).
static bool	MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo MRI, const X86InstrInfo TII, const CCValAssign &VA)
	Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.
static bool	mayBeSRetTailCallCompatible (const TargetLowering::CallLoweringInfo &CLI, Register CallerSRetReg)

Detailed Description

This file implements the lowering of LLVM calls to DAG nodes.

Definition in file X86ISelLoweringCall.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "x86-isel"

Definition at line 31 of file X86ISelLoweringCall.cpp.

Function Documentation

◆ canGuaranteeTCO()

bool canGuaranteeTCO ( CallingConv::ID CC )

static

Return true if the calling convention is one that we can guarantee TCO for.

Definition at line 1269 of file X86ISelLoweringCall.cpp.

References llvm::CallingConv::Fast, llvm::CallingConv::GHC, llvm::CallingConv::HiPE, llvm::CallingConv::SwiftTail, llvm::CallingConv::Tail, and llvm::CallingConv::X86_RegCall.

◆ CreateCopyOfByValArgument()

SDValue CreateCopyOfByValArgument	(	SDValue	Src,
		SDValue	Dst,
		SDValue	Chain,
		ISD::ArgFlagsTy	Flags,
		SelectionDAG &	DAG,
		const SDLoc &	dl )

static

Make a copy of an aggregate at address specified by "Src" to address "Dst" with size and alignment information specified by the specific parameter attribute.

The copy will be passed as a byval function parameter.

Definition at line 1257 of file X86ISelLoweringCall.cpp.

References llvm::SelectionDAG::getIntPtrConstant(), and llvm::SelectionDAG::getMemcpy().

◆ EmitTailCallStoreRetAddr()

SDValue EmitTailCallStoreRetAddr	(	SelectionDAG &	DAG,
		MachineFunction &	MF,
		SDValue	Chain,
		SDValue	RetAddrFrIdx,
		EVT	PtrVT,
		unsigned	SlotSize,
		int	FPDiff,
		const SDLoc &	dl )

static

Emit a store of the return address if tail call optimization is performed and it is required (FPDiff!=0).

Definition at line 1984 of file X86ISelLoweringCall.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getMachineFunction(), and llvm::SelectionDAG::getStore().

◆ errorUnsupported()

void errorUnsupported	(	SelectionDAG &	DAG,
		const SDLoc &	dl,
		const char *	Msg )

static

Call this when the user attempts to do something unsupported, like returning a double without SSE2 enabled on x86_64.

This is not fatal, unlike report_fatal_error, so calling code should attempt to recover without crashing.

Definition at line 41 of file X86ISelLoweringCall.cpp.

References llvm::LLVMContext::diagnose(), llvm::SelectionDAG::getContext(), llvm::SDLoc::getDebugLoc(), llvm::MachineFunction::getFunction(), and llvm::SelectionDAG::getMachineFunction().

◆ get64BitArgumentGPRs()

ArrayRef< MCPhysReg > get64BitArgumentGPRs	(	CallingConv::ID	CallConv,
		const X86Subtarget &	Subtarget )

static

Definition at line 1433 of file X86ISelLoweringCall.cpp.

References assert(), and llvm::X86Subtarget::isCallingConvWin64().

◆ get64BitArgumentXMMs()

ArrayRef< MCPhysReg > get64BitArgumentXMMs	(	MachineFunction &	MF,
		CallingConv::ID	CallConv,
		const X86Subtarget &	Subtarget )

static

Definition at line 1451 of file X86ISelLoweringCall.cpp.

References assert(), llvm::X86Subtarget::hasSSE1(), and llvm::X86Subtarget::isCallingConvWin64().

◆ getMaxByValAlign()

void getMaxByValAlign	(	Type *	Ty,
		Align &	MaxAlign )

static

Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.

Definition at line 256 of file X86ISelLoweringCall.cpp.

References llvm::dyn_cast(), and getMaxByValAlign().

◆ getPopFromX87Reg()

SDValue getPopFromX87Reg	(	SelectionDAG &	DAG,
		SDValue	Chain,
		const SDLoc &	dl,
		Register	Reg,
		EVT	VT,
		SDValue	Glue )

static

Definition at line 1099 of file X86ISelLoweringCall.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ArrayRef(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getVTList(), llvm::X86ISD::POP_FROM_X87_REG, and Reg.

◆ getv64i1Argument()

SDValue getv64i1Argument	(	CCValAssign &	VA,
		CCValAssign &	NextVA,
		SDValue &	Root,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		const X86Subtarget &	Subtarget,
		SDValue *	InGlue = nullptr )

static

Reads two 32 bit registers and creates a 64 bit mask value.

Parameters

	VA	The current 32 bit value that need to be assigned.
	NextVA	The next 32 bit value that need to be assigned.
	Root	The parent DAG node.
[in,out]	InGlue	Represents SDvalue in the parent DAG node for glue purposes. In the case the DAG is already using physical register instead of virtual, we should glue our new SDValue to InGlue SDvalue.

Returns: a new SDvalue of size 64bit.

Definition at line 1015 of file X86ISelLoweringCall.cpp.

References llvm::MachineFunction::addLiveIn(), assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getCopyFromReg(), llvm::CCValAssign::getLocReg(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isRegLoc(), llvm::Lo, and Reg.

◆ handleMaskRegisterForCallingConv()

std::pair< MVT, unsigned > handleMaskRegisterForCallingConv	(	unsigned	NumElts,
		CallingConv::ID	CC,
		const X86Subtarget &	Subtarget )

static

Definition at line 70 of file X86ISelLoweringCall.cpp.

References llvm::CallingConv::Intel_OCL_BI, llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, llvm::isPowerOf2_32(), llvm::X86Subtarget::useAVX512Regs(), and llvm::CallingConv::X86_RegCall.

Referenced by llvm::X86TargetLowering::getNumRegistersForCallingConv(), and llvm::X86TargetLowering::getRegisterTypeForCallingConv().

◆ hasCalleePopSRet()

template<typename T>

bool hasCalleePopSRet	(	const SmallVectorImpl< T > &	Args,
		const X86Subtarget &	Subtarget )

static

Determines whether Args, either a set of outgoing arguments to a call, or a set of incoming args of a call, contains an sret pointer that the callee pops.

Definition at line 1222 of file X86ISelLoweringCall.cpp.

References llvm::X86Subtarget::getTargetTriple(), llvm::Triple::isOSMSVCRT(), and llvm::X86Subtarget::isTargetMCU().

◆ hasStackGuardSlotTLS()

bool hasStackGuardSlotTLS ( const Triple & TargetTriple )

static

Definition at line 548 of file X86ISelLoweringCall.cpp.

References llvm::Triple::isAndroid(), llvm::Triple::isAndroidVersionLT(), llvm::Triple::isOSFuchsia(), and llvm::Triple::isOSGlibc().

Referenced by llvm::X86TargetLowering::getIRStackGuard(), and llvm::X86TargetLowering::insertSSPDeclarations().

◆ isBitAligned()

bool isBitAligned	(	Align	Alignment,
		uint64_t	SizeInBits )

static

Definition at line 353 of file X86ISelLoweringCall.cpp.

References llvm::Align::value().

Referenced by llvm::X86TargetLowering::allowsMemoryAccess(), and llvm::X86TargetLowering::isMemoryAccessFast().

◆ isSortedByValueNo()

bool isSortedByValueNo ( ArrayRef< CCValAssign > ArgLocs )

static

Definition at line 1477 of file X86ISelLoweringCall.cpp.

References A(), B(), and llvm::is_sorted().

◆ lowerMasksToReg()

SDValue lowerMasksToReg	(	const SDValue &	ValArg,
		const EVT &	ValLoc,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

Lowers masks values (v*i1) to the local register values.

Returns: DAG node after lowering to register type

Definition at line 690 of file X86ISelLoweringCall.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), and llvm::SDValue::getValueType().

◆ lowerRegToMasks()

SDValue lowerRegToMasks	(	const SDValue &	ValArg,
		const EVT &	ValVT,
		const EVT &	ValLoc,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

The function will lower a register of various sizes (8/16/32/64) to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)

Returns: a DAG node contains the operand after lowering to mask type.

Definition at line 1066 of file X86ISelLoweringCall.cpp.

References assert(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm_unreachable, llvm::ISD::SCALAR_TO_VECTOR, llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.

◆ MatchingStackOffset()

bool MatchingStackOffset	(	SDValue	Arg,
		unsigned	Offset,
		ISD::ArgFlagsTy	Flags,
		MachineFrameInfo &	MFI,
		const MachineRegisterInfo *	MRI,
		const X86InstrInfo *	TII,
		const CCValAssign &	VA )

static

Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.

Definition at line 2682 of file X86ISelLoweringCall.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::AssertZext, llvm::cast(), llvm::ISD::CopyFromReg, llvm::dyn_cast(), llvm::ISD::FrameIndex, llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::FrameIndexSDNode::getIndex(), llvm::CCValAssign::getLocVT(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::MachineFrameInfo::isImmutableObjectIndex(), llvm::MachineFrameInfo::isObjectSExt(), llvm::MachineFrameInfo::isObjectZExt(), llvm::Register::isVirtual(), MRI, llvm::Offset, Ptr, TII, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

◆ mayBeSRetTailCallCompatible()

bool mayBeSRetTailCallCompatible	(	const TargetLowering::CallLoweringInfo &	CLI,
		Register	CallerSRetReg )

static

Definition at line 2776 of file X86ISelLoweringCall.cpp.

References llvm::cast(), llvm::ISD::CopyToReg, E(), llvm::User::getOperand(), llvm::TargetLowering::CallLoweringInfo::Outs, llvm::TargetLowering::CallLoweringInfo::OutVals, Reg, and llvm::SDNode::users().

◆ mayTailCallThisCC()

bool mayTailCallThisCC ( CallingConv::ID CC )

static

Return true if we might ever do TCO for calls with this calling convention.

Definition at line 1276 of file X86ISelLoweringCall.cpp.

References llvm::CallingConv::C, canGuaranteeTCO(), llvm::CallingConv::PreserveNone, llvm::CallingConv::Swift, llvm::CallingConv::Win64, llvm::CallingConv::X86_64_SysV, llvm::CallingConv::X86_FastCall, llvm::CallingConv::X86_StdCall, llvm::CallingConv::X86_ThisCall, and llvm::CallingConv::X86_VectorCall.

◆ Passv64i1ArgInRegs()

void Passv64i1ArgInRegs	(	const SDLoc &	DL,
		SelectionDAG &	DAG,
		SDValue &	Arg,
		SmallVectorImpl< std::pair< Register, SDValue > > &	RegsToPass,
		CCValAssign &	VA,
		CCValAssign &	NextVA,
		const X86Subtarget &	Subtarget )

static

Breaks v64i1 value into two registers and adds the new node to the DAG.

Definition at line 721 of file X86ISelLoweringCall.cpp.

References assert(), DL, llvm::SelectionDAG::getBitcast(), llvm::CCValAssign::getLocReg(), llvm::SDValue::getValueType(), llvm::Hi, llvm::CCValAssign::isRegLoc(), llvm::Lo, and llvm::SelectionDAG::SplitScalar().

◆ SegmentOffset()

Constant * SegmentOffset	(	IRBuilderBase &	IRB,
		int	Offset,
		unsigned	AddressSpace )

static

Definition at line 553 of file X86ISelLoweringCall.cpp.

References llvm::IRBuilderBase::getContext(), llvm::Type::getInt32Ty(), llvm::ConstantExpr::getIntToPtr(), llvm::IRBuilderBase::getPtrTy(), and llvm::Offset.

Referenced by llvm::X86TargetLowering::getIRStackGuard(), and llvm::X86TargetLowering::getSafeStackPointerLocation().

◆ shouldDisableArgRegFromCSR()

bool shouldDisableArgRegFromCSR ( CallingConv::ID CC )

static

Returns true if a CC can dynamically exclude a register from the list of callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on the parameters.

Definition at line 65 of file X86ISelLoweringCall.cpp.

References llvm::CallingConv::X86_RegCall.

◆ shouldDisableRetRegFromCSR()

bool shouldDisableRetRegFromCSR ( CallingConv::ID CC )

static

Returns true if a CC can dynamically exclude a register from the list of callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on the return registers.

Definition at line 51 of file X86ISelLoweringCall.cpp.

References llvm::CallingConv::PreserveAll, llvm::CallingConv::PreserveMost, and llvm::CallingConv::X86_RegCall.

◆ shouldGuaranteeTCO()

bool shouldGuaranteeTCO	(	CallingConv::ID	CC,
		bool	GuaranteedTailCallOpt )

static

Return true if the function is being made into a tailcall target by changing its ABI.

Definition at line 1298 of file X86ISelLoweringCall.cpp.

References canGuaranteeTCO(), llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.

◆ STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"	)

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ DEBUG_TYPE

Function Documentation

◆ canGuaranteeTCO()

◆ CreateCopyOfByValArgument()

◆ EmitTailCallStoreRetAddr()

◆ errorUnsupported()

◆ get64BitArgumentGPRs()

◆ get64BitArgumentXMMs()

◆ getMaxByValAlign()

◆ getPopFromX87Reg()

◆ getv64i1Argument()

◆ handleMaskRegisterForCallingConv()

◆ hasCalleePopSRet()

◆ hasStackGuardSlotTLS()

◆ isBitAligned()

◆ isSortedByValueNo()

◆ lowerMasksToReg()

◆ lowerRegToMasks()

◆ MatchingStackOffset()

◆ mayBeSRetTailCallCompatible()

◆ mayTailCallThisCC()

◆ Passv64i1ArgInRegs()

◆ SegmentOffset()

◆ shouldDisableArgRegFromCSR()

◆ shouldDisableRetRegFromCSR()

◆ shouldGuaranteeTCO()

◆ STATISTIC()