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LLVM 22.0.0git
llvm::AMDGPULegalizerInfo Class Referencefinal

#include "Target/AMDGPU/AMDGPULegalizerInfo.h"

Inheritance diagram for llvm::AMDGPULegalizerInfo:
[legend]

Public Member Functions

 AMDGPULegalizerInfo (const GCNSubtarget &ST, const GCNTargetMachine &TM)
bool legalizeCustom (LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override
 Called for instructions with the Custom LegalizationAction.
Register getSegmentAperture (unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeAddrSpaceCast (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFroundeven (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFceil (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFrem (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeIntrinsicTrunc (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeITOFP (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
bool legalizeFPTOI (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
bool legalizeMinNumMaxNum (LegalizerHelper &Helper, MachineInstr &MI) const
bool legalizeExtractVectorElt (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeInsertVectorElt (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeSinCos (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool buildPCRelGlobalAddress (Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, int64_t Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const
void buildAbsGlobalAddress (Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, MachineRegisterInfo &MRI) const
bool legalizeGlobalValue (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeLoad (LegalizerHelper &Helper, MachineInstr &MI) const
bool legalizeStore (LegalizerHelper &Helper, MachineInstr &MI) const
bool legalizeFMad (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeAtomicCmpXChg (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
std::pair< Register, RegistergetScaledLogInput (MachineIRBuilder &B, Register Src, unsigned Flags) const
bool legalizeFlog2 (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeFlogCommon (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeFlogUnsafe (MachineIRBuilder &B, Register Dst, Register Src, bool IsLog10, unsigned Flags) const
bool legalizeFExp2 (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeFExpUnsafe (MachineIRBuilder &B, Register Dst, Register Src, unsigned Flags) const
bool legalizeFExp (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeFPow (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeFFloor (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeBuildVector (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
void buildMultiply (LegalizerHelper &Helper, MutableArrayRef< Register > Accum, ArrayRef< Register > Src0, ArrayRef< Register > Src1, bool UsePartialMad64_32, bool SeparateOddAlignedProducts) const
bool legalizeMul (LegalizerHelper &Helper, MachineInstr &MI) const
bool legalizeCTLZ_CTTZ (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeCTLZ_ZERO_UNDEF (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
void buildLoadInputValue (Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg, const TargetRegisterClass *ArgRC, LLT ArgTy) const
bool legalizeWorkGroupId (MachineInstr &MI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ClusterIdPV, AMDGPUFunctionArgInfo::PreloadedValue ClusterMaxIdPV, AMDGPUFunctionArgInfo::PreloadedValue ClusterWorkGroupIdPV) const
bool loadInputValue (Register DstReg, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
bool legalizePointerAsRsrcIntrin (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 To create a buffer resource from a 64-bit pointer, mask off the upper 32 bits of the pointer and replace them with the stride argument, then merge_values everything together.
bool legalizePreloadedArgIntrin (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
bool legalizeWorkitemIDIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Register getKernargParameterPtr (MachineIRBuilder &B, int64_t Offset) const
bool legalizeKernargMemParameter (MachineInstr &MI, MachineIRBuilder &B, uint64_t Offset, Align Alignment=Align(4)) const
 Legalize a value that's loaded from kernel arguments.
bool legalizeUnsignedDIV_REM (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
void legalizeUnsignedDIV_REM32Impl (MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const
void legalizeUnsignedDIV_REM64Impl (MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const
bool legalizeSignedDIV_REM (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIV (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIV16 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIV32 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIV64 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFFREXP (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFastUnsafeFDIV (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFastUnsafeFDIV64 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIVFastIntrin (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFSQRTF16 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFSQRTF32 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFSQRTF64 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFSQRT (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeRsqClampIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool getImplicitArgPtr (Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeImplicitArgPtr (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool getLDSKernelId (Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeLDSKernelId (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeIsAddrSpace (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const
std::pair< Register, unsignedsplitBufferOffsets (MachineIRBuilder &B, Register OrigOffset) const
Register handleD16VData (MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg, bool ImageStore=false) const
 Handle register layout difference for f16 images for some subtargets.
Register fixStoreSourceType (MachineIRBuilder &B, Register VData, LLT MemTy, bool IsFormat) const
bool legalizeBufferStore (MachineInstr &MI, LegalizerHelper &Helper, bool IsTyped, bool IsFormat) const
bool legalizeBufferLoad (MachineInstr &MI, LegalizerHelper &Helper, bool IsFormat, bool IsTyped) const
bool legalizeBufferAtomic (MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const
bool legalizeBVHIntersectRayIntrinsic (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeBVHDualOrBVH8IntersectRayIntrinsic (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeLaneOp (LegalizerHelper &Helper, MachineInstr &MI, Intrinsic::ID IID) const
bool legalizeBVHIntrinsic (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeStackSave (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeWaveID (MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeConstHwRegRead (MachineInstr &MI, MachineIRBuilder &B, AMDGPU::Hwreg::Id HwReg, unsigned LowBit, unsigned Width) const
bool legalizeGetFPEnv (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeSetFPEnv (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeImageIntrinsic (MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const
 Rewrite image intrinsics to use register layouts expected by the subtarget.
bool legalizeSBufferLoad (LegalizerHelper &Helper, MachineInstr &MI) const
bool legalizeSBufferPrefetch (LegalizerHelper &Helper, MachineInstr &MI) const
bool legalizeTrap (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeTrapEndpgm (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeTrapHsaQueuePtr (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeTrapHsa (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeDebugTrap (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeIntrinsic (LegalizerHelper &Helper, MachineInstr &MI) const override
Public Member Functions inherited from llvm::LegalizerInfo
virtual ~LegalizerInfo ()=default
const LegacyLegalizerInfogetLegacyLegalizerInfo () const
LegacyLegalizerInfogetLegacyLegalizerInfo ()
unsigned getOpcodeIdxForOpcode (unsigned Opcode) const
unsigned getActionDefinitionsIdx (unsigned Opcode) const
void verify (const MCInstrInfo &MII) const
 Perform simple self-diagnostic and assert if there is anything obviously wrong with the actions set up.
const LegalizeRuleSetgetActionDefinitions (unsigned Opcode) const
 Get the action definitions for the given opcode.
LegalizeRuleSetgetActionDefinitionsBuilder (unsigned Opcode)
 Get the action definition builder for the given opcode.
LegalizeRuleSetgetActionDefinitionsBuilder (std::initializer_list< unsigned > Opcodes)
 Get the action definition builder for the given set of opcodes.
void aliasActionDefinitions (unsigned OpcodeTo, unsigned OpcodeFrom)
LegalizeActionStep getAction (const LegalityQuery &Query) const
 Determine what action should be taken to legalize the described instruction.
LegalizeActionStep getAction (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 Determine what action should be taken to legalize the given generic instruction.
bool isLegal (const LegalityQuery &Query) const
bool isLegalOrCustom (const LegalityQuery &Query) const
bool isLegal (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool isLegalOrCustom (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
virtual unsigned getExtOpcodeForWideningConstant (LLT SmallTy) const
 Return the opcode (SEXT/ZEXT/ANYEXT) that should be performed while widening a constant of type SmallTy which targets can override.

Detailed Description

Definition at line 30 of file AMDGPULegalizerInfo.h.

Constructor & Destructor Documentation

◆ AMDGPULegalizerInfo()

AMDGPULegalizerInfo::AMDGPULegalizerInfo ( const GCNSubtarget & ST,
const GCNTargetMachine & TM )

Definition at line 687 of file AMDGPULegalizerInfo.cpp.

References llvm::alignTo(), llvm::LegalityPredicates::all(), AllS32Vectors, AllS64Vectors, AllVectors, llvm::LegalizeRuleSet::alwaysLegal(), assert(), llvm::bit_floor(), llvm::LegalizeRuleSet::bitcastIf(), bitcastToRegisterType(), bitcastToVectorElement32(), llvm::AMDGPUAS::BUFFER_FAT_POINTER, llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::AMDGPUAS::BUFFER_STRIDED_POINTER, llvm::LegalizeMutations::changeTo(), llvm::LegalizeRuleSet::clampMaxNumElements(), llvm::LegalizeRuleSet::clampMaxNumElementsStrict(), llvm::LegalizeRuleSet::clampNumElements(), llvm::LegalizeRuleSet::clampScalar(), llvm::LegalizeRuleSet::clampScalarOrElt(), llvm::LegacyLegalizerInfo::computeTables(), llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::LegalizeRuleSet::custom(), llvm::LegalizeRuleSet::customFor(), llvm::LegalizeRuleSet::customIf(), llvm::LegalityPredicates::elementTypeIs(), elementTypeIsLegal(), F32, F64, llvm::LegalizeRuleSet::fewerElementsIf(), fewerEltsToSize64Vector(), llvm::LLT::fixed_vector(), llvm::AMDGPUAS::FLAT_ADDRESS, llvm::LegalizerInfo::getActionDefinitionsBuilder(), llvm::LLT::getAddressSpace(), llvm::LLT::getElementType(), llvm::ElementCount::getFixed(), llvm::LegalizerInfo::getLegacyLegalizerInfo(), llvm::LLT::getNumElements(), llvm::LLT::getScalarSizeInBits(), getScalarTypeFromMemDesc(), llvm::SIRegisterInfo::getSGPRClassForBitWidth(), llvm::LLT::getSizeInBits(), llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::has_single_bit(), hasBufferRsrcWorkaround(), isIllegalRegisterType(), isLoadStoreLegal(), llvm::LegalityPredicates::isPointer(), llvm::LLT::isPointer(), llvm::isPowerOf2_32(), isRegisterClassType(), isRegisterType(), llvm::LegalityPredicates::isScalar(), isSmallOddVector(), isTruncStoreToSizePowerOf2(), llvm::LLT::isVector(), isWideVec16(), llvm::LegalityPredicates::largerThan(), llvm::LegalizeRuleSet::legalFor(), llvm::LegalizeRuleSet::legalForCartesianProduct(), llvm::LegalizeRuleSet::legalIf(), llvm::AMDGPUAS::LOCAL_ADDRESS, llvm::Log2_32_Ceil(), llvm::LegalizeRuleSet::lower(), llvm::LegalizeRuleSet::lowerFor(), llvm::LegalizeRuleSet::lowerIf(), MaxRegisterSize, MaxScalar, llvm::LegalizeRuleSet::maxScalar(), llvm::LegalizeRuleSet::maxScalarIf(), maxSizeForAddrSpace(), llvm::LegalizeRuleSet::minScalar(), llvm::LegalizeRuleSet::minScalarOrElt(), llvm::LegalityQuery::MMODescrs, llvm::LegalizeRuleSet::moreElementsIf(), moreElementsToNextExistingRegClass(), moreEltsToNext32Bit(), llvm::Mul, llvm::NotAtomic, numElementsNotEven(), oneMoreElement(), llvm::LLT::pointer(), llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::AMDGPUAS::REGION_ADDRESS, S1, S128, S16, S256, S32, S512, S64, S8, llvm::LegalityPredicates::sameSize(), llvm::LLT::scalar(), llvm::LegalizeMutations::scalarize(), llvm::LegalizeRuleSet::scalarize(), llvm::LegalityPredicates::scalarNarrowerThan(), llvm::LegalityPredicates::scalarOrEltNarrowerThan(), llvm::LegalityPredicates::scalarOrEltWiderThan(), llvm::LLT::scalarOrVector(), llvm::LegalizeRuleSet::scalarSameSizeAs(), llvm::AMDGPUSubtarget::SEA_ISLANDS, shouldBitcastLoadStoreType(), shouldWidenLoad(), llvm::LegalityPredicates::sizeIs(), sizeIsMultipleOf32(), llvm::LegalityPredicates::smallerThan(), llvm::LegalityPredicates::typeInSet(), llvm::LegalityPredicates::typeIs(), llvm::LegalityPredicates::typeIsNot(), llvm::LegalityQuery::Types, llvm::LegalizeRuleSet::unsupported(), unsupported(), llvm::LegalizeRuleSet::unsupportedFor(), llvm::LegalizeRuleSet::unsupportedIf(), V16S32, V16S64, V2BF16, V2F16, V2S16, V2S32, V2S64, V2S8, V32S32, V4S16, V4S32, vectorSmallerThan(), vectorWiderThan(), verify, llvm::LegalizeRuleSet::widenScalarIf(), llvm::LegalizeMutations::widenScalarOrEltToNextPow2(), llvm::LegalizeRuleSet::widenScalarToNextMultipleOf(), and llvm::LegalizeRuleSet::widenScalarToNextPow2().

Member Function Documentation

◆ buildAbsGlobalAddress()

void AMDGPULegalizerInfo::buildAbsGlobalAddress ( Register DstReg,
LLT PtrTy,
MachineIRBuilder & B,
const GlobalValue * GV,
MachineRegisterInfo & MRI ) const

◆ buildLoadInputValue()

◆ buildMultiply()

◆ buildPCRelGlobalAddress()

◆ fixStoreSourceType()

Register AMDGPULegalizerInfo::fixStoreSourceType ( MachineIRBuilder & B,
Register VData,
LLT MemTy,
bool IsFormat ) const

◆ getImplicitArgPtr()

◆ getKernargParameterPtr()

◆ getLDSKernelId()

bool AMDGPULegalizerInfo::getLDSKernelId ( Register DstReg,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ getScaledLogInput()

◆ getSegmentAperture()

◆ handleD16VData()

Register AMDGPULegalizerInfo::handleD16VData ( MachineIRBuilder & B,
MachineRegisterInfo & MRI,
Register Reg,
bool ImageStore = false ) const

◆ legalizeAddrSpaceCast()

◆ legalizeAtomicCmpXChg()

bool AMDGPULegalizerInfo::legalizeAtomicCmpXChg ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeBufferAtomic()

bool AMDGPULegalizerInfo::legalizeBufferAtomic ( MachineInstr & MI,
MachineIRBuilder & B,
Intrinsic::ID IID ) const

◆ legalizeBufferLoad()

◆ legalizeBufferStore()

◆ legalizeBuildVector()

bool AMDGPULegalizerInfo::legalizeBuildVector ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 3989 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), llvm::LLT::fixed_vector(), Merge, MI, MRI, S16, S32, and llvm::LLT::scalar().

Referenced by legalizeCustom().

◆ legalizeBVHDualOrBVH8IntersectRayIntrinsic()

bool AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic ( MachineInstr & MI,
MachineIRBuilder & B ) const

◆ legalizeBVHIntersectRayIntrinsic()

◆ legalizeBVHIntrinsic()

bool llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic ( MachineInstr & MI,
MachineIRBuilder & B ) const

References B(), MI, and MRI.

◆ legalizeConstHwRegRead()

bool AMDGPULegalizerInfo::legalizeConstHwRegRead ( MachineInstr & MI,
MachineIRBuilder & B,
AMDGPU::Hwreg::Id HwReg,
unsigned LowBit,
unsigned Width ) const

◆ legalizeCTLZ_CTTZ()

bool AMDGPULegalizerInfo::legalizeCTLZ_CTTZ ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 4328 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::LLT::getSizeInBits(), MI, and MRI.

Referenced by legalizeCustom().

◆ legalizeCTLZ_ZERO_UNDEF()

bool AMDGPULegalizerInfo::legalizeCTLZ_ZERO_UNDEF ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 4346 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), getReg(), MI, MRI, and S32.

Referenced by legalizeCustom().

◆ legalizeCustom()

◆ legalizeDebugTrap()

◆ legalizeExtractVectorElt()

◆ legalizeFastUnsafeFDIV()

bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeFastUnsafeFDIV64()

bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64 ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 5129 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::MachineInstr::FmAfn, MI, MRI, X, and Y.

Referenced by legalizeFDIV64().

◆ legalizeFceil()

bool AMDGPULegalizerInfo::legalizeFceil ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeFDIV()

bool AMDGPULegalizerInfo::legalizeFDIV ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeFDIV16()

bool AMDGPULegalizerInfo::legalizeFDIV16 ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 5164 of file AMDGPULegalizerInfo.cpp.

References B(), legalizeFastUnsafeFDIV(), MI, MRI, S16, S32, and llvm::LLT::scalar().

Referenced by legalizeFDIV().

◆ legalizeFDIV32()

◆ legalizeFDIV64()

bool AMDGPULegalizerInfo::legalizeFDIV64 ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeFDIVFastIntrin()

bool AMDGPULegalizerInfo::legalizeFDIVFastIntrin ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 5453 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::CmpInst::FCMP_OGT, MI, MRI, S1, S32, and llvm::LLT::scalar().

Referenced by legalizeIntrinsic().

◆ legalizeFExp()

◆ legalizeFExp2()

bool AMDGPULegalizerInfo::legalizeFExp2 ( MachineInstr & MI,
MachineIRBuilder & B ) const

◆ legalizeFExpUnsafe()

bool AMDGPULegalizerInfo::legalizeFExpUnsafe ( MachineIRBuilder & B,
Register Dst,
Register Src,
unsigned Flags ) const

◆ legalizeFFloor()

◆ legalizeFFREXP()

bool AMDGPULegalizerInfo::legalizeFFREXP ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeFlog2()

bool AMDGPULegalizerInfo::legalizeFlog2 ( MachineInstr & MI,
MachineIRBuilder & B ) const

Definition at line 3440 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), F32, getScaledLogInput(), llvm::Log2(), MI, and llvm::LLT::scalar().

Referenced by legalizeCustom().

◆ legalizeFlogCommon()

◆ legalizeFlogUnsafe()

bool AMDGPULegalizerInfo::legalizeFlogUnsafe ( MachineIRBuilder & B,
Register Dst,
Register Src,
bool IsLog10,
unsigned Flags ) const

◆ legalizeFMad()

◆ legalizeFPow()

bool AMDGPULegalizerInfo::legalizeFPow ( MachineInstr & MI,
MachineIRBuilder & B ) const

Definition at line 3884 of file AMDGPULegalizerInfo.cpp.

References B(), F32, llvm::LLT::float16(), llvm::LLT::float32(), MI, and llvm::Mul.

Referenced by legalizeCustom().

◆ legalizeFPTOI()

bool AMDGPULegalizerInfo::legalizeFPTOI ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B,
bool Signed ) const

◆ legalizeFrem()

bool AMDGPULegalizerInfo::legalizeFrem ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 2609 of file AMDGPULegalizerInfo.cpp.

References B(), MI, and MRI.

Referenced by legalizeCustom().

◆ legalizeFroundeven()

bool AMDGPULegalizerInfo::legalizeFroundeven ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeFSQRT()

bool AMDGPULegalizerInfo::legalizeFSQRT ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeFSQRTF16()

bool AMDGPULegalizerInfo::legalizeFSQRTF16 ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 5488 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), F32, llvm::Log2(), MI, MRI, and llvm::LLT::scalar().

Referenced by legalizeFSQRT().

◆ legalizeFSQRTF32()

◆ legalizeFSQRTF64()

bool AMDGPULegalizerInfo::legalizeFSQRTF64 ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeGetFPEnv()

bool AMDGPULegalizerInfo::legalizeGetFPEnv ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 7570 of file AMDGPULegalizerInfo.cpp.

References B(), FPEnvModeBitField, FPEnvTrapBitField, MI, MRI, S32, and S64.

Referenced by legalizeCustom().

◆ legalizeGlobalValue()

◆ legalizeImageIntrinsic()

bool AMDGPULegalizerInfo::legalizeImageIntrinsic ( MachineInstr & MI,
MachineIRBuilder & B,
GISelChangeObserver & Observer,
const AMDGPU::ImageDimIntrinsicInfo * Intr ) const

Rewrite image intrinsics to use register layouts expected by the subtarget.

Depending on the subtarget, load/store with 16-bit element data need to be rewritten to use the low half of 32-bit registers, or directly use a packed layout. 16-bit addresses should also sometimes be packed into 32-bit registers.

We don't want to directly select image instructions just yet, but also want to exposes all register repacking to the legalizer/combiners. We also don't want a selected instruction entering RegBankSelect. In order to avoid defining a multitude of intermediate image instructions, directly hack on the intrinsic's arguments. In cases like a16 addresses, this requires padding now unnecessary arguments with $noreg.

Definition at line 6695 of file AMDGPULegalizerInfo.cpp.

References llvm::ArrayRef(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Atomic, llvm::AMDGPU::MIMGBaseOpcodeInfo::AtomicX2, B(), llvm::AMDGPU::ImageDimIntrinsicInfo::BaseOpcode, llvm::AMDGPU::MIMGBaseOpcodeInfo::BaseOpcode, llvm::GISelChangeObserver::changedInstr(), llvm::GISelChangeObserver::changingInstr(), Concat, convertImageAddrToPacked(), llvm::AMDGPU::ImageDimIntrinsicInfo::CoordStart, llvm::MachineOperand::CreateImm(), llvm::AMDGPU::ImageDimIntrinsicInfo::DMaskIndex, llvm::LLT::fixed_vector(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Gather4, llvm::ElementCount::getFixed(), llvm::SrcOp::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::SrcOp::getReg(), llvm::LLT::getScalarType(), llvm::LLT::getSizeInBits(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::AMDGPU::ImageDimIntrinsicInfo::GradientStart, handleD16VData(), I, llvm::LLT::isVector(), llvm::make_scope_exit(), MI, MRI, llvm::AMDGPU::MIMGBaseOpcodeInfo::NoReturn, llvm::AMDGPU::ImageDimIntrinsicInfo::NumVAddrs, packImage16bitOpsToDwords(), llvm::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::resize(), S16, S32, llvm::AMDGPU::MIMGBaseOpcodeInfo::Sampler, llvm::LLT::scalar(), llvm::LLT::scalarOrVector(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Store, V2S16, V4S16, and llvm::AMDGPU::ImageDimIntrinsicInfo::VAddrStart.

Referenced by legalizeIntrinsic().

◆ legalizeImplicitArgPtr()

◆ legalizeInsertVectorElt()

◆ legalizeIntrinsic()

bool AMDGPULegalizerInfo::legalizeIntrinsic ( LegalizerHelper & Helper,
MachineInstr & MI ) const
overridevirtual
Returns
true if MI is either legal or has been legalized and false if not legal. Return true if MI is either legal or has been legalized and false if not legal.

Reimplemented from llvm::LegalizerInfo.

Definition at line 7610 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), llvm::cast(), llvm::GISelChangeObserver::changedInstr(), llvm::GISelChangeObserver::changingInstr(), llvm::AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_X, llvm::AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Y, llvm::AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Z, llvm::AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_FLAT_ID, llvm::AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_X, llvm::AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Y, llvm::AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Z, llvm::AMDGPUFunctionArgInfo::DISPATCH_ID, llvm::AMDGPUFunctionArgInfo::DISPATCH_PTR, llvm::AMDGPU::getImageDimIntrinsicInfo(), llvm::MachineInstr::getOperand(), llvm::AMDGPU::Hwreg::ID_IB_STS2, llvm::AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR, llvm::AMDGPU::isKernel(), llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR, llvm::AMDGPUFunctionArgInfo::LDS_KERNEL_ID, legalizeAddrSpaceCast(), legalizeBufferAtomic(), legalizeBufferLoad(), legalizeBufferStore(), legalizeBVHDualOrBVH8IntersectRayIntrinsic(), legalizeBVHIntersectRayIntrinsic(), legalizeConstHwRegRead(), legalizeFDIVFastIntrin(), legalizeImageIntrinsic(), legalizeImplicitArgPtr(), legalizeIsAddrSpace(), legalizeKernargMemParameter(), legalizeLaneOp(), legalizePointerAsRsrcIntrin(), legalizePreloadedArgIntrin(), legalizeRsqClampIntrinsic(), legalizeSBufferLoad(), legalizeSBufferPrefetch(), legalizeWaveID(), legalizeWorkGroupId(), legalizeWorkitemIDIntrinsic(), llvm::AMDGPUAS::LOCAL_ADDRESS, llvm::SI::KernelInputOffsets::LOCAL_SIZE_X, llvm::SI::KernelInputOffsets::LOCAL_SIZE_Y, llvm::SI::KernelInputOffsets::LOCAL_SIZE_Z, MI, llvm::LegalizerHelper::MIRBuilder, MRI, llvm::SI::KernelInputOffsets::NGROUPS_X, llvm::SI::KernelInputOffsets::NGROUPS_Y, llvm::SI::KernelInputOffsets::NGROUPS_Z, llvm::LegalizerHelper::Observer, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::AMDGPUFunctionArgInfo::QUEUE_PTR, S32, S64, llvm::LLT::scalar(), llvm::MachineOperand::setMBB(), std::swap(), TRI, verifyCFIntrinsic(), llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z, llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_X, llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Y, and llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Z.

◆ legalizeIntrinsicTrunc()

bool AMDGPULegalizerInfo::legalizeIntrinsicTrunc ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeIsAddrSpace()

bool AMDGPULegalizerInfo::legalizeIsAddrSpace ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B,
unsigned AddrSpace ) const

◆ legalizeITOFP()

bool AMDGPULegalizerInfo::legalizeITOFP ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B,
bool Signed ) const

Definition at line 2688 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), MI, MRI, S32, S64, llvm::LLT::scalar(), llvm::Signed, and X.

Referenced by legalizeCustom().

◆ legalizeKernargMemParameter()

bool AMDGPULegalizerInfo::legalizeKernargMemParameter ( MachineInstr & MI,
MachineIRBuilder & B,
uint64_t Offset,
Align Alignment = Align(4) ) const

Legalize a value that's loaded from kernel arguments.

This is only used by legacy intrinsics.

Definition at line 4724 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), llvm::AMDGPUAS::CONSTANT_ADDRESS, getKernargParameterPtr(), MI, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::Offset, Ptr, and llvm::LLT::scalar().

Referenced by legalizeIntrinsic().

◆ legalizeLaneOp()

◆ legalizeLDSKernelId()

◆ legalizeLoad()

◆ legalizeMinNumMaxNum()

◆ legalizeMul()

◆ legalizePointerAsRsrcIntrin()

bool AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

To create a buffer resource from a 64-bit pointer, mask off the upper 32 bits of the pointer and replace them with the stride argument, then merge_values everything together.

In the common case of a raw buffer (the stride component is 0), we can just AND off the upper half.

Definition at line 5899 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::getIConstantVRegValWithLookThrough(), llvm::MachineInstrBuilder::getReg(), llvm::Masked, MI, MRI, S32, and llvm::LLT::scalar().

Referenced by legalizeIntrinsic().

◆ legalizePreloadedArgIntrin()

bool AMDGPULegalizerInfo::legalizePreloadedArgIntrin ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B,
AMDGPUFunctionArgInfo::PreloadedValue ArgType ) const

Definition at line 4650 of file AMDGPULegalizerInfo.cpp.

References B(), loadInputValue(), MI, and MRI.

Referenced by legalizeImplicitArgPtr(), legalizeIntrinsic(), and legalizeLDSKernelId().

◆ legalizeRsqClampIntrinsic()

◆ legalizeSBufferLoad()

◆ legalizeSBufferPrefetch()

◆ legalizeSetFPEnv()

bool AMDGPULegalizerInfo::legalizeSetFPEnv ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 7590 of file AMDGPULegalizerInfo.cpp.

References B(), FPEnvModeBitField, FPEnvTrapBitField, MI, MRI, S32, and S64.

Referenced by legalizeCustom().

◆ legalizeSignedDIV_REM()

bool AMDGPULegalizerInfo::legalizeSignedDIV_REM ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeSinCos()

bool AMDGPULegalizerInfo::legalizeSinCos ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 2954 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::numbers::inv_pi, MI, and MRI.

Referenced by legalizeCustom().

◆ legalizeStackSave()

bool AMDGPULegalizerInfo::legalizeStackSave ( MachineInstr & MI,
MachineIRBuilder & B ) const

◆ legalizeStore()

◆ legalizeTrap()

bool AMDGPULegalizerInfo::legalizeTrap ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeTrapEndpgm()

◆ legalizeTrapHsa()

bool AMDGPULegalizerInfo::legalizeTrapHsa ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

Definition at line 7279 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::GCNSubtarget::LLVMAMDHSATrap, MI, and MRI.

Referenced by legalizeTrap().

◆ legalizeTrapHsaQueuePtr()

◆ legalizeUnsignedDIV_REM()

bool AMDGPULegalizerInfo::legalizeUnsignedDIV_REM ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineIRBuilder & B ) const

◆ legalizeUnsignedDIV_REM32Impl()

void AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl ( MachineIRBuilder & B,
Register DstDivReg,
Register DstRemReg,
Register Num,
Register Den ) const

◆ legalizeUnsignedDIV_REM64Impl()

void AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl ( MachineIRBuilder & B,
Register DstDivReg,
Register DstRemReg,
Register Num,
Register Den ) const

◆ legalizeWaveID()

bool AMDGPULegalizerInfo::legalizeWaveID ( MachineInstr & MI,
MachineIRBuilder & B ) const

Definition at line 7533 of file AMDGPULegalizerInfo.cpp.

References B(), MI, Register, S32, and llvm::LLT::scalar().

Referenced by legalizeIntrinsic().

◆ legalizeWorkGroupId()

◆ legalizeWorkitemIDIntrinsic()

◆ loadInputValue()

◆ splitBufferOffsets()


The documentation for this class was generated from the following files: