llvm::GCNTTIImpl Class Reference

#include "Target/AMDGPU/AMDGPUTargetTransformInfo.h"

Inheritance diagram for llvm::GCNTTIImpl:

Public Types
enum class	KnownIEEEMode { Unknown , On , Off }

Public Member Functions
	GCNTTIImpl (const AMDGPUTargetMachine *TM, const Function &F)
bool	hasBranchDivergence (const Function *F=nullptr) const override
void	getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const override
void	getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP) const override
TTI::PopcntSupportKind	getPopcntSupport (unsigned TyWidth) const override
unsigned	getNumberOfRegisters (unsigned RCID) const override
TypeSize	getRegisterBitWidth (TargetTransformInfo::RegisterKind Vector) const override
unsigned	getMinVectorRegisterBitWidth () const override
unsigned	getMaximumVF (unsigned ElemWidth, unsigned Opcode) const override
unsigned	getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const override
unsigned	getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const override
unsigned	getLoadStoreVecRegBitWidth (unsigned AddrSpace) const override
bool	isLegalToVectorizeMemChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool	isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const override
bool	isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const override
uint64_t	getMaxMemIntrinsicInlineSizeThreshold () const override
Type *	getMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize) const override
void	getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize) const override
unsigned	getMaxInterleaveFactor (ElementCount VF) const override
bool	getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info) const override
InstructionCost	getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const override
InstructionCost	getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override
bool	isInlineAsmSourceOfDivergence (const CallInst *CI, ArrayRef< unsigned > Indices={}) const
	Analyze if the results of inline asm are divergent.
InstructionCost	getVectorInstrCost (unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, const Value *Op0, const Value *Op1) const override
bool	isReadRegisterSourceOfDivergence (const IntrinsicInst *ReadReg) const
bool	isSourceOfDivergence (const Value *V) const override
bool	isAlwaysUniform (const Value *V) const override
bool	isValidAddrSpaceCast (unsigned FromAS, unsigned ToAS) const override
bool	addrspacesMayAlias (unsigned AS0, unsigned AS1) const override
unsigned	getFlatAddressSpace () const override
bool	collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const override
bool	canHaveNonUndefGlobalInitializerInAddressSpace (unsigned AS) const override
Value *	rewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const override
bool	canSimplifyLegacyMulToMul (const Instruction &I, const Value *Op0, const Value *Op1, InstCombiner &IC) const
bool	simplifyDemandedLaneMaskArg (InstCombiner &IC, IntrinsicInst &II, unsigned LaneAgIdx) const
	Simplify a lane index operand (e.g.
std::optional< Instruction * >	instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const override
Value *	simplifyAMDGCNLaneIntrinsicDemanded (InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts, APInt &UndefElts) const
Instruction *	hoistLaneIntrinsicThroughOperand (InstCombiner &IC, IntrinsicInst &II) const
std::optional< Value * >	simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const override
InstructionCost	getVectorSplitCost () const
InstructionCost	getShuffleCost (TTI::ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const override
bool	isProfitableToSinkOperands (Instruction *I, SmallVectorImpl< Use * > &Ops) const override
	Whether it is profitable to sink the operands of an Instruction I to the basic block of I.
bool	areInlineCompatible (const Function *Caller, const Function *Callee) const override
int	getInliningLastCallToStaticBonus () const override
unsigned	getInliningThresholdMultiplier () const override
unsigned	adjustInliningThreshold (const CallBase *CB) const override
unsigned	getCallerAllocaCost (const CallBase *CB, const AllocaInst *AI) const override
int	getInlinerVectorBonusPercent () const override
InstructionCost	getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const override
InstructionCost	getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const override
	Get intrinsic cost based on arguments.
InstructionCost	getMinMaxReductionCost (Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const override
	Try to calculate op costs for min/max reduction operations.
unsigned	getCacheLineSize () const override
	Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.
unsigned	getPrefetchDistance () const override
	How much before a load we should place the prefetch instruction.
bool	shouldPrefetchAddressSpace (unsigned AS) const override
void	collectKernelLaunchBounds (const Function &F, SmallVectorImpl< std::pair< StringRef, int64_t > > &LB) const override
KnownIEEEMode	fpenvIEEEMode (const Instruction &I) const
	Return KnownIEEEMode::On if we know if the use context can assume "amdgpu-ieee"="true" and KnownIEEEMode::Off if we can assume "amdgpu-ieee"="false".
InstructionCost	getMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr) const override
	Account for loads of i8 vector types to have reduced cost.
unsigned	getNumberOfParts (Type *Tp) const override
	When counting parts on AMD GPUs, account for i8s being grouped together under a single i32 value.
InstructionCost	getVectorInstrCost (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Scalar, ArrayRef< std::tuple< Value *, User *, int > > ScalarUserAndIdx) const override
InstructionCost	getVectorInstrCost (const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const override
Public Member Functions inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
bool	allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const override
bool	isNoopAddrSpaceCast (unsigned FromAS, unsigned ToAS) const override
unsigned	getAssumedAddrSpace (const Value *V) const override
bool	isSingleThreaded () const override
std::pair< const Value *, unsigned >	getPredicatedAddrSpace (const Value *V) const override
bool	isLegalAddImmediate (int64_t imm) const override
bool	isLegalAddScalableImmediate (int64_t Imm) const override
bool	isLegalICmpImmediate (int64_t imm) const override
bool	isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr, int64_t ScalableOffset=0) const override
int64_t	getPreferredLargeGEPBaseOffset (int64_t MinOffset, int64_t MaxOffset)
unsigned	getStoreMinimumVF (unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const override
bool	isIndexedLoadLegal (TTI::MemIndexedMode M, Type *Ty) const override
bool	isIndexedStoreLegal (TTI::MemIndexedMode M, Type *Ty) const override
bool	isLSRCostLess (const TTI::LSRCost &C1, const TTI::LSRCost &C2) const override
bool	isNumRegsMajorCostOfLSR () const override
bool	shouldDropLSRSolutionIfLessProfitable () const override
bool	isProfitableLSRChainElement (Instruction *I) const override
InstructionCost	getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const override
bool	isTruncateFree (Type *Ty1, Type *Ty2) const override
bool	isProfitableToHoist (Instruction *I) const override
bool	useAA () const override
bool	isTypeLegal (Type *Ty) const override
unsigned	getRegUsageForType (Type *Ty) const override
InstructionCost	getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind) const override
unsigned	getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JumpTableSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const override
bool	shouldBuildLookupTables () const override
bool	shouldBuildRelLookupTables () const override
bool	haveFastSqrt (Type *Ty) const override
bool	isFCmpOrdCheaperThanFCmpZero (Type *Ty) const override
InstructionCost	getFPOpCost (Type *Ty) const override
bool	preferToKeepConstantsAttached (const Instruction &Inst, const Function &Fn) const override
bool	isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const override
unsigned	getEpilogueVectorizationMinVF () const override
bool	preferPredicateOverEpilogue (TailFoldingInfo *TFI) const override
TailFoldingStyle	getPreferredTailFoldingStyle (bool IVUpdateMayOverflow=true) const override
std::optional< Value * >	simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const override
virtual std::optional< unsigned >	getCacheSize (TargetTransformInfo::CacheLevel Level) const override
virtual std::optional< unsigned >	getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const override
virtual unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
virtual unsigned	getMaxPrefetchIterationsAhead () const override
virtual bool	enableWritePrefetching () const override
std::optional< unsigned >	getMaxVScale () const override
std::optional< unsigned >	getVScaleForTuning () const override
bool	isVScaleKnownToBeAPowerOfTwo () const override
InstructionCost	getScalarizationOverhead (VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, bool ForPoisonSrc=true, ArrayRef< Value * > VL={}) const override
	Estimate the overhead of scalarizing an instruction.
bool	isTargetIntrinsicTriviallyScalarizable (Intrinsic::ID ID) const override
bool	isTargetIntrinsicWithScalarOpAtArg (Intrinsic::ID ID, unsigned ScalarOpdIdx) const override
bool	isTargetIntrinsicWithOverloadTypeAtArg (Intrinsic::ID ID, int OpdIdx) const override
bool	isTargetIntrinsicWithStructReturnOverloadAtField (Intrinsic::ID ID, int RetIdx) const override
InstructionCost	getScalarizationOverhead (VectorType *InTy, bool Insert, bool Extract, TTI::TargetCostKind CostKind) const
	Helper wrapper for the DemandedElts variant of getScalarizationOverhead.
InstructionCost	getOperandsScalarizationOverhead (ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const override
	Estimate the overhead of scalarizing an instruction's operands.
InstructionCost	getScalarizationOverhead (VectorType *RetTy, ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
	Estimate the overhead of scalarizing the inputs and outputs of an instruction, with return type RetTy and arguments Args of type Tys.
std::pair< InstructionCost, MVT >	getTypeLegalizationCost (Type *Ty) const
	Estimate the cost of type-legalization and the legalized type.
TTI::ShuffleKind	improveShuffleKindFromMask (TTI::ShuffleKind Kind, ArrayRef< int > Mask, VectorType *SrcTy, int &Index, VectorType *&SubTy) const
InstructionCost	getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override
InstructionCost	getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index, TTI::TargetCostKind CostKind) const override
InstructionCost	getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr) const override
InstructionCost	getIndexedVectorInstrCostFromEnd (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const override
InstructionCost	getReplicationShuffleCost (Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const override
InstructionCost	getMaskedMemoryOpCost (unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const override
InstructionCost	getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override
InstructionCost	getExpandCompressMemoryOpCost (unsigned Opcode, Type *DataTy, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override
InstructionCost	getStridedMemoryOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const override
InstructionCost	getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false) const override
InstructionCost	getTypeBasedIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
	Get intrinsic cost based on argument types.
InstructionCost	getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const override
	Compute a cost of the given call instruction.
InstructionCost	getAddressComputationCost (Type *PtrTy, ScalarEvolution *, const SCEV *, TTI::TargetCostKind) const override
InstructionCost	getTreeReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind) const
	Try to calculate arithmetic and shuffle op costs for reduction intrinsics.
InstructionCost	getOrderedReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind) const
	Try to calculate the cost of performing strict (in-order) reductions, which involves doing a sequence of floating point additions in lane order, starting with an initial value.
InstructionCost	getExtendedReductionCost (unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const override
InstructionCost	getMulAccReductionCost (bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const override
InstructionCost	getVectorSplitCost () const
Public Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< T >
InstructionCost	getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind) const override
InstructionCost	getPointersChainCost (ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind) const override
InstructionCost	getInstructionCost (const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const override
bool	isExpensiveToSpeculativelyExecute (const Instruction *I) const override
bool	supportsTailCallFor (const CallBase *CB) const override
Public Member Functions inherited from llvm::TargetTransformInfoImplBase
virtual	~TargetTransformInfoImplBase ()
	TargetTransformInfoImplBase (const TargetTransformInfoImplBase &Arg)=default
	TargetTransformInfoImplBase (TargetTransformInfoImplBase &&Arg)
virtual const DataLayout &	getDataLayout () const
virtual unsigned	getInliningCostBenefitAnalysisSavingsMultiplier () const
virtual unsigned	getInliningCostBenefitAnalysisProfitableMultiplier () const
virtual InstructionCost	getMemcpyCost (const Instruction *I) const
virtual BranchProbability	getPredictableBranchThreshold () const
virtual InstructionCost	getBranchMispredictPenalty () const
virtual bool	isLoweredToCall (const Function *F) const
virtual bool	canMacroFuseCmp () const
virtual bool	canSaveCmp (Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
virtual TTI::AddressingModeKind	getPreferredAddressingMode (const Loop *L, ScalarEvolution *SE) const
virtual bool	isLegalMaskedStore (Type *DataType, Align Alignment, unsigned AddressSpace) const
virtual bool	isLegalMaskedLoad (Type *DataType, Align Alignment, unsigned AddressSpace) const
virtual bool	isLegalNTStore (Type *DataType, Align Alignment) const
virtual bool	isLegalNTLoad (Type *DataType, Align Alignment) const
virtual bool	isLegalBroadcastLoad (Type *ElementTy, ElementCount NumElements) const
virtual bool	isLegalMaskedScatter (Type *DataType, Align Alignment) const
virtual bool	isLegalMaskedGather (Type *DataType, Align Alignment) const
virtual bool	forceScalarizeMaskedGather (VectorType *DataType, Align Alignment) const
virtual bool	forceScalarizeMaskedScatter (VectorType *DataType, Align Alignment) const
virtual bool	isLegalMaskedCompressStore (Type *DataType, Align Alignment) const
virtual bool	isLegalAltInstr (VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
virtual bool	isLegalMaskedExpandLoad (Type *DataType, Align Alignment) const
virtual bool	isLegalStridedLoadStore (Type *DataType, Align Alignment) const
virtual bool	isLegalInterleavedAccessType (VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
virtual bool	isLegalMaskedVectorHistogram (Type *AddrType, Type *DataType) const
virtual bool	enableOrderedReductions () const
virtual bool	hasDivRemOp (Type *DataType, bool IsSigned) const
virtual bool	hasVolatileVariant (Instruction *I, unsigned AddrSpace) const
virtual bool	prefersVectorizedAddressing () const
virtual bool	LSRWithInstrQueries () const
virtual bool	shouldBuildLookupTablesForConstant (Constant *C) const
virtual bool	useColdCCForColdCall (Function &F) const
virtual bool	supportsEfficientVectorElementLoadStore () const
virtual bool	supportsTailCalls () const
virtual bool	enableAggressiveInterleaving (bool LoopHasReductions) const
virtual TTI::MemCmpExpansionOptions	enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const
virtual bool	enableSelectOptimize () const
virtual bool	shouldTreatInstructionLikeSelect (const Instruction *I) const
virtual bool	enableInterleavedAccessVectorization () const
virtual bool	enableMaskedInterleavedAccessVectorization () const
virtual bool	isFPVectorizationPotentiallyUnsafe () const
virtual InstructionCost	getIntImmCodeSizeCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
virtual InstructionCost	getIntImmCost (const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
virtual InstructionCost	getIntImmCostInst (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
virtual InstructionCost	getIntImmCostIntrin (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
virtual bool	hasConditionalLoadStoreForType (Type *Ty, bool IsStore) const
virtual unsigned	getRegisterClassForType (bool Vector, Type *Ty=nullptr) const
virtual const char *	getRegisterClassName (unsigned ClassID) const
virtual bool	shouldMaximizeVectorBandwidth (TargetTransformInfo::RegisterKind K) const
virtual ElementCount	getMinimumVF (unsigned ElemWidth, bool IsScalable) const
virtual bool	shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
virtual std::optional< unsigned >	getMinPageSize () const
virtual InstructionCost	getPartialReductionCost (unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, ElementCount VF, TTI::PartialReductionExtendKind OpAExtend, TTI::PartialReductionExtendKind OpBExtend, std::optional< unsigned > BinOp, TTI::TargetCostKind CostKind) const
virtual InstructionCost	getAltInstrCost (VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const
virtual InstructionCost	getInsertExtractValueCost (unsigned Opcode, TTI::TargetCostKind CostKind) const
virtual InstructionCost	getVPMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
virtual InstructionCost	getCostOfKeepingLiveOverCall (ArrayRef< Type * > Tys) const
virtual unsigned	getAtomicMemIntrinsicMaxElementSize () const
virtual Value *	getOrCreateResultFromMemIntrinsic (IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate=true) const
virtual unsigned	getInlineCallPenalty (const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
virtual bool	areTypesABICompatible (const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
virtual bool	isLegalToVectorizeLoad (LoadInst *LI) const
virtual bool	isLegalToVectorizeStore (StoreInst *SI) const
virtual bool	isLegalToVectorizeReduction (const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
virtual bool	isElementTypeLegalForScalableVector (Type *Ty) const
virtual bool	preferFixedOverScalableIfEqualCost (bool IsEpilogue) const
virtual bool	preferInLoopReduction (RecurKind Kind, Type *Ty) const
virtual bool	preferAlternateOpcodeVectorization () const
virtual bool	preferPredicatedReductionSelect () const
virtual bool	preferEpilogueVectorization () const
virtual bool	shouldConsiderVectorizationRegPressure () const
virtual bool	shouldExpandReduction (const IntrinsicInst *II) const
virtual TTI::ReductionShuffle	getPreferredExpandedReductionShuffle (const IntrinsicInst *II) const
virtual unsigned	getGISelRematGlobalCost () const
virtual unsigned	getMinTripCountTailFoldingThreshold () const
virtual bool	supportsScalableVectors () const
virtual bool	enableScalableVectorization () const
virtual bool	hasActiveVectorLength () const
virtual bool	isVectorShiftByScalarCheap (Type *Ty) const
virtual TargetTransformInfo::VPLegalization	getVPLegalizationStrategy (const VPIntrinsic &PI) const
virtual bool	hasArmWideBranch (bool) const
virtual APInt	getFeatureMask (const Function &F) const
virtual bool	isMultiversionedFunction (const Function &F) const
virtual unsigned	getMaxNumArgs () const
virtual unsigned	getNumBytesToPadGlobalArray (unsigned Size, Type *ArrayType) const
virtual bool	allowVectorElementIndexingUsingGEP () const

Additional Inherited Members
Protected Types inherited from llvm::TargetTransformInfoImplBase
typedef TargetTransformInfo	TTI
Protected Member Functions inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
	BasicTTIImplBase (const TargetMachine *TM, const DataLayout &DL)
virtual	~BasicTTIImplBase ()=default
Protected Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< T >
	TargetTransformInfoImplCRTPBase (const DataLayout &DL)
Protected Member Functions inherited from llvm::TargetTransformInfoImplBase
	TargetTransformInfoImplBase (const DataLayout &DL)
unsigned	minRequiredElementSize (const Value *Val, bool &isSigned) const
bool	isStridedAccess (const SCEV *Ptr) const
const SCEVConstant *	getConstantStrideStep (ScalarEvolution *SE, const SCEV *Ptr) const
bool	isConstantStridedAccessLessThan (ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
Protected Attributes inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
const DataLayout &	DL
Protected Attributes inherited from llvm::TargetTransformInfoImplBase
const DataLayout &	DL

Detailed Description

Definition at line 63 of file AMDGPUTargetTransformInfo.h.

Member Enumeration Documentation

KnownIEEEMode

enum class llvm::GCNTTIImpl::KnownIEEEMode

strong

Enumerator
Unknown
On
Off

Definition at line 285 of file AMDGPUTargetTransformInfo.h.

Constructor & Destructor Documentation

GCNTTIImpl()

GCNTTIImpl::GCNTTIImpl ( const AMDGPUTargetMachine * TM, const Function & F )

explicit

Definition at line 305 of file AMDGPUTargetTransformInfo.cpp.

References const, F, llvm::TargetTransformInfoImplBase::getDataLayout(), llvm::DenormalMode::getPreserveSign(), and Mode.

Member Function Documentation

addrspacesMayAlias()

bool llvm::GCNTTIImpl::addrspacesMayAlias ( unsigned AS0, unsigned AS1 ) const

inlineoverridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 189 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPU::addrspacesMayAlias().

adjustInliningThreshold()

unsigned GCNTTIImpl::adjustInliningThreshold ( const CallBase * CB ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1422 of file AMDGPUTargetTransformInfo.cpp.

References adjustInliningThresholdUsingCallee(), ArgAllocaCost, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, and getCallArgsTotalAllocaSize().

areInlineCompatible()

bool GCNTTIImpl::areInlineCompatible ( const Function * Caller, const Function * Callee ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1305 of file AMDGPUTargetTransformInfo.cpp.

References InlineMaxBB, and llvm::SIModeRegisterDefaults::isInlineCompatible().

canHaveNonUndefGlobalInitializerInAddressSpace()

bool llvm::GCNTTIImpl::canHaveNonUndefGlobalInitializerInAddressSpace ( unsigned AS ) const

inlineoverridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 205 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPUAS::LOCAL_ADDRESS, llvm::AMDGPUAS::PRIVATE_ADDRESS, and llvm::AMDGPUAS::REGION_ADDRESS.

canSimplifyLegacyMulToMul()

bool GCNTTIImpl::canSimplifyLegacyMulToMul	(	const Instruction &	I,
		const Value *	Op0,
		const Value *	Op1,
		InstCombiner &	IC ) const

Definition at line 391 of file AMDGPUInstCombineIntrinsic.cpp.

References llvm::InstCombiner::getSimplifyQuery(), llvm::SimplifyQuery::getWithInstruction(), I, llvm::isKnownNeverInfOrNaN(), llvm::PatternMatch::m_FiniteNonZero(), and llvm::PatternMatch::match().

Referenced by instCombineIntrinsic().

collectFlatAddressOperands()

bool GCNTTIImpl::collectFlatAddressOperands ( SmallVectorImpl< int > & OpIndexes, Intrinsic::ID IID ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1118 of file AMDGPUTargetTransformInfo.cpp.

References llvm::SmallVectorTemplateBase< T, bool >::push_back().

collectKernelLaunchBounds()

void GCNTTIImpl::collectKernelLaunchBounds ( const Function & F, SmallVectorImpl< std::pair< StringRef, int64_t > > & LB ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 1514 of file AMDGPUTargetTransformInfo.cpp.

References F, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

fpenvIEEEMode()

GCNTTIImpl::KnownIEEEMode GCNTTIImpl::fpenvIEEEMode

(

const Instruction &

I

)

const

Return KnownIEEEMode::On if we know if the use context can assume "amdgpu-ieee"="true" and KnownIEEEMode::Off if we can assume "amdgpu-ieee"="false".

Definition at line 1531 of file AMDGPUTargetTransformInfo.cpp.

References F, llvm::Attribute::getValueAsBool(), I, llvm::AMDGPU::isShader(), llvm::Attribute::isValid(), Off, On, and Unknown.

Referenced by getIntrinsicInstrCost(), and instCombineIntrinsic().

getArithmeticInstrCost()

InstructionCost GCNTTIImpl::getArithmeticInstrCost ( unsigned Opcode, Type * Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args = {}, const Instruction * CxtI = nullptr ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 530 of file AMDGPUTargetTransformInfo.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, CostKind, llvm::dyn_cast(), llvm::ISD::FADD, llvm::FAdd, llvm::FPOpFusion::Fast, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::BasicTTIImplBase< GCNTTIImpl >::getArithmeticInstrCost(), llvm::Instruction::hasAllowContract(), llvm::Instruction::hasApproxFunc(), llvm::Value::hasOneUse(), llvm::PatternMatch::m_FPOne(), llvm::PatternMatch::match(), llvm::ISD::MUL, Options, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::TargetTransformInfo::TCC_Free, llvm::Value::user_begin(), and llvm::ISD::XOR.

getArithmeticReductionCost()

InstructionCost GCNTTIImpl::getArithmeticReductionCost ( unsigned Opcode, VectorType * Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 850 of file AMDGPUTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::BasicTTIImplBase< GCNTTIImpl >::getArithmeticReductionCost(), llvm::EVT::getScalarSizeInBits(), and llvm::TargetTransformInfo::requiresOrderedReduction().

getCacheLineSize()

unsigned llvm::GCNTTIImpl::getCacheLineSize ( ) const

inlineoverridevirtual

Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 273 of file AMDGPUTargetTransformInfo.h.

getCallerAllocaCost()

unsigned GCNTTIImpl::getCallerAllocaCost ( const CallBase * CB, const AllocaInst * AI ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1433 of file AMDGPUTargetTransformInfo.cpp.

References ArgAllocaCost, ArgAllocaCutoff, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::AllocaInst::getAllocatedType(), getCallArgsTotalAllocaSize(), llvm::CallBase::getCalledFunction(), getInliningThresholdMultiplier(), and llvm::none_of().

getCFInstrCost()

InstructionCost GCNTTIImpl::getCFInstrCost ( unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction * I = nullptr ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 819 of file AMDGPUTargetTransformInfo.cpp.

References assert(), CostKind, llvm::dyn_cast_or_null(), llvm::BasicTTIImplBase< GCNTTIImpl >::getCFInstrCost(), I, llvm::TargetTransformInfo::TCK_CodeSize, and llvm::TargetTransformInfo::TCK_SizeAndLatency.

getFlatAddressSpace()

unsigned llvm::GCNTTIImpl::getFlatAddressSpace ( ) const

inlineoverridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 193 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPUAS::FLAT_ADDRESS.

getInlinerVectorBonusPercent()

int llvm::GCNTTIImpl::getInlinerVectorBonusPercent ( ) const

inlineoverridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 256 of file AMDGPUTargetTransformInfo.h.

getInliningLastCallToStaticBonus()

int GCNTTIImpl::getInliningLastCallToStaticBonus ( ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 1417 of file AMDGPUTargetTransformInfo.cpp.

References llvm::TargetTransformInfoImplBase::getInliningLastCallToStaticBonus(), and getInliningThresholdMultiplier().

getInliningThresholdMultiplier()

unsigned llvm::GCNTTIImpl::getInliningThresholdMultiplier ( ) const

inlineoverridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 251 of file AMDGPUTargetTransformInfo.h.

Referenced by getCallerAllocaCost(), and getInliningLastCallToStaticBonus().

getIntrinsicInstrCost()

InstructionCost GCNTTIImpl::getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA, TTI::TargetCostKind CostKind ) const

overridevirtual

Get intrinsic cost based on arguments.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 710 of file AMDGPUTargetTransformInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::any_of(), CostKind, fpenvIEEEMode(), llvm::IntrinsicCostAttributes::getID(), llvm::IntrinsicCostAttributes::getInst(), llvm::BasicTTIImplBase< GCNTTIImpl >::getIntrinsicInstrCost(), llvm::IntrinsicCostAttributes::getReturnType(), II, intrinsicHasPackedVectorBenefit(), and Off.

getLoadStoreVecRegBitWidth()

unsigned GCNTTIImpl::getLoadStoreVecRegBitWidth ( unsigned AddrSpace ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 380 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPUAS::BUFFER_FAT_POINTER, llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::AMDGPUAS::BUFFER_STRIDED_POINTER, llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

Referenced by getMemoryOpCost().

getLoadVectorFactor()

unsigned GCNTTIImpl::getLoadVectorFactor ( unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType * VecTy ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 359 of file AMDGPUTargetTransformInfo.cpp.

References llvm::Type::getScalarSizeInBits().

getMaximumVF()

unsigned GCNTTIImpl::getMaximumVF ( unsigned ElemWidth, unsigned Opcode ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 348 of file AMDGPUTargetTransformInfo.cpp.

getMaxInterleaveFactor()

unsigned GCNTTIImpl::getMaxInterleaveFactor ( ElementCount VF ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 495 of file AMDGPUTargetTransformInfo.cpp.

References llvm::ElementCount::isScalar().

getMaxMemIntrinsicInlineSizeThreshold()

uint64_t GCNTTIImpl::getMaxMemIntrinsicInlineSizeThreshold ( ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 422 of file AMDGPUTargetTransformInfo.cpp.

getMemcpyLoopLoweringType()

Type * GCNTTIImpl::getMemcpyLoopLoweringType ( LLVMContext & Context, Value * Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 426 of file AMDGPUTargetTransformInfo.cpp.

References llvm::FixedVectorType::get(), llvm::Type::getInt32Ty(), llvm::Type::getIntNTy(), llvm::isa(), llvm::Length, and MemcpyLoopUnroll.

getMemcpyLoopResidualLoweringType()

void GCNTTIImpl::getMemcpyLoopResidualLoweringType ( SmallVectorImpl< Type * > & OpsOut, LLVMContext & Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 453 of file AMDGPUTargetTransformInfo.cpp.

References llvm::FixedVectorType::get(), llvm::Type::getInt16Ty(), llvm::Type::getInt32Ty(), llvm::Type::getInt64Ty(), llvm::Type::getInt8Ty(), llvm::TargetTransformInfoImplBase::getMemcpyLoopResidualLoweringType(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

getMemoryOpCost()

InstructionCost GCNTTIImpl::getMemoryOpCost ( unsigned Opcode, Type * Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, const Instruction * I = nullptr ) const

overridevirtual

Account for loads of i8 vector types to have reduced cost.

For example the cost of load 4 i8s values is one is the cost of loading a single i32 value.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1547 of file AMDGPUTargetTransformInfo.cpp.

References CostKind, llvm::divideCeil(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::dyn_cast(), getLoadStoreVecRegBitWidth(), llvm::BasicTTIImplBase< GCNTTIImpl >::getMemoryOpCost(), and I.

getMinMaxReductionCost()

InstructionCost GCNTTIImpl::getMinMaxReductionCost ( Intrinsic::ID IID, VectorType * Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind ) const

overridevirtual

Try to calculate op costs for min/max reduction operations.

Parameters

CondTy

Conditional type for the Select instruction.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 868 of file AMDGPUTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::BasicTTIImplBase< GCNTTIImpl >::getMinMaxReductionCost(), and llvm::EVT::getScalarSizeInBits().

getMinVectorRegisterBitWidth()

unsigned GCNTTIImpl::getMinVectorRegisterBitWidth ( ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 344 of file AMDGPUTargetTransformInfo.cpp.

getNumberOfParts()

unsigned GCNTTIImpl::getNumberOfParts ( Type * Tp ) const

overridevirtual

When counting parts on AMD GPUs, account for i8s being grouped together under a single i32 value.

Otherwise fall back to base implementation.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1564 of file AMDGPUTargetTransformInfo.cpp.

References llvm::divideCeil(), llvm::dyn_cast(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), and llvm::BasicTTIImplBase< GCNTTIImpl >::getNumberOfParts().

getNumberOfRegisters()

unsigned GCNTTIImpl::getNumberOfRegisters ( unsigned RCID ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 320 of file AMDGPUTargetTransformInfo.cpp.

getPeelingPreferences()

void GCNTTIImpl::getPeelingPreferences ( Loop * L, ScalarEvolution & SE, TTI::PeelingPreferences & PP ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1480 of file AMDGPUTargetTransformInfo.cpp.

getPopcntSupport()

TTI::PopcntSupportKind llvm::GCNTTIImpl::getPopcntSupport ( unsigned TyWidth ) const

inlineoverridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 116 of file AMDGPUTargetTransformInfo.h.

References assert(), llvm::isPowerOf2_32(), and llvm::TargetTransformInfo::PSK_FastHardware.

getPrefetchDistance()

unsigned GCNTTIImpl::getPrefetchDistance ( ) const

overridevirtual

How much before a load we should place the prefetch instruction.

This is currently measured in number of IR instructions.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1506 of file AMDGPUTargetTransformInfo.cpp.

getRegisterBitWidth()

TypeSize GCNTTIImpl::getRegisterBitWidth ( TargetTransformInfo::RegisterKind Vector ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 332 of file AMDGPUTargetTransformInfo.cpp.

References llvm::TypeSize::getFixed(), llvm::TypeSize::getScalable(), llvm_unreachable, llvm::TargetTransformInfo::RGK_FixedWidthVector, llvm::TargetTransformInfo::RGK_ScalableVector, and llvm::TargetTransformInfo::RGK_Scalar.

getShuffleCost()

InstructionCost GCNTTIImpl::getShuffleCost ( TTI::ShuffleKind Kind, VectorType * DstTy, VectorType * SrcTy, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType * SubTp, ArrayRef< const Value * > Args = {}, const Instruction * CxtI = nullptr ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1222 of file AMDGPUTargetTransformInfo.cpp.

References llvm::alignTo(), llvm::cast(), CostKind, llvm::count_if(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::BasicTTIImplBase< GCNTTIImpl >::getShuffleCost(), llvm::BasicTTIImplBase< GCNTTIImpl >::improveShuffleKindFromMask(), llvm::isa(), llvm::TargetTransformInfo::SK_Broadcast, llvm::TargetTransformInfo::SK_ExtractSubvector, llvm::TargetTransformInfo::SK_InsertSubvector, llvm::TargetTransformInfo::SK_PermuteSingleSrc, llvm::TargetTransformInfo::SK_PermuteTwoSrc, llvm::TargetTransformInfo::SK_Reverse, llvm::TargetTransformInfo::SK_Select, llvm::TargetTransformInfo::SK_Splice, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

getStoreVectorFactor()

unsigned GCNTTIImpl::getStoreVectorFactor ( unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType * VecTy ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 370 of file AMDGPUTargetTransformInfo.cpp.

getTgtMemIntrinsic()

bool GCNTTIImpl::getTgtMemIntrinsic ( IntrinsicInst * Inst, MemIntrinsicInfo & Info ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 504 of file AMDGPUTargetTransformInfo.cpp.

References llvm::dyn_cast(), llvm::CallBase::getArgOperand(), llvm::IntrinsicInst::getIntrinsicID(), and llvm::SequentiallyConsistent.

getUnrollingPreferences()

void GCNTTIImpl::getUnrollingPreferences ( Loop * L, ScalarEvolution & SE, TTI::UnrollingPreferences & UP, OptimizationRemarkEmitter * ORE ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1474 of file AMDGPUTargetTransformInfo.cpp.

getVectorInstrCost() [1/3]

InstructionCost llvm::BasicTTIImplBase< GCNTTIImpl >::getVectorInstrCost ( const Instruction & I, Type * Val, TTI::TargetCostKind CostKind, unsigned Index ) const

inlineoverridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1443 of file BasicTTIImpl.h.

getVectorInstrCost() [2/3]

InstructionCost llvm::BasicTTIImplBase< GCNTTIImpl >::getVectorInstrCost ( unsigned Opcode, Type * Val, TTI::TargetCostKind CostKind, unsigned Index, Value * Scalar, ArrayRef< std::tuple< Value *, User *, int > > ScalarUserAndIdx ) const

inlineoverridevirtual

Parameters

ScalarUserAndIdx

encodes the information about extracts from a vector with 'Scalar' being the value being extracted,'User' being the user of the extract(nullptr if user is not known before vectorization) and 'Idx' being the extract lane.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1434 of file BasicTTIImpl.h.

getVectorInstrCost() [3/3]

InstructionCost GCNTTIImpl::getVectorInstrCost ( unsigned Opcode, Type * ValTy, TTI::TargetCostKind CostKind, unsigned Index, const Value * Op0, const Value * Op1 ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 882 of file AMDGPUTargetTransformInfo.cpp.

References llvm::cast(), CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, and llvm::BasicTTIImplBase< GCNTTIImpl >::getVectorInstrCost().

getVectorSplitCost()

InstructionCost llvm::GCNTTIImpl::getVectorSplitCost ( ) const

inline

Definition at line 236 of file AMDGPUTargetTransformInfo.h.

hasBranchDivergence()

bool GCNTTIImpl::hasBranchDivergence ( const Function * F = nullptr ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 316 of file AMDGPUTargetTransformInfo.cpp.

References F.

hoistLaneIntrinsicThroughOperand()

Instruction * GCNTTIImpl::hoistLaneIntrinsicThroughOperand	(	InstCombiner &	IC,
		IntrinsicInst &	II ) const

Definition at line 557 of file AMDGPUInstCombineIntrinsic.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::InstCombiner::Builder, llvm::Instruction::clone(), llvm::DominatorTree::dominates(), llvm::dyn_cast(), llvm::InstCombiner::getDominatorTree(), llvm::User::getOperand(), llvm::User::getOperandUse(), llvm::Intrinsic::getOrInsertDeclaration(), llvm::ilist_detail::node_parent_access< NodeTy, ParentTy >::getParent(), llvm::Value::hasOneUser(), II, llvm::isa(), isTriviallyUniform(), llvm::BasicTTIImplBase< GCNTTIImpl >::isTypeLegal(), OpIdx, rewriteCall(), and llvm::User::setOperand().

Referenced by instCombineIntrinsic().

instCombineIntrinsic()

std::optional< Instruction * > GCNTTIImpl::instCombineIntrinsic ( InstCombiner & IC, IntrinsicInst & II ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 639 of file AMDGPUInstCombineIntrinsic.cpp.

References llvm::CallBase::addFnAttr(), llvm::FastMathFlags::allowContract(), assert(), llvm::APFloat::bitcastToAPInt(), llvm::InstCombiner::Builder, llvm::CallingConv::C, Call, canContractSqrtToRsq(), canSimplifyLegacyMulToMul(), llvm::cast(), Changed, llvm::ConstantFoldCompareInstOperands(), llvm::APFloat::convert(), llvm::IRBuilderBase::CreateAShr(), llvm::IRBuilderBase::CreateExtractVector(), llvm::IRBuilderBase::CreateFAddFMF(), llvm::IRBuilderBase::CreateFMulFMF(), llvm::IRBuilderBase::CreateICmpNE(), llvm::IRBuilderBase::CreateInsertElement(), llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateLShr(), llvm::IRBuilderBase::CreateMaximumNum(), llvm::IRBuilderBase::CreateMaxNum(), llvm::IRBuilderBase::CreateMinimumNum(), llvm::IRBuilderBase::CreateMinNum(), llvm::IRBuilderBase::CreateSExt(), llvm::IRBuilderBase::CreateShl(), llvm::IRBuilderBase::CreateZExt(), defaultComponentBroadcast(), llvm::APFloat::divide(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::dyn_cast(), llvm::InstCombiner::eraseInstFromFunction(), llvm::Exponent, llvm::FAdd, llvm::fcAllFlags, llvm::CmpInst::FIRST_FCMP_PREDICATE, llvm::CmpInst::FIRST_ICMP_PREDICATE, fmed3AMDGCN(), llvm::FMul, llvm::AMDGPU::MFMAScaleFormats::FP4_E2M1, llvm::AMDGPU::MFMAScaleFormats::FP6_E2M3, llvm::AMDGPU::MFMAScaleFormats::FP6_E3M2, llvm::AMDGPU::MFMAScaleFormats::FP8_E4M3, llvm::AMDGPU::MFMAScaleFormats::FP8_E5M2, fpenvIEEEMode(), llvm::frexp(), llvm::FixedVectorType::get(), llvm::MDNode::get(), llvm::MDString::get(), llvm::MetadataAsValue::get(), llvm::PoisonValue::get(), llvm::UndefValue::get(), llvm::ConstantInt::getFalse(), llvm::FPMathOperator::getFastMathFlags(), llvm::Type::getHalfTy(), llvm::AMDGPU::getImageDimIntrinsicInfo(), llvm::ConstantFP::getInfinity(), llvm::IRBuilderBase::getInt64(), llvm::IRBuilderBase::getIntNTy(), llvm::CmpInst::getInversePredicate(), llvm::ConstantFP::getNaN(), llvm::Constant::getNullValue(), llvm::Intrinsic::getOrInsertDeclaration(), llvm::APFloat::getQNaN(), llvm::APFloat::getSemantics(), llvm::InstCombiner::getSimplifyQuery(), llvm::CmpInst::getSwappedPredicate(), llvm::Value::getType(), llvm::ConstantInt::getValue(), llvm::ConstantFP::getValueAPF(), llvm::APFloat::getZero(), llvm::ConstantFP::getZero(), llvm::APInt::getZExtValue(), llvm::ConstantInt::getZExtValue(), hoistLaneIntrinsicThroughOperand(), I, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEK_Inf, llvm::APFloatBase::IEK_NaN, II, llvm::isa(), llvm::CmpInst::isFPPredicate(), llvm::APFloat::isInfinity(), llvm::Type::isIntegerTy(), llvm::APFloat::isNaN(), llvm::APFloat::isNegInfinity(), llvm::Constant::isNullValue(), llvm::APFloat::isPosInfinity(), llvm::APFloat::isSignaling(), llvm::CmpInst::isSigned(), isTriviallyUniform(), llvm::SimplifyQuery::isUndefValue(), llvm::CmpInst::LAST_FCMP_PREDICATE, llvm::CmpInst::LAST_ICMP_PREDICATE, llvm_unreachable, llvm::PatternMatch::m_AllOnes(), llvm::PatternMatch::m_AnyZeroFP(), llvm::PatternMatch::m_APFloat(), llvm::PatternMatch::m_Cmp(), llvm::PatternMatch::m_ConstantFP(), llvm::PatternMatch::m_FPExt(), llvm::PatternMatch::m_One(), llvm::PatternMatch::m_SExt(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::PatternMatch::m_ZExt(), llvm::PatternMatch::m_ZExtOrSExt(), llvm::Make_64(), llvm::APFloat::makeQuiet(), llvm::PatternMatch::match(), matchFPExtFromF16(), llvm::NearestTiesToEven, Off, llvm::Offset, On, llvm::InstCombiner::replaceInstUsesWith(), llvm::InstCombiner::replaceOperand(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardZero, llvm::scalbn(), llvm::Signed, simplifyAMDGCNImageIntrinsic(), simplifyAMDGCNMemoryIntrinsicDemanded(), simplifyDemandedLaneMaskArg(), std::swap(), llvm::Value::takeName(), trimTrailingZerosInVector(), llvm::APInt::trunc(), Unknown, llvm::AMDGPU::wmmaScaleF8F6F4FormatToNumRegs(), X, and Y.

isAlwaysUniform()

bool GCNTTIImpl::isAlwaysUniform ( const Value * V ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1044 of file AMDGPUTargetTransformInfo.cpp.

References llvm::CallingConv::C, llvm::computeKnownBits(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::dyn_cast(), F, llvm::ExtractValueInst::getIndices(), llvm::User::getOperand(), I, llvm::CallBase::isInlineAsm(), isInlineAsmSourceOfDivergence(), llvm::AMDGPU::isIntrinsicAlwaysUniform(), llvm::PatternMatch::m_AShr(), llvm::PatternMatch::m_c_And(), llvm::PatternMatch::m_ConstantInt(), llvm::PatternMatch::m_Intrinsic(), llvm::PatternMatch::m_LShr(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::match(), and llvm::ArrayRef< T >::size().

isInlineAsmSourceOfDivergence()

bool GCNTTIImpl::isInlineAsmSourceOfDivergence	(	const CallInst *	CI,
		ArrayRef< unsigned >	Indices = {} ) const

Analyze if the results of inline asm are divergent.

If Indices is empty, this is analyzing the collective result of all output registers. Otherwise, this is only querying a specific result index if this returns multiple registers in a struct.

Definition at line 914 of file AMDGPUTargetTransformInfo.cpp.

References llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::ArrayRef< T >::empty(), llvm::Instruction::getDataLayout(), llvm::InlineAsm::isOutput, SDValue(), llvm::ArrayRef< T >::size(), and TRI.

Referenced by isAlwaysUniform(), and isSourceOfDivergence().

isLegalToVectorizeLoadChain()

bool GCNTTIImpl::isLegalToVectorizeLoadChain ( unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 410 of file AMDGPUTargetTransformInfo.cpp.

References isLegalToVectorizeMemChain().

isLegalToVectorizeMemChain()

bool GCNTTIImpl::isLegalToVectorizeMemChain	(	unsigned	ChainSizeInBytes,
		Align	Alignment,
		unsigned	AddrSpace ) const

Definition at line 397 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPUAS::PRIVATE_ADDRESS.

Referenced by isLegalToVectorizeLoadChain(), and isLegalToVectorizeStoreChain().

isLegalToVectorizeStoreChain()

bool GCNTTIImpl::isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace ) const

overridevirtual

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 416 of file AMDGPUTargetTransformInfo.cpp.

References isLegalToVectorizeMemChain().

isProfitableToSinkOperands()

bool GCNTTIImpl::isProfitableToSinkOperands ( Instruction * I, SmallVectorImpl< Use * > & Ops ) const

overridevirtual

Whether it is profitable to sink the operands of an Instruction I to the basic block of I.

This helps using several modifiers (like abs and neg) more often.

Reimplemented from llvm::TargetTransformInfoImplBase.

Definition at line 1289 of file AMDGPUTargetTransformInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::any_of(), I, llvm::PatternMatch::m_FAbs(), llvm::PatternMatch::m_FNeg(), llvm::PatternMatch::m_Value(), and llvm::PatternMatch::match().

isReadRegisterSourceOfDivergence()

bool GCNTTIImpl::isReadRegisterSourceOfDivergence

(

const IntrinsicInst *

ReadReg

)

const

Definition at line 950 of file AMDGPUTargetTransformInfo.cpp.

References llvm::cast(), llvm::CallBase::getArgOperand(), llvm::Value::getType(), llvm::MVT::getVT(), and RegName.

Referenced by isSourceOfDivergence().

isSourceOfDivergence()

bool GCNTTIImpl::isSourceOfDivergence ( const Value * V ) const

overridevirtual

Returns

true if the result of the value could potentially be different across workitems in a wavefront.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 973 of file AMDGPUTargetTransformInfo.cpp.

References A(), llvm::dyn_cast(), F, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::isa(), llvm::AMDGPU::isArgPassedInSGPR(), isInlineAsmSourceOfDivergence(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), isReadRegisterSourceOfDivergence(), and llvm::AMDGPUAS::PRIVATE_ADDRESS.

isValidAddrSpaceCast()

bool llvm::GCNTTIImpl::isValidAddrSpaceCast ( unsigned FromAS, unsigned ToAS ) const

inlineoverridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 180 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPU::addrspacesMayAlias().

rewriteIntrinsicWithAddressSpace()

Value * GCNTTIImpl::rewriteIntrinsicWithAddressSpace ( IntrinsicInst * II, Value * OldV, Value * NewV ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1134 of file AMDGPUTargetTransformInfo.cpp.

References B(), llvm::computeKnownBits(), llvm::KnownBits::countMinLeadingOnes(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::Type::getContext(), llvm::ConstantInt::getFalse(), llvm::Intrinsic::getOrInsertDeclaration(), llvm::Type::getPointerAddressSpace(), llvm::ConstantInt::getTrue(), llvm::Value::getType(), II, llvm::AMDGPU::isExtendedGlobalAddrSpace(), llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

shouldPrefetchAddressSpace()

bool GCNTTIImpl::shouldPrefetchAddressSpace ( unsigned AS ) const

overridevirtual

Returns

if target want to issue a prefetch in address space AS.

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1510 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPU::isFlatGlobalAddrSpace().

simplifyAMDGCNLaneIntrinsicDemanded()

Value * GCNTTIImpl::simplifyAMDGCNLaneIntrinsicDemanded	(	InstCombiner &	IC,
		IntrinsicInst &	II,
		const APInt &	DemandedElts,
		APInt &	UndefElts ) const

Definition at line 1912 of file AMDGPUInstCombineIntrinsic.cpp.

References llvm::InstCombiner::Builder, llvm::APInt::countr_zero(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateExtractElement(), llvm::IRBuilderBase::CreateInsertElement(), llvm::IRBuilderBase::CreateShuffleVector(), llvm::dyn_cast(), llvm::FixedVectorType::get(), llvm::PoisonValue::get(), llvm::APInt::getActiveBits(), llvm::IRBuilderBase::GetInsertBlock(), llvm::BasicBlock::getModule(), llvm::Intrinsic::getOrInsertDeclaration(), I, II, and llvm::BasicTTIImplBase< GCNTTIImpl >::isTypeLegal().

Referenced by simplifyDemandedVectorEltsIntrinsic().

simplifyDemandedLaneMaskArg()

bool GCNTTIImpl::simplifyDemandedLaneMaskArg	(	InstCombiner &	IC,
		IntrinsicInst &	II,
		unsigned	LaneArgIdx ) const

Simplify a lane index operand (e.g.

llvm.amdgcn.readlane src1).

The instruction only reads the low 5 bits for wave32, and 6 bits for wave64.

Definition at line 518 of file AMDGPUInstCombineIntrinsic.cpp.

References llvm::KnownBits::getConstant(), llvm::Value::getType(), II, llvm::KnownBits::isConstant(), llvm::maskTrailingOnes(), and llvm::InstCombiner::SimplifyDemandedBits().

Referenced by instCombineIntrinsic().

simplifyDemandedVectorEltsIntrinsic()

std::optional< Value * > GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic ( InstCombiner & IC, IntrinsicInst & II, APInt DemandedElts, APInt & UndefElts, APInt & UndefElts2, APInt & UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp ) const

overridevirtual

Reimplemented from llvm::BasicTTIImplBase< GCNTTIImpl >.

Definition at line 1978 of file AMDGPUInstCombineIntrinsic.cpp.

References II, simplifyAMDGCNLaneIntrinsicDemanded(), and simplifyAMDGCNMemoryIntrinsicDemanded().

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The documentation for this class was generated from the following files:

• lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
• lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
• lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp