Classes
struct	CPUInfo
struct	CPUModel
struct	NDSVLNPseudo
struct	RISCVMaskedPseudoInfo
struct	VLEPseudo
struct	VLSEGPseudo
struct	VLX_VSXPseudo
struct	VLXSEGPseudo
struct	VSEPseudo
struct	VSSEGPseudo
struct	VSXSEGPseudo
struct	VXMemOpInfo

Typedefs
using	Specifier = uint16_t

Enumerations
enum	PartialMappingIdx { PMI_GPRB32 = 0 , PMI_GPRB64 = 1 , PMI_FPRB16 = 2 , PMI_FPRB32 = 3 , PMI_FPRB64 = 4 , PMI_VRB64 = 5 , PMI_VRB128 = 6 , PMI_VRB256 = 7 , PMI_VRB512 = 8 }
enum	ValueMappingIdx { InvalidIdx = 0 , GPRB32Idx = 1 , GPRB64Idx = 4 , FPRB16Idx = 7 , FPRB32Idx = 10 , FPRB64Idx = 13 , VRB64Idx = 16 , VRB128Idx = 19 , VRB256Idx = 22 , VRB512Idx = 25 }
enum	Fixups { fixup_riscv_hi20 = FirstTargetFixupKind , fixup_riscv_lo12_i , fixup_riscv_12_i , fixup_riscv_lo12_s , fixup_riscv_pcrel_hi20 , fixup_riscv_pcrel_lo12_i , fixup_riscv_pcrel_lo12_s , fixup_riscv_jal , fixup_riscv_branch , fixup_riscv_rvc_jump , fixup_riscv_rvc_branch , fixup_riscv_rvc_imm , fixup_riscv_call , fixup_riscv_call_plt , fixup_riscv_qc_e_branch , fixup_riscv_qc_e_32 , fixup_riscv_qc_abs20_u , fixup_riscv_qc_e_call_plt , fixup_riscv_nds_branch_10 , fixup_riscv_invalid , NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind }
enum	{ S_None , S_LO = FirstTargetFixupKind , S_PCREL_LO , S_TPREL_LO , S_QC_ABS20 }
enum	CPUKind : unsigned

Functions
LLVM_ABI void	getFeaturesForCPU (StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
LLVM_ABI bool	parseCPU (StringRef CPU, bool IsRV64)
LLVM_ABI bool	parseTuneCPU (StringRef CPU, bool IsRV64)
LLVM_ABI StringRef	getMArchFromMcpu (StringRef CPU)
LLVM_ABI void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
LLVM_ABI void	fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
LLVM_ABI bool	hasFastScalarUnalignedAccess (StringRef CPU)
LLVM_ABI bool	hasFastVectorUnalignedAccess (StringRef CPU)
LLVM_ABI bool	hasValidCPUModel (StringRef CPU)
LLVM_ABI CPUModel	getCPUModel (StringRef CPU)
LLVM_ABI StringRef	getCPUNameFromCPUModel (const CPUModel &Model)
Specifier	parseSpecifierName (StringRef name)
StringRef	getSpecifierName (Specifier Kind)
ArrayRef< MCPhysReg >	getArgGPRs (const RISCVABI::ABI ABI)
bool	isRVVSpill (const MachineInstr &MI)
std::optional< std::pair< unsigned, unsigned > >	isRVVSpillForZvlsseg (unsigned Opcode)
bool	hasEqualFRM (const MachineInstr &MI1, const MachineInstr &MI2)
std::optional< unsigned >	getVectorLowDemandedScalarBits (unsigned Opcode, unsigned Log2SEW)
unsigned	getRVVMCOpcode (unsigned RVVPseudoOpcode)
unsigned	getDestLog2EEW (const MCInstrDesc &Desc, unsigned Log2SEW)
bool	isVLKnownLE (const MachineOperand &LHS, const MachineOperand &RHS)
	Given two VL operands, do we know that LHS <= RHS?
static const CPUInfo *	getCPUInfoByName (StringRef CPU)

Variables
static constexpr unsigned	RVVBitsPerBlock = 64
static constexpr unsigned	RVVBytesPerBlock = RVVBitsPerBlock / 8
const RegisterBankInfo::PartialMapping	PartMappings []
const RegisterBankInfo::ValueMapping	ValueMappings []
static constexpr int64_t	VLMaxSentinel = -1LL
static constexpr unsigned	FPMASK_Negative_Infinity = 0x001
static constexpr unsigned	FPMASK_Negative_Normal = 0x002
static constexpr unsigned	FPMASK_Negative_Subnormal = 0x004
static constexpr unsigned	FPMASK_Negative_Zero = 0x008
static constexpr unsigned	FPMASK_Positive_Zero = 0x010
static constexpr unsigned	FPMASK_Positive_Subnormal = 0x020
static constexpr unsigned	FPMASK_Positive_Normal = 0x040
static constexpr unsigned	FPMASK_Positive_Infinity = 0x080
static constexpr unsigned	FPMASK_Signaling_NaN = 0x100
static constexpr unsigned	FPMASK_Quiet_NaN = 0x200
constexpr CPUInfo	RISCVCPUInfo []

Typedef Documentation

◆ Specifier

using llvm::RISCV::Specifier = uint16_t

Definition at line 35 of file RISCVMCAsmInfo.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
S_None
S_LO
S_PCREL_LO
S_TPREL_LO
S_QC_ABS20

Definition at line 38 of file RISCVMCAsmInfo.h.

◆ CPUKind

enum llvm::RISCV::CPUKind : unsigned

Definition at line 22 of file RISCVTargetParser.cpp.

◆ Fixups

enum llvm::RISCV::Fixups

Enumerator
fixup_riscv_hi20
fixup_riscv_lo12_i
fixup_riscv_12_i
fixup_riscv_lo12_s
fixup_riscv_pcrel_hi20
fixup_riscv_pcrel_lo12_i
fixup_riscv_pcrel_lo12_s
fixup_riscv_jal
fixup_riscv_branch
fixup_riscv_rvc_jump
fixup_riscv_rvc_branch
fixup_riscv_rvc_imm
fixup_riscv_call
fixup_riscv_call_plt
fixup_riscv_qc_e_branch
fixup_riscv_qc_e_32
fixup_riscv_qc_abs20_u
fixup_riscv_qc_e_call_plt
fixup_riscv_nds_branch_10
fixup_riscv_invalid
NumTargetFixupKinds

Definition at line 19 of file RISCVFixupKinds.h.

◆ PartialMappingIdx

enum llvm::RISCV::PartialMappingIdx

Enumerator
PMI_GPRB32
PMI_GPRB64
PMI_FPRB16
PMI_FPRB32
PMI_FPRB64
PMI_VRB64
PMI_VRB128
PMI_VRB256
PMI_VRB512

Definition at line 42 of file RISCVRegisterBankInfo.cpp.

◆ ValueMappingIdx

enum llvm::RISCV::ValueMappingIdx

Enumerator
InvalidIdx
GPRB32Idx
GPRB64Idx
FPRB16Idx
FPRB32Idx
FPRB64Idx
VRB64Idx
VRB128Idx
VRB256Idx
VRB512Idx

Definition at line 95 of file RISCVRegisterBankInfo.cpp.

Function Documentation

◆ fillValidCPUArchList()

void llvm::RISCV::fillValidCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64 )

Definition at line 108 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ fillValidTuneCPUArchList()

void llvm::RISCV::fillValidTuneCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64 )

Definition at line 115 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ getArgGPRs()

ArrayRef< MCPhysReg > llvm::RISCV::getArgGPRs ( const RISCVABI::ABI ABI )

Definition at line 127 of file RISCVCallingConv.cpp.

References llvm::RISCVABI::ABI_ILP32E, llvm::RISCVABI::ABI_LP64E, and llvm::ArrayRef().

Referenced by llvm::CC_RISCV(), CC_RISCVAssign2XLen(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ getCPUInfoByName()

const CPUInfo * llvm::RISCV::getCPUInfoByName ( StringRef CPU )

static

Definition at line 43 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, and RISCVCPUInfo.

Referenced by getCPUModel(), getMArchFromMcpu(), hasFastScalarUnalignedAccess(), hasFastVectorUnalignedAccess(), and parseCPU().

◆ getCPUModel()

CPUModel llvm::RISCV::getCPUModel ( StringRef CPU )

Definition at line 62 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

Referenced by hasValidCPUModel().

◆ getCPUNameFromCPUModel()

StringRef llvm::RISCV::getCPUNameFromCPUModel ( const CPUModel & Model )

Definition at line 69 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, and RISCVCPUInfo.

◆ getDestLog2EEW()

unsigned llvm::RISCV::getDestLog2EEW	(	const MCInstrDesc &	Desc,
		unsigned	Log2SEW )

Definition at line 4813 of file RISCVInstrInfo.cpp.

References assert(), llvm::RISCVII::DestEEWMask, llvm::RISCVII::DestEEWShift, and Scaled.

Referenced by INITIALIZE_PASS().

◆ getFeaturesForCPU()

void llvm::RISCV::getFeaturesForCPU	(	StringRef	CPU,
		SmallVectorImpl< std::string > &	EnabledFeatures,
		bool	NeedPlus = false )

Definition at line 125 of file RISCVTargetParser.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::errorToBool(), F, getMArchFromMcpu(), llvm::RISCVISAInfo::parseArchString(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getMArchFromMcpu()

StringRef llvm::RISCV::getMArchFromMcpu ( StringRef CPU )

Definition at line 101 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

Referenced by getFeaturesForCPU().

◆ getRVVMCOpcode()

unsigned llvm::RISCV::getRVVMCOpcode ( unsigned RVVPseudoOpcode )

Definition at line 4805 of file RISCVInstrInfo.cpp.

References llvm::RVV.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector(), getFoldedOpcode(), llvm::RISCVInstrInfo::getReassociateOperandIndices(), INITIALIZE_PASS(), llvm::RISCVInstrInfo::isHighLatencyDef(), llvm::RISCVInstrInfo::isReallyTriviallyReMaterializable(), isSegmentedStoreInstr(), vectorPseudoHasAllNBitUsers(), and vectorPseudoHasAllNBitUsers().

◆ getSpecifierName()

StringRef llvm::RISCV::getSpecifierName ( Specifier Kind )

Definition at line 46 of file RISCVMCExpr.cpp.

References llvm_unreachable, S_LO, S_None, S_PCREL_LO, S_QC_ABS20, and S_TPREL_LO.

Referenced by llvm::RISCVMCAsmInfo::printSpecifierExpr().

◆ getVectorLowDemandedScalarBits()

std::optional< unsigned > llvm::RISCV::getVectorLowDemandedScalarBits	(	unsigned	Opcode,
		unsigned	Log2SEW )

Definition at line 4688 of file RISCVInstrInfo.cpp.

Referenced by vectorPseudoHasAllNBitUsers(), and vectorPseudoHasAllNBitUsers().

◆ hasEqualFRM()

bool llvm::RISCV::hasEqualFRM	(	const MachineInstr &	MI1,
		const MachineInstr &	MI2 )

Definition at line 4675 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::hasReassociableSibling().

◆ hasFastScalarUnalignedAccess()

bool llvm::RISCV::hasFastScalarUnalignedAccess ( StringRef CPU )

Definition at line 50 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

◆ hasFastVectorUnalignedAccess()

bool llvm::RISCV::hasFastVectorUnalignedAccess ( StringRef CPU )

Definition at line 55 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

◆ hasValidCPUModel()

bool llvm::RISCV::hasValidCPUModel ( StringRef CPU )

Definition at line 60 of file RISCVTargetParser.cpp.

References getCPUModel(), and llvm::RISCV::CPUModel::isValid().

◆ isRVVSpill()

bool llvm::RISCV::isRVVSpill ( const MachineInstr & MI )

Definition at line 4624 of file RISCVInstrInfo.cpp.

References getLMULForRVVWholeLoadStore(), isRVVSpillForZvlsseg(), and MI.

Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and getScavSlotsNumForRVV().

◆ isRVVSpillForZvlsseg()

std::optional< std::pair< unsigned, unsigned > > llvm::RISCV::isRVVSpillForZvlsseg ( unsigned Opcode )

Definition at line 4635 of file RISCVInstrInfo.cpp.

Referenced by isRVVSpill(), and llvm::RISCVRegisterInfo::lowerSegmentSpillReload().

◆ isVLKnownLE()

bool llvm::RISCV::isVLKnownLE	(	const MachineOperand &	LHS,
		const MachineOperand &	RHS )

Given two VL operands, do we know that LHS <= RHS?

Given two VL operands, do we know that LHS <= RHS? Must be used in SSA form.

Definition at line 4838 of file RISCVInstrInfo.cpp.

References assert(), getEffectiveImm(), and VLMaxSentinel.

◆ parseCPU()

bool llvm::RISCV::parseCPU	(	StringRef	CPU,
		bool	IsRV64 )

Definition at line 79 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

Referenced by parseTuneCPU().

◆ parseSpecifierName()

RISCV::Specifier llvm::RISCV::parseSpecifierName ( StringRef name )

Definition at line 23 of file RISCVMCExpr.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), name, S_LO, S_PCREL_LO, S_QC_ABS20, and S_TPREL_LO.

◆ parseTuneCPU()

bool llvm::RISCV::parseTuneCPU	(	StringRef	CPU,
		bool	IsRV64 )

Definition at line 87 of file RISCVTargetParser.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), ENUM, parseCPU(), and TUNE_PROC.

Variable Documentation

◆ FPMASK_Negative_Infinity

unsigned llvm::RISCV::FPMASK_Negative_Infinity = 0x001

staticconstexpr

Definition at line 371 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Normal

unsigned llvm::RISCV::FPMASK_Negative_Normal = 0x002

staticconstexpr

Definition at line 372 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Subnormal

unsigned llvm::RISCV::FPMASK_Negative_Subnormal = 0x004

staticconstexpr

Definition at line 373 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Zero

unsigned llvm::RISCV::FPMASK_Negative_Zero = 0x008

staticconstexpr

Definition at line 374 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Infinity

unsigned llvm::RISCV::FPMASK_Positive_Infinity = 0x080

staticconstexpr

Definition at line 378 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Normal

unsigned llvm::RISCV::FPMASK_Positive_Normal = 0x040

staticconstexpr

Definition at line 377 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Subnormal

unsigned llvm::RISCV::FPMASK_Positive_Subnormal = 0x020

staticconstexpr

Definition at line 376 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Zero

unsigned llvm::RISCV::FPMASK_Positive_Zero = 0x010

staticconstexpr

Definition at line 375 of file RISCVInstrInfo.h.

◆ FPMASK_Quiet_NaN

unsigned llvm::RISCV::FPMASK_Quiet_NaN = 0x200

staticconstexpr

Definition at line 380 of file RISCVInstrInfo.h.

◆ FPMASK_Signaling_NaN

unsigned llvm::RISCV::FPMASK_Signaling_NaN = 0x100

staticconstexpr

Definition at line 379 of file RISCVInstrInfo.h.

◆ PartMappings

const RegisterBankInfo::PartialMapping llvm::RISCV::PartMappings[]

Initial value:

= {
    
    {0, 32, GPRBRegBank},
    {0, 64, GPRBRegBank},
    {0, 16, FPRBRegBank},
    {0, 32, FPRBRegBank},
    {0, 64, FPRBRegBank},
    {0, 64, VRBRegBank},
    {0, 128, VRBRegBank},
    {0, 256, VRBRegBank},
    {0, 512, VRBRegBank},
    
}

Definition at line 28 of file RISCVRegisterBankInfo.cpp.

◆ RISCVCPUInfo

CPUInfo llvm::RISCV::RISCVCPUInfo[]

constexpr

Initial value:

= {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN,                   FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)                  
                                                                         \
                                                                               \
                                                                               \
                                                                               \
                                                                               \
                                                                               \
                                                                               \
    
 
}

Definition at line 30 of file RISCVTargetParser.cpp.

Referenced by fillValidCPUArchList(), fillValidTuneCPUArchList(), getCPUInfoByName(), and getCPUNameFromCPUModel().

◆ RVVBitsPerBlock

unsigned llvm::RISCV::RVVBitsPerBlock = 64

staticconstexpr

Definition at line 51 of file RISCVTargetParser.h.

Referenced by computeKnownBitsFromOperator(), llvm::RISCVTargetLowering::computeVLMAX(), llvm::RISCVSubtarget::expandVScale(), getContainerForFixedLengthVector(), getLMUL1Ty(), llvm::RISCVTargetLowering::getM1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetMachine::getSubtargetImpl(), llvm::RISCVTTIImpl::getVScaleForTuning(), isTupleInsertInstr(), isValidEGW(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), llvm::RISCVInstrInfo::loadRegFromStackSlot(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::RISCVInstrInfo::storeRegToStackSlot(), and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().

◆ RVVBytesPerBlock

unsigned llvm::RISCV::RVVBytesPerBlock = RVVBitsPerBlock / 8

staticconstexpr

Definition at line 52 of file RISCVTargetParser.h.

Referenced by llvm::RISCVRegisterInfo::adjustReg(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::RISCVInstrInfo::isLoadFromStackSlot(), and llvm::RISCVInstrInfo::isStoreToStackSlot().

◆ ValueMappings

const RegisterBankInfo::ValueMapping llvm::RISCV::ValueMappings[]

Definition at line 54 of file RISCVRegisterBankInfo.cpp.

Referenced by getFPValueMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), and getVRBValueMapping().

◆ VLMaxSentinel

int64_t llvm::RISCV::VLMaxSentinel = -1LL

staticconstexpr

Definition at line 365 of file RISCVInstrInfo.h.

Referenced by isVLKnownLE(), and llvm::RISCVDAGToDAGISel::selectVLOp().

Classes

Typedefs

Enumerations

Functions

Variables

Typedef Documentation

◆ Specifier

Enumeration Type Documentation

◆ anonymous enum

◆ CPUKind

◆ Fixups

◆ PartialMappingIdx

◆ ValueMappingIdx

Function Documentation

◆ fillValidCPUArchList()

◆ fillValidTuneCPUArchList()

◆ getArgGPRs()

◆ getCPUInfoByName()

◆ getCPUModel()

◆ getCPUNameFromCPUModel()

◆ getDestLog2EEW()

◆ getFeaturesForCPU()

◆ getMArchFromMcpu()

◆ getRVVMCOpcode()

◆ getSpecifierName()

◆ getVectorLowDemandedScalarBits()

◆ hasEqualFRM()

◆ hasFastScalarUnalignedAccess()

◆ hasFastVectorUnalignedAccess()

◆ hasValidCPUModel()

◆ isRVVSpill()

◆ isRVVSpillForZvlsseg()

◆ isVLKnownLE()

◆ parseCPU()

◆ parseSpecifierName()

◆ parseTuneCPU()

Variable Documentation

◆ FPMASK_Negative_Infinity

◆ FPMASK_Negative_Normal

◆ FPMASK_Negative_Subnormal

◆ FPMASK_Negative_Zero

◆ FPMASK_Positive_Infinity

◆ FPMASK_Positive_Normal

◆ FPMASK_Positive_Subnormal

◆ FPMASK_Positive_Zero

◆ FPMASK_Quiet_NaN

◆ FPMASK_Signaling_NaN

◆ PartMappings

◆ RISCVCPUInfo

◆ RVVBitsPerBlock

◆ RVVBytesPerBlock

◆ ValueMappings

◆ VLMaxSentinel