#include "llvm/CodeGen/ValueTypes.h"
Classes | |
| struct | compareRawBits |
| A meaningless but well-behaved order, useful for constructing containers. More... | |
Public Member Functions | |
| constexpr | EVT ()=default |
| constexpr | EVT (MVT::SimpleValueType SVT) |
| constexpr | EVT (MVT S) |
| bool | operator== (EVT VT) const |
| bool | operator!= (EVT VT) const |
| EVT | changeVectorElementTypeToInteger () const |
| Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth. | |
| EVT | changeVectorElementType (EVT EltVT) const |
| Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller. | |
| EVT | changeElementType (EVT EltVT) const |
| Return a VT for a type whose attributes match ourselves with the exception of the element type that is chosen by the caller. | |
| EVT | changeTypeToInteger () const |
| Return the type converted to an equivalently sized integer or vector with integer element type. | |
| bool | isZeroSized () const |
| Test if the given EVT has zero size, this will fail if called on a scalable type. | |
| bool | isSimple () const |
| Test if the given EVT is simple (as opposed to being extended). | |
| bool | isExtended () const |
| Test if the given EVT is extended (as opposed to being simple). | |
| bool | isFloatingPoint () const |
| Return true if this is a FP or a vector FP type. | |
| bool | isInteger () const |
| Return true if this is an integer or a vector integer type. | |
| bool | isScalarInteger () const |
| Return true if this is an integer, but not a vector. | |
| bool | isScalableTargetExtVT () const |
| Return true if this is a vector type where the runtime length is machine dependent. | |
| bool | isVector () const |
| Return true if this is a vector value type. | |
| bool | isScalableVector () const |
| Return true if this is a vector type where the runtime length is machine dependent. | |
| bool | isRISCVVectorTuple () const |
| Return true if this is a vector value type. | |
| bool | isFixedLengthVector () const |
| bool | isScalableVT () const |
| Return true if the type is a scalable type. | |
| bool | is16BitVector () const |
| Return true if this is a 16-bit vector type. | |
| bool | is32BitVector () const |
| Return true if this is a 32-bit vector type. | |
| bool | is64BitVector () const |
| Return true if this is a 64-bit vector type. | |
| bool | is128BitVector () const |
| Return true if this is a 128-bit vector type. | |
| bool | is256BitVector () const |
| Return true if this is a 256-bit vector type. | |
| bool | is512BitVector () const |
| Return true if this is a 512-bit vector type. | |
| bool | is1024BitVector () const |
| Return true if this is a 1024-bit vector type. | |
| bool | is2048BitVector () const |
| Return true if this is a 2048-bit vector type. | |
| bool | isCheriCapability () const |
| Return true if this is a capability type. | |
| bool | isOverloaded () const |
| Return true if this is an overloaded type for TableGen. | |
| bool | isByteSized () const |
| Return true if the bit size is a multiple of 8. | |
| bool | isRound () const |
| Return true if the size is a power-of-two number of bytes. | |
| bool | bitsEq (EVT VT) const |
| Return true if this has the same number of bits as VT. | |
| bool | knownBitsGT (EVT VT) const |
| Return true if we know at compile time this has more bits than VT. | |
| bool | knownBitsGE (EVT VT) const |
| Return true if we know at compile time this has more than or the same bits as VT. | |
| bool | knownBitsLT (EVT VT) const |
| Return true if we know at compile time this has fewer bits than VT. | |
| bool | knownBitsLE (EVT VT) const |
| Return true if we know at compile time this has fewer than or the same bits as VT. | |
| bool | bitsGT (EVT VT) const |
| Return true if this has more bits than VT. | |
| bool | bitsGE (EVT VT) const |
| Return true if this has no less bits than VT. | |
| bool | bitsLT (EVT VT) const |
| Return true if this has less bits than VT. | |
| bool | bitsLE (EVT VT) const |
| Return true if this has no more bits than VT. | |
| MVT | getSimpleVT () const |
| Return the SimpleValueType held in the specified simple EVT. | |
| EVT | getScalarType () const |
| If this is a vector type, return the element type, otherwise return this. | |
| EVT | getVectorElementType () const |
| Given a vector type, return the type of each element. | |
| unsigned | getVectorNumElements () const |
| Given a vector type, return the number of elements it contains. | |
| ElementCount | getVectorElementCount () const |
| unsigned | getVectorMinNumElements () const |
| Given a vector type, return the minimum number of elements it contains. | |
| unsigned | getRISCVVectorTupleNumFields () const |
| Given a RISCV vector tuple type, return the num_fields. | |
| TypeSize | getSizeInBits () const |
| Return the size of the specified value type in bits. | |
| uint64_t | getFixedSizeInBits () const |
| Return the size of the specified fixed width value type in bits. | |
| uint64_t | getScalarSizeInBits () const |
| TypeSize | getStoreSize () const |
| Return the number of bytes overwritten by a store of the specified value type. | |
| uint64_t | getScalarStoreSize () const |
| TypeSize | getStoreSizeInBits () const |
| Return the number of bits overwritten by a store of the specified value type. | |
| EVT | getRoundIntegerType (LLVMContext &Context) const |
| Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight), and returns the integer EVT with that number of bits. | |
| EVT | getHalfSizedIntegerVT (LLVMContext &Context) const |
| Finds the smallest simple value type that is greater than or equal to half the width of this EVT. | |
| EVT | widenIntegerVectorElementType (LLVMContext &Context) const |
| Return a VT for an integer vector type with the size of the elements doubled. | |
| EVT | getHalfNumVectorElementsVT (LLVMContext &Context) const |
| EVT | getDoubleNumVectorElementsVT (LLVMContext &Context) const |
| bool | isPow2VectorType () const |
| Returns true if the given vector is a power of 2. | |
| EVT | getPow2VectorType (LLVMContext &Context) const |
| Widens the length of the given vector EVT up to the nearest power of 2 and returns that type. | |
| LLVM_ABI std::string | getEVTString () const |
| This function returns value type as a string, e.g. "i32". | |
| LLVM_ABI void | dump () const |
| Support for debugging, callable in GDB: VT.dump() | |
| void | print (raw_ostream &OS) const |
| Implement operator<<. | |
| LLVM_ABI Type * | getTypeForEVT (LLVMContext &Context) const |
| This method returns an LLVM type corresponding to the specified EVT. | |
| intptr_t | getRawBits () const |
| LLVM_ABI const fltSemantics & | getFltSemantics () const |
| Returns an APFloat semantics tag appropriate for the value type. | |
Static Public Member Functions | |
| static EVT | getFloatingPointVT (unsigned BitWidth) |
| Returns the EVT that represents a floating-point type with the given number of bits. | |
| static EVT | getIntegerVT (LLVMContext &Context, unsigned BitWidth) |
| Returns the EVT that represents an integer with the given number of bits. | |
| static EVT | getVectorVT (LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false) |
| Returns the EVT that represents a vector NumElements in length, where each element is of type VT. | |
| static EVT | getVectorVT (LLVMContext &Context, EVT VT, ElementCount EC) |
| Returns the EVT that represents a vector EC.Min elements in length, where each element is of type VT. | |
| static LLVM_ABI EVT | getEVT (Type *Ty, bool HandleUnknown=false) |
| Return the value type corresponding to the specified type. | |
Detailed Description
Capable of holding value types which are not native for any processor (such as the i12345 type), as well as the types an MVT can represent.
Definition at line 35 of file ValueTypes.h.
Constructor & Destructor Documentation
◆ EVT() [1/3]
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constexprdefault |
Referenced by bitsEq(), bitsGE(), bitsGT(), bitsLE(), bitsLT(), changeElementType(), changeTypeToInteger(), changeVectorElementType(), changeVectorElementTypeToInteger(), getDoubleNumVectorElementsVT(), getEVT(), getFloatingPointVT(), getHalfNumVectorElementsVT(), getHalfSizedIntegerVT(), getIntegerVT(), getPow2VectorType(), getRoundIntegerType(), getScalarType(), getVectorElementType(), getVectorVT(), getVectorVT(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), operator!=(), llvm::EVT::compareRawBits::operator()(), operator==(), and widenIntegerVectorElementType().
◆ EVT() [2/3]
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inlineconstexpr |
Definition at line 42 of file ValueTypes.h.
◆ EVT() [3/3]
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inlineconstexpr |
Definition at line 43 of file ValueTypes.h.
Member Function Documentation
◆ bitsEq()
Return true if this has the same number of bits as VT.
Definition at line 256 of file ValueTypes.h.
References EVT(), and getSizeInBits().
Referenced by llvm::SelectionDAG::getStrictFPExtendOrRound(), lowerFCMPIntrinsic(), lowerICMPIntrinsic(), llvm::AMDGPUDAGToDAGISel::Select(), and llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle().
◆ bitsGE()
Return true if this has no less bits than VT.
Definition at line 292 of file ValueTypes.h.
References assert(), EVT(), isScalableVector(), and knownBitsGE().
Referenced by findFPToIntLibcall(), getCopyToPartsVector(), getMemcpyLoadsAndStores(), llvm::isConstOrConstSplat(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), performSIGN_EXTEND_INREGCombine(), and unrollVectorShift().
◆ bitsGT()
Return true if this has more bits than VT.
Definition at line 284 of file ValueTypes.h.
References assert(), EVT(), isScalableVector(), and knownBitsGT().
Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::R600TargetLowering::allowsMisalignedMemoryAccesses(), correctParamType(), llvm::TargetLowering::findOptimalMemOpLowering(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::AArch64TTIImpl::getCastInstrCost(), getCopyToPartsVector(), llvm::SelectionDAG::getFPExtendOrRound(), llvm::SelectionDAG::getNode(), llvm::FastISel::getRegForGEPIndex(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getStrictFPExtendOrRound(), getSVEPredicateBitCast(), llvm::SelectionDAG::getVPZExtOrTrunc(), llvm::SelectionDAG::getZExtOrTrunc(), LowerSELECTWithCmpZero(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::FastISel::selectOperator(), llvm::TargetLowering::SimplifySetCC(), and tryToReplaceScalarFPConversionWithSVE().
◆ bitsLE()
Return true if this has no more bits than VT.
Definition at line 308 of file ValueTypes.h.
References assert(), EVT(), isScalableVector(), and knownBitsLE().
Referenced by llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getVPZeroExtendInReg(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), PerformVECREDUCE_ADDCombine(), and llvm::TargetLowering::SimplifySetCC().
◆ bitsLT()
Return true if this has less bits than VT.
Definition at line 300 of file ValueTypes.h.
References assert(), EVT(), isScalableVector(), and knownBitsLT().
Referenced by llvm::R600TargetLowering::allowsMisalignedMemoryAccesses(), combineShuffleOfScalars(), correctParamType(), llvm::TargetLowering::expandMULO(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAG::getLoad(), getLoadExtOrTrunc(), getMemsetStores(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::FastISel::getRegForGEPIndex(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::MipsTargetLowering::getTypeForExtReturn(), llvm::TargetLowering::getTypeForExtReturn(), llvm::SelectionDAG::getVPZExtOrTrunc(), handleCMSEValue(), legalizeScatterGatherIndexType(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::SITargetLowering::LowerFormalArguments(), LowerSELECTWithCmpZero(), matchPMADDWD_2(), narrowIndex(), OptimizeNoopCopyExpression(), llvm::AArch64TargetLowering::ReconstructShuffle(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::FastISel::selectOperator(), and llvm::TargetLowering::SimplifySetCC().
◆ changeElementType()
Return a VT for a type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
Definition at line 113 of file ValueTypes.h.
References changeVectorElementType(), EVT(), getScalarType(), and isVector().
◆ changeTypeToInteger()
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inline |
Return the type converted to an equivalently sized integer or vector with integer element type.
Similar to changeVectorElementTypeToInteger, but also handles scalars.
Definition at line 121 of file ValueTypes.h.
References llvm::MVT::changeTypeToInteger(), changeVectorElementTypeToInteger(), EVT(), getSimpleVT(), isSimple(), and isVector().
Referenced by adjustLoadValueTypeImpl(), combineFP_EXTEND(), constructRetValue(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandVECTOR_COMPRESS(), GenerateFixedLengthSVETBL(), getMemsetStringVal(), LowerFMINIMUM_FMAXIMUM(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SITargetLowering::lowerFP_EXTEND(), PerformEXTRACTCombine(), performLD1ReplicateCombine(), performLDNT1Combine(), performSTNT1Combine(), and llvm::AMDGPUTargetLowering::performTruncateCombine().
◆ changeVectorElementType()
Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
Definition at line 102 of file ValueTypes.h.
References assert(), llvm::MVT::changeVectorElementType(), EVT(), getSimpleVT(), and isSimple().
Referenced by changeElementType(), combineAnd(), combineArithReduction(), combineConcatVectorOps(), combineEXTEND_VECTOR_INREG(), combineFP_EXTEND(), combineGatherScatter(), combineMulToPMADDWD(), combineSelect(), combineSIntToFP(), combineTruncateWithSat(), combineUIntToFP(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorFindLastActive(), findMoreOptimalIndexType(), getMemVTFromNode(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), getPredicateForScalableVector(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), getVectorBitwiseReduce(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), legalizeScatterGatherIndexType(), LowerFLDEXP(), LowerVectorAllEqual(), narrowIndex(), performBuildShuffleExtendCombine(), performBuildVectorCombine(), performSETCCCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performUnpackCombine(), PerformVECREDUCE_ADDCombine(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), llvm::X86TargetLowering::ReplaceNodeResults(), tryToReplaceScalarFPConversionWithSVE(), tryToWidenSetCCOperands(), and widenVectorToPartType().
◆ changeVectorElementTypeToInteger()
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inline |
Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.
Definition at line 94 of file ValueTypes.h.
References llvm::MVT::changeVectorElementTypeToInteger(), EVT(), getSimpleVT(), and isSimple().
Referenced by changeTypeToInteger(), combineBitcast(), combineExtSetcc(), combineFP_EXTEND(), combineFP_ROUND(), combineSelect(), createVariablePermute(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::CSKYTargetLowering::getSetCCResultType(), llvm::LoongArchTargetLowering::getSetCCResultType(), llvm::MipsTargetLowering::getSetCCResultType(), llvm::PPCTargetLowering::getSetCCResultType(), llvm::R600TargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::SparcTargetLowering::getSetCCResultType(), llvm::SystemZTargetLowering::getSetCCResultType(), llvm::X86TargetLowering::getSetCCResultType(), llvm::XtensaTargetLowering::getSetCCResultType(), lowerVECTOR_SHUFFLE_VSHF(), LowerVSETCC(), LowerVSETCC(), performSelectCombine(), performVSelectCombine(), and llvm::X86TargetLowering::ReplaceNodeResults().
◆ dump()
| void EVT::dump | ( | ) | const |
Support for debugging, callable in GDB: VT.dump()
Definition at line 209 of file ValueTypes.cpp.
References llvm::dbgs(), and print().
◆ getDoubleNumVectorElementsVT()
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inline |
Definition at line 463 of file ValueTypes.h.
References EVT(), getVectorElementCount(), getVectorElementType(), and getVectorVT().
Referenced by combineConcatVectorOps(), LowerCONCAT_VECTORS_i1(), performDUPCombine(), performExtBinopLoadFold(), llvm::AMDGPUTargetLowering::performShlCombine(), performSignExtendInRegCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performUADDVZextCombine(), performUzpCombine(), and tryCombineMULLWithUZP1().
◆ getEVT()
Return the value type corresponding to the specified type.
getEVT - Return the value type corresponding to the specified type.
If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid. NB: This includes pointer types, which require a DataLayout to convert to a concrete value type.
Definition at line 301 of file ValueTypes.cpp.
References llvm::cast(), EVT(), llvm::Type::FixedVectorTyID, llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), getEVT(), getIntegerVT(), getVectorVT(), llvm::MVT::getVT(), llvm::Type::IntegerTyID, llvm::Type::ScalableVectorTyID, and llvm::Type::TokenTyID.
Referenced by llvm::ARMTargetLowering::allowTruncateForTailCall(), llvm::X86TargetLowering::allowTruncateForTailCall(), llvm::CallLowering::determineAssignments(), llvm::BasicTTIImplBase< BasicTTIImpl >::getCastInstrCost(), getEVT(), llvm::TargetLoweringBase::getMemValueType(), llvm::AArch64TTIImpl::getPartialReductionCost(), llvm::WebAssemblyTTIImpl::getPartialReductionCost(), llvm::FastISel::getRegForGEPIndex(), llvm::TargetLoweringBase::getValueType(), llvm::CallLowering::handleAssignments(), llvm::TargetLoweringBase::isExtFree(), isNoopBitcast(), llvm::HexagonTargetLowering::isTruncateFree(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::ARMTargetLowering::lowerInterleavedLoad(), llvm::ARMTargetLowering::lowerInterleavedStore(), llvm::FastISel::selectBinaryOp(), sinkCmpExpression(), splitMergedValStore(), and targetSupportsFrem().
◆ getEVTString()
| std::string EVT::getEVTString | ( | ) | const |
This function returns value type as a string, e.g. "i32".
getEVTString - This function returns value type as a string, e.g. "i32".
Definition at line 162 of file ValueTypes.cpp.
References getEVTString(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getRISCVVectorTupleNumFields(), getSizeInBits(), getVectorElementCount(), getVectorElementType(), isCheriCapability(), isFloatingPoint(), isInteger(), isRISCVVectorTuple(), isScalableVector(), isVector(), llvm_unreachable, and llvm::utostr().
Referenced by checkOperandType(), checkResultType(), getEVTString(), print(), llvm::MVT::print(), and llvm::SDNode::print_types().
◆ getFixedSizeInBits()
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inline |
Return the size of the specified fixed width value type in bits.
The function will assert if the type is scalable.
Definition at line 381 of file ValueTypes.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), and getSizeInBits().
Referenced by clampDynamicVectorIndex(), combineBROADCAST_LOAD(), combineConstantPoolLoads(), combineLoad(), combineSCALAR_TO_VECTOR(), combineToVCPOP(), expandMulToNAFSequence(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVectorSplice(), findMemType(), llvm::TargetLowering::forceExpandWideMUL(), getCopyFromPartsVector(), getCopyToPartsVector(), getFauxShuffleMask(), getReducedGprRegisterClass(), llvm::SDValue::getScalarValueSizeInBits(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::AArch64TargetLowering::hasAndNot(), llvm::TargetLowering::IncrementMemoryAddress(), IsMulWideOperandDemotable(), llvm::AArch64TargetLowering::isTruncateFree(), llvm::MSP430TargetLowering::isTruncateFree(), llvm::SystemZTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), lookThroughSignExtension(), LowerVAARG(), lowerVECTOR_COMPRESS(), LowerVectorMatch(), performBitcastCombine(), performFPExtendCombine(), performSETCCCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), promoteScalarIntegerPTX(), llvm::AArch64TargetLowering::ReconstructShuffle(), llvm::AArch64TargetLowering::shouldExpandGetActiveLaneMask(), llvm::AArch64TargetLowering::shouldFoldConstantShiftPairToMask(), shouldLowerTailCallStackArg(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), truncateScalarIntegerArg(), trySQDMULHCombine(), tryWidenMaskForShuffle(), llvm::AArch64Subtarget::useSVEForFixedLengthVectors(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), and widenSubVector().
◆ getFloatingPointVT()
Returns the EVT that represents a floating-point type with the given number of bits.
There are two floating-point types with 128 bits - this returns f128 rather than ppcf128.
Definition at line 59 of file ValueTypes.h.
References llvm::BitWidth, EVT(), and llvm::MVT::getFloatingPointVT().
Referenced by EltsFromConsecutiveLoads(), lowerFP_TO_SINT_STORE(), LowerVECTOR_SHUFFLE(), and llvm::LoongArchTargetLowering::ReplaceNodeResults().
◆ getFltSemantics()
| const fltSemantics & EVT::getFltSemantics | ( | ) | const |
Returns an APFloat semantics tag appropriate for the value type.
If this is a vector type, the element semantics are returned.
Definition at line 332 of file ValueTypes.cpp.
References llvm::MVT::getFltSemantics(), getScalarType(), and getSimpleVT().
Referenced by llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::foldConstantFPMath(), FoldIntToFPToInt(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getDenormalMode(), getEstimate(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getMemsetValue(), llvm::SelectionDAG::getNeutralElement(), llvm::TargetLowering::getSqrtInputTest(), llvm::isNeutralConstant(), llvm::ConstantFPSDNode::isValueValidForType(), and llvm::TargetLowering::SimplifyDemandedBits().
◆ getHalfNumVectorElementsVT()
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inline |
Definition at line 453 of file ValueTypes.h.
References assert(), EVT(), getVectorElementCount(), getVectorElementType(), and getVectorVT().
Referenced by combineAndShuffleNot(), llvm::TargetLowering::expandVecReduce(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::TargetLoweringBase::getTypeConversion(), isUpperSubvectorUndef(), LowerVectorExtend(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performSunpkloCombine(), splitStores(), splitVector(), truncateVectorWithPACK(), and tryFormConcatFromShuffle().
◆ getHalfSizedIntegerVT()
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inline |
Finds the smallest simple value type that is greater than or equal to half the width of this EVT.
If no simple value type can be found, an extended integer value type of half the size (rounded up) is returned.
Definition at line 430 of file ValueTypes.h.
References assert(), EVT(), getIntegerVT(), getSizeInBits(), isInteger(), and isVector().
Referenced by combineBinOpOfZExt(), llvm::TargetLowering::expandUnalignedStore(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performVectorExtCombine(), and skipExtensionForVectorMULL().
◆ getIntegerVT()
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inlinestatic |
Returns the EVT that represents an integer with the given number of bits.
Definition at line 65 of file ValueTypes.h.
References llvm::BitWidth, EVT(), llvm::MVT::getIntegerVT(), and llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.
Referenced by llvm::BasicTTIImplBase< BasicTTIImpl >::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), combineAnd(), combineBitcastvxi1(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineExtractWithShuffle(), combinei64TruncSrlConstant(), combineLoad(), combineOr(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineShiftToAVG(), combineShuffleToZeroExtendVectorInReg(), combineStore(), combineVectorMulToSraBitcast(), combinevXi1ConstantToInteger(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandAVG(), expandDivFix(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::SelectionDAG::FoldConstantBuildVector(), llvm::TargetLowering::forceExpandWideMUL(), llvm::getApproximateEVTForLLT(), llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(), getCopyFromParts(), getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::AMDGPUTargetLowering::getEquivalentMemType(), getEVT(), getHalfSizedIntegerVT(), getMemsetValue(), getPackedVectorTypeFromPredicateType(), getRoundIntegerType(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), llvm::AMDGPUTargetLowering::getTypeForExtReturn(), llvm::X86TargetLowering::getTypeToTransformTo(), getVectorBitwiseReduce(), llvm::TargetLowering::IncrementMemoryAddress(), lowerBitreverseShuffle(), llvm::SystemZTargetLowering::LowerCall(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerFCMPIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), lowerICMPIntrinsic(), LowerPredicateLoad(), LowerPredicateStore(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), LowerStore(), LowerVectorAllEqual(), narrowIndex(), performBITCASTCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), PerformExtractFpToIntStores(), PerformMinMaxFpToSatCombine(), performMulVectorCmpZeroCombine(), performSETCC_BITCASTCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), PerformUMinFpToSatCombine(), performVECTOR_SHUFFLECombine(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::FastISel::selectFNeg(), llvm::TargetLowering::ShrinkDemandedOp(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), and widenIntegerVectorElementType().
◆ getPow2VectorType()
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Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition at line 477 of file ValueTypes.h.
References EVT(), llvm::ElementCount::get(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getVectorElementCount(), getVectorElementType(), getVectorVT(), isPow2VectorType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), and llvm::Log2_32_Ceil().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), and llvm::TargetLoweringBase::getTypeConversion().
◆ getRawBits()
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Definition at line 512 of file ValueTypes.h.
References isSimple().
Referenced by AddNodeIDCustom(), llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getGatherVP(), llvm::SelectionDAG::getGetFPEnv(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getLoadFFVP(), llvm::SelectionDAG::getLoadVP(), llvm::SelectionDAG::getMaskedGather(), llvm::SelectionDAG::getMaskedHistogram(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMaskedScatter(), llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getScatterVP(), llvm::SelectionDAG::getSetFPEnv(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getStoreVP(), llvm::SelectionDAG::getStridedLoadVP(), llvm::SelectionDAG::getStridedStoreVP(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getVTList(), and llvm::SelectionDAG::getVTList().
◆ getRISCVVectorTupleNumFields()
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Given a RISCV vector tuple type, return the num_fields.
Definition at line 364 of file ValueTypes.h.
Referenced by getEVTString(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().
◆ getRoundIntegerType()
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Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight), and returns the integer EVT with that number of bits.
Definition at line 419 of file ValueTypes.h.
References assert(), llvm::bit_ceil(), llvm::BitWidth, EVT(), getIntegerVT(), getSizeInBits(), isInteger(), and isVector().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLoweringBase::getTypeConversion(), and narrowIndex().
◆ getScalarSizeInBits()
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Definition at line 385 of file ValueTypes.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getSizeInBits().
Referenced by llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), areLoadedOffsetButOtherwiseSame(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), canExpandVectorCTPOP(), canLowerSRLToRoundingShiftForVT(), canonicalizeShuffleWithOp(), canReduceVMulWidth(), checkSignTestSetCCCombine(), combineAnd(), combineAndMaskToShift(), combineArithReduction(), combineAVG(), combineAVX512SetCCToKMOV(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBitcast(), combineBitOpWithMOVMSK(), combineCMP(), combineConcatVectorOps(), combineConstantPoolLoads(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineHorizOpWithShuffle(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMaskedLoad(), combineMaskedStore(), combineOr(), combineOrXorWithSETCC(), combinePMULH(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSetCC(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineTruncatedArithmetic(), combineTruncationShuffle(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorInsert(), combineVectorMulToSraBitcast(), combineVectorPack(), combineVectorShiftImm(), combineVSelectWithAllOnesOrZeros(), combineVTRUNC(), combineZext(), llvm::SelectionDAG::computeKnownBits(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::AArch64TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), createBSWAPShuffleMask(), createShuffleMaskFromVSELECT(), llvm::createUnpackShuffleMask(), createVariablePermute(), llvm::X86TargetLowering::decomposeMulByConstant(), llvm::XtensaTargetLowering::decomposeMulByConstant(), detectSSatPattern(), detectSSatSPattern(), detectSSatUPattern(), detectUSatPattern(), detectUSatUPattern(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), expandVPFunnelShift(), extractShiftForRotate(), findMoreOptimalIndexType(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndToUsubsat(), foldBoolSelectToLogic(), llvm::SelectionDAG::FoldConstantArithmetic(), FoldIntToFPToInt(), foldSubCtlzNot(), foldVSelectToSignBitSplatMask(), GeneratePerfectShuffle(), GeneratePerfectShuffle(), generateSToVPermutedForVecShuffle(), llvm::SelectionDAG::getAllOnesConstant(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::GCNTTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantRawBits(), getEXTEND_VECTOR_INREG(), getFauxShuffleMask(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::ARMTTIImpl::getIntrinsicInstrCost(), llvm::SelectionDAG::getLoad(), llvm::AArch64TTIImpl::getMemoryOpCost(), getMemsetValue(), llvm::ARMTTIImpl::getMinMaxReductionCost(), llvm::GCNTTIImpl::getMinMaxReductionCost(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::AArch64TTIImpl::getPartialReductionCost(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getStepVector(), llvm::SelectionDAG::getStepVector(), getTargetConstantBitsFromNode(), getTruncatedUSUBSAT(), getVectorShuffleOpcode(), llvm::SelectionDAG::getVPZeroExtendInReg(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::TargetLowering::IncrementMemoryAddress(), insertSubVector(), llvm::SelectionDAG::isBoolConstant(), llvm::AArch64TargetLowering::isComplexDeinterleavingOperationSupported(), llvm::ARMTargetLowering::isComplexDeinterleavingOperationSupported(), llvm::BuildVectorSDNode::isConstantSequence(), llvm::BuildVectorSDNode::isConstantSplat(), IsElementEquivalent(), isExtendedBUILD_VECTOR(), isExtendedBUILD_VECTOR(), isFNEG(), llvm::RISCVTargetLowering::isFPImmLegal(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), isLegalBitRotate(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), llvm::AMDGPUTargetLowering::isNarrowingProfitable(), llvm::AArch64TargetLowering::isShuffleMaskLegal(), llvm::ARMTargetLowering::isShuffleMaskLegal(), llvm::SelectionDAG::isSplatValue(), isValidEGW(), isValidMtVsrBmi(), isVectorElementSwap(), llvm::isVREVMask(), isVShiftLImm(), isVShiftLImm(), isVShiftRImm(), isVShiftRImm(), isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), isWideDUPMask(), lower1BitShuffle(), lowerBALLOTIntrinsic(), lowerBitreverseShuffle(), LowerCONCAT_VECTORS(), LowerCTPOP(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), LowerFMINIMUM_FMAXIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), LowerFP_TO_INT_SAT(), LowerINSERT_VECTOR_ELT_i1(), lowerMSABitClearImm(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVectorAllEqual(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), MatchVectorAllEqualTest(), matchVPMADD52(), narrowIndex(), PerformBITCASTCombine(), performBuildShuffleExtendCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), performFP_TO_INTCombine(), performFpToIntCombine(), performGatherLoadCombine(), performMulVectorCmpZeroCombine(), PerformMVEVMULLCombine(), performPostLD1Combine(), performScatterStoreCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVZextCombine(), PerformVDUPLANECombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVECTOR_SHUFFLECombine(), performVP_STORECombine(), performVP_TRUNCATECombine(), PerformVQDMULHCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), performZExtDeinterleaveShuffleCombine(), performZExtUZPCombine(), llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(), llvm::ARMTargetLowering::preferIncOfAddToSubOfNot(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), llvm::X86TargetLowering::ReplaceNodeResults(), reverseZExtICmpCombine(), SaturateWidenedDIVFIX(), llvm::AMDGPUDAGToDAGISel::Select(), selectUmullSmull(), llvm::AArch64TargetLowering::shouldFoldConstantShiftPairToMask(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), llvm::SelectionDAG::SplitEVL(), stripModuloOnShift(), supportedVectorShiftWithImm(), supportedVectorVarShift(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), TryCombineBaseUpdate(), tryLowerToBSL(), tryLowerToSLI(), trySQDMULHCombine(), tryToFoldExtendOfConstant(), tryToWidenSetCCOperands(), and visitORCommutative().
◆ getScalarStoreSize()
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Definition at line 402 of file ValueTypes.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getStoreSize().
Referenced by matchIndexAsShuffle(), matchIndexAsWiderOp(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ getScalarType()
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If this is a vector type, return the element type, otherwise return this.
Definition at line 323 of file ValueTypes.h.
References EVT(), getVectorElementType(), and isVector().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), BuildExactSDIV(), BuildExactUDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), changeElementType(), combineAdd(), combineAnd(), combineAndnp(), combineArithReduction(), combineAVG(), combineBitcast(), combineBitcastvxi1(), combineBITREVERSE(), combineConcatVectorOps(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFMA(), combineFMinNumFMaxNum(), combineFneg(), combineFP_EXTEND(), combineFPToSInt(), combineLoad(), combineLRINT_LLRINT(), combineMinMaxReduction(), combineSCALAR_TO_VECTOR(), combineSelect(), combineShuffleOfScalars(), combineSIntToFP(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineTruncatedArithmetic(), combineUIntToFP(), CombineVMOVDRRCandidateWithVecOp(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), concatSubVectors(), llvm::createUnpackShuffleMask(), llvm::SITargetLowering::denormalsEnabledForType(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVPCTTZElements(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldSetCC(), foldShuffleOfConcatUndefs(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getConstantFP(), getCopyFromPartsVector(), getCopyToPartsVector(), getEstimateRefinementSteps(), getEstimateRefinementSteps(), getFauxShuffleMask(), getFltSemantics(), llvm::BasicTTIImplBase< BasicTTIImpl >::getIntrinsicInstrCost(), llvm::SelectionDAG::getLoad(), getMemsetStores(), getMemsetValue(), llvm::X86TargetLowering::getNegatedExpression(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SITargetLowering::getNumRegistersForCallingConv(), getReciprocalOpName(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), getScalarSizeInBits(), getScalarStoreSize(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::X86TTIImpl::getVectorInstrCost(), getVectorizedVT(), getVectorShuffle(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::AArch64TargetLowering::isComplexDeinterleavingOperationSupported(), llvm::ARMTargetLowering::isComplexDeinterleavingOperationSupported(), llvm::X86TargetLowering::isExtractVecEltCheap(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::AMDGPUTargetLowering::isFNegFree(), llvm::SITargetLowering::isFPExtFoldable(), llvm::AMDGPUTargetLowering::isFPImmLegal(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(), llvm::RISCVTTIImpl::isLegalMaskedLoadStore(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), isSaturatingMinMax(), llvm::X86TargetLowering::isVectorLoadExtDesirable(), LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::SITargetLowering::lowerFP_EXTEND(), LowerFP_TO_INT_SAT(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerTruncate(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVectorExtend(), lowerVectorSplatImm(), llvm::ISD::matchBinaryPredicate(), llvm::SelectionDAG::matchBinOpReduction(), matchPMADDWD_2(), narrowExtractedVectorBinOp(), padEltsToUndef(), performBITCASTCombine(), performBitcastCombine(), performBuildShuffleExtendCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformMinMaxFpToSatCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), performVectorExtCombine(), PerformVQDMULHCombine(), performVSelectCombine(), llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(), ReplaceAddWithADDP(), replaceLoadVector(), scalarizeExtEltFP(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), setInfoSVEStN(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(), llvm::RISCVTargetLowering::shouldScalarizeBinop(), llvm::X86TargetLowering::shouldScalarizeBinop(), llvm::AMDGPUTargetLowering::ShouldShrinkFPConstant(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), skipExtensionForVectorMULL(), takeInexpensiveLog2(), trySQDMULHCombine(), tryToFoldExtendOfConstant(), and widenSubVector().
◆ getSimpleVT()
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Return the SimpleValueType held in the specified simple EVT.
Definition at line 316 of file ValueTypes.h.
References assert(), and isSimple().
Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::HexagonTargetLowering::allowsMemoryAccess(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::HexagonTargetLowering::allowsMisalignedMemoryAccesses(), llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(), llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), analyzeCallOperands(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canonicalizeShuffleMaskWithHorizOp(), changeTypeToInteger(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineAnd(), combineAndMaskToShift(), combineArithReduction(), combineBitcastvxi1(), combineCONCAT_VECTORS(), combineConcatVectorOps(), combineExtractWithShuffle(), combineSCALAR_TO_VECTOR(), combineSelect(), llvm::VETargetLowering::combineSelectCC(), combineStore(), combineTargetShuffle(), combineToVCPOP(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), llvm::TargetLowering::createSelectForFMINNUM_FMAXNUM(), createVariablePermute(), llvm::SITargetLowering::denormalsEnabledForType(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::findOptimalMemOpLowering(), foldFCmpToFPClassTest(), foldReduceOperandViaVQDOT(), llvm::SelectionDAG::FoldSetCC(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::TargetLoweringBase::getAtomicLoadExtAction(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), getContainerForFixedLengthVector(), getExtensionTo64Bits(), getFltSemantics(), llvm::WebAssemblyTTIImpl::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::TargetLoweringBase::getLoadExtAction(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLoweringBase::getOperationAction(), getPackedSVEVectorVT(), llvm::TargetLoweringBase::getPartialReduceMLAAction(), llvm::HexagonTargetLowering::getPostIndexedAddressParts(), getPredicateForFixedLengthVector(), llvm::SPIRVTargetLowering::getPreferredSwitchConditionType(), llvm::FastISel::getRegForGEPIndex(), llvm::FastISel::getRegForValue(), llvm::TargetLoweringBase::getRegisterType(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), llvm::SDNode::getSimpleValueType(), llvm::SDValue::getSimpleValueType(), llvm::AArch64TTIImpl::getSpliceCost(), getSVEContainerType(), llvm::TargetLoweringBase::getTruncStoreAction(), llvm::TargetLoweringBase::getTypeConversion(), llvm::BasicTTIImplBase< BasicTTIImpl >::getTypeLegalizationCost(), llvm::SelectionDAG::getValueType(), getVectorLoweringShape(), getVectorTyFromPredicateVector(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SelectionDAG::getVTList(), is32Bit(), isAddSubOrSubAdd(), isConstantSplatVectorMaskForType(), isConstantSplatVectorMaskForType(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::TargetLoweringBase::isIndexedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedStoreLegal(), llvm::TargetLoweringBase::isIndexedStoreLegal(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::LoongArchTargetLowering::isShuffleMaskLegal(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), llvm::HexagonTargetLowering::isTruncateFree(), llvm::TargetLoweringBase::isTypeLegal(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidIndexedLoad(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), LowerADDSUBSAT(), LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), LowerFMINIMUM_FMAXIMUM(), llvm::SystemZTargetLowering::LowerFormalArguments(), lowerLaneOp(), llvm::HexagonTargetLowering::LowerLoad(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerStore(), llvm::VETargetLowering::lowerToVVP(), lowerVECTOR_COMPRESS(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), NarrowVector(), llvm::TargetLowering::ParseConstraints(), performBITCASTCombine(), performCONCAT_VECTORSCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformEXTRACTCombine(), performExtractLastActiveCombine(), performFP_TO_INTCombine(), performScatterStoreCombine(), performUADDVZextCombine(), performUzpCombine(), performVSelectCombine(), llvm::SITargetLowering::PostISelFolding(), recoverFramePointer(), ReplaceINTRINSIC_W_CHAIN(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::FastISel::selectBinaryOp(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectCast(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::FastISel::selectExtractValue(), llvm::FastISel::selectFNeg(), llvm::FastISel::selectFreeze(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), unpackFromRegLoc(), unpackFromRegLoc(), unpackFromRegLoc(), usePartialVectorLoads(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), llvm::SelectionDAGBuilder::visitBitTestHeader(), WidenVector(), X86ChooseCmpImmediateOpcode(), and X86ChooseCmpOpcode().
◆ getSizeInBits()
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inline |
Return the size of the specified value type in bits.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 373 of file ValueTypes.h.
References isSimple().
Referenced by AddRequiredExtensionForVMULL(), llvm::X86TargetLowering::allowsMemoryAccess(), llvm::SITargetLowering::allowsMisalignedMemoryAccesses(), allUsesTruncate(), llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), bitsEq(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), llvm::AArch64TargetLowering::canMergeStoresTo(), llvm::ARMTargetLowering::canMergeStoresTo(), llvm::R600TargetLowering::canMergeStoresTo(), llvm::SITargetLowering::canMergeStoresTo(), llvm::X86TargetLowering::canMergeStoresTo(), canonicalizeShuffleMaskWithHorizOp(), checkZExtBool(), clampDynamicVectorIndex(), collectConcatOps(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAnd(), combineArithReduction(), combineBasicSADPattern(), combineBEXTR(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBROADCAST_LOAD(), combineCMov(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineConstantPoolLoads(), combineDeMorganOfBoolean(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractFromVectorLoad(), combineExtractWithShuffle(), combineExtSetcc(), combinei64TruncSrlConstant(), combineLoad(), combineMinMaxReduction(), combineMulToPMADDWD(), combineMulWide(), combinePMULH(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAndUse(), combineSetCC(), combineShiftRightArithmetic(), combineShiftToPMULH(), combineSignExtendInReg(), combineStore(), combineSubShiftToOrcB(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncateWithSat(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVEXTRACT_STORE(), combineVPDPBUSDPattern(), combineX86ShufflesRecursively(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), concatSubVectors(), ConstantBuildVector(), constructDup(), constructRetValue(), convertIntLogicToFPLogic(), createPSADBW(), llvm::createUnpackShuffleMask(), llvm::LoongArchTargetLowering::decomposeMulByConstant(), llvm::RISCVTargetLowering::decomposeMulByConstant(), llvm::XtensaTargetLowering::decomposeMulByConstant(), EltsFromConsecutiveLoads(), emitFloatCompareMask(), emitVectorComparison(), Expand64BitShift(), expandDivFix(), expandMul(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), extractSubVector(), extractSubVector(), llvm::SwitchCG::SwitchLowering::findBitTestClusters(), findMemType(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantBuildVector(), foldExtendedSignBitTest(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandMultiply(), llvm::TargetLowering::forceExpandWideMUL(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), GenerateTBL(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), llvm::SelectionDAG::getElementCount(), getEVTString(), getEXTEND_VECTOR_INREG(), llvm::AArch64TTIImpl::getExtendedReductionCost(), llvm::ARMTTIImpl::getExtendedReductionCost(), getExtensionTo64Bits(), getExtFactor(), getFauxShuffleMask(), getFixedSizeInBits(), llvm::NVPTXDAGToDAGISel::getFromTypeWidthForLoad(), getHalfSizedIntegerVT(), getHorizDemandedElts(), getLeftShift(), getLoadStackGuard(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), llvm::WebAssemblyTTIImpl::getMemoryOpCost(), getMemsetStores(), getMemsetStringVal(), getMemsetValue(), llvm::ARMTTIImpl::getMulAccReductionCost(), llvm::SelectionDAG::getNeutralElement(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getNumRegisters(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), getOnesVector(), getPackDemandedElts(), getPredicateForFixedLengthVector(), llvm::X86TargetLowering::getPreferredSwitchConditionType(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(), getRoundIntegerType(), llvm::XtensaTargetLowering::getScalarShiftAmountTy(), getScalarSizeInBits(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), getStoreSize(), getTargetConstantBitsFromNode(), llvm::TargetLoweringBase::getTypeConversion(), llvm::AMDGPUTargetLowering::getTypeForExtReturn(), llvm::MipsTargetLowering::getTypeForExtReturn(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::SDNode::getValueSizeInBits(), llvm::SDValue::getValueSizeInBits(), getVectorBitwiseReduce(), llvm::X86TTIImpl::getVectorInstrCost(), getVectorLoweringShape(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SelectionDAG::getVScale(), llvm::X86TargetLowering::hasAndNot(), llvm::AArch64TargetLowering::hasPairedLoad(), llvm::TargetLowering::IncrementMemoryAddress(), INITIALIZE_PASS(), isBitfieldDstMask(), isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), isBitfieldPositioningOpFromAnd(), isByteSized(), isConcatMask(), isConsecutiveLSLoc(), llvm::BuildVectorSDNode::isConstantSplat(), IsElementEquivalent(), isExtendedFrom16Bits(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::SITargetLowering::isExtractVecEltCheap(), llvm::AArch64TargetLowering::isFPImmLegal(), llvm::HexagonSubtarget::isHVXVectorType(), isI24(), isLegalT2AddressImmediate(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::X86TargetLowering::isMemoryAccessFast(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::AMDGPUTargetLowering::isNarrowingProfitable(), isPackedVectorType(), isPerfectIncrement(), isRound(), isSaturatingMinMax(), llvm::AArch64TargetLowering::isShuffleMaskLegal(), llvm::AMDGPUTargetLowering::isTruncateFree(), llvm::ARMTargetLowering::isTruncateFree(), llvm::PPCTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::X86TargetLowering::isTruncateFree(), isUnpackedVectorVT(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidEGW(), isValidMtVsrBmi(), isVectorElementSwap(), isWideDUPMask(), isWorthFoldingIntoOrrWithShift(), isZeroSized(), llvm::AArch64TargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::SystemZTargetLowering::joinRegisterPartsIntoValue(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), lowerAddSubToHorizontalOp(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), lowerLaneOp(), llvm::MipsTargetLowering::lowerLOAD(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerSETCC(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::MipsTargetLowering::lowerSTORE(), lowerSTOREVector(), LowerSVEIntrinsicEXT(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), LowerVectorAllEqual(), lowerVectorSplatImm(), lowerX86CmpEqZeroToCtlzSrl(), llvm::ARMTargetLowering::LowerXConstraint(), MatchingStackOffset(), matchMergedBFX(), matchPMADDWD_2(), matchTruncateWithPACK(), MatchVectorAllEqualTest(), matchVPMADD52(), llvm::ARMTTIImpl::maybeLoweredToCall(), narrowExtractedVectorBinOp(), NormalizeBuildVector(), performANDCombine(), performANDCombine(), PerformARMBUILD_VECTORCombine(), performBITCASTCombine(), performBITREVERSECombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), PerformExtractFpToIntStores(), llvm::AMDGPUTargetLowering::performFNegCombine(), performGatherLoadCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performIntToFpCombine(), performLD1Combine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performScatterStoreCombine(), performSelectCombine(), performSETCC_BITCASTCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), performSRACombine(), performSRACombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performSVEAndCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUnpackCombine(), performVectorCompareAndMaskUnaryOpCombine(), performVectorDeinterleaveCombine(), performVectorExtCombine(), PerformVQDMULHCombine(), performVSelectCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceANDOfAtomicLoad(), reduceBuildVecToShuffleWithZero(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), resolveBuildVector(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::AMDGPUDAGToDAGISel::SelectBuildVector(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::FastISel::selectFNeg(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::LoongArchDAGToDAGISel::selectVSplatImm(), llvm::LoongArchDAGToDAGISel::selectVSplatUimmInvPow2(), llvm::LoongArchDAGToDAGISel::selectVSplatUimmPow2(), llvm::ARMTargetLowering::shouldExpandCmpUsingSelects(), llvm::SITargetLowering::shouldExpandVectorDynExt(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), shouldTransformMulToShiftsAddsSubs(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SplitOpsAndApply(), splitStores(), splitStoreSplat(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::SystemZTargetLowering::splitValueIntoRegisterParts(), splitVector(), takeInexpensiveLog2(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), transformAddImmMulImm(), transformAddShlImm(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), TryCombineBaseUpdate(), tryDemorganOfBooleanCondition(), TryMULWIDECombine(), tryToFoldExtendOfConstant(), tryToFoldExtOfAtomicLoad(), UnpackFromArgumentSlot(), unpackFromMemLoc(), unrollVectorShift(), llvm::AArch64SelectionDAGInfo::verifyTargetNode(), llvm::SelectionDAGBuilder::visitBitTestHeader(), widenBuildVec(), widenIntegerVectorElementType(), and widenVec().
◆ getStoreSize()
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inline |
Return the number of bytes overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 395 of file ValueTypes.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Referenced by llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses(), llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::X86TargetLowering::BuildFILD(), calculateSrcByte(), CalculateStackSlotAlignment(), CalculateStackSlotSize(), canMergeParamLoadStoresStartingAt(), combineStore(), llvm::SelectionDAG::CreateStackTemporary(), llvm::SelectionDAG::CreateStackTemporary(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), findConsecutiveLoad(), getBROADCAST_LOAD(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getLoadVP(), llvm::SelectionDAG::getMemIntrinsicNode(), getParamsForOneTrueMaskedElt(), getScalarStoreSize(), llvm::SelectionDAG::getStore(), getStoreSizeInBits(), llvm::PPCTargetLowering::getTgtMemIntrinsic(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getTruncStoreVP(), getVPermMask(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(), llvm::RISCVTTIImpl::isLegalMaskedLoadStore(), llvm::RISCVTargetLowering::isLegalStridedLoadStore(), isOnlyUsedByStores(), llvm::AMDGPUTargetLowering::loadStackInputValue(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::MemSDNode::MemSDNode(), narrowExtractedVectorLoad(), llvm::SITargetLowering::passSpecialInputs(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), ShrinkLoadReplaceStoreWithStore(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), splitVectorStore(), unpackFromMemLoc(), and unpackFromMemLoc().
◆ getStoreSizeInBits()
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inline |
Return the number of bits overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 412 of file ValueTypes.h.
References getStoreSize().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), EltsFromConsecutiveLoads(), llvm::AMDGPUTargetLowering::getEquivalentMemType(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::AMDGPUTargetLowering::shouldReduceLoadWidth(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().
◆ getTypeForEVT()
| Type * EVT::getTypeForEVT | ( | LLVMContext & | Context | ) | const |
This method returns an LLVM type corresponding to the specified EVT.
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
For integer types, this returns an unsigned type. Note that this will abort for types that cannot be represented.
Definition at line 218 of file ValueTypes.cpp.
References assert(), llvm::FixedVectorType::get(), llvm::IntegerType::get(), llvm::TargetExtType::get(), llvm::Type::getMetadataTy(), llvm::Type::getVoidTy(), llvm::Type::getWasm_ExternrefTy(), llvm::Type::getWasm_FuncrefTy(), llvm::Type::getX86_AMXTy(), and isExtended().
Referenced by llvm::TargetLoweringBase::allowsMemoryAccessForAlignment(), llvm::analyzeArguments(), canFoldInAddressingMode(), combineTargetShuffle(), llvm::SelectionDAG::CreateStackTemporary(), llvm::SelectionDAG::CreateStackTemporary(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::SelectionDAG::expandMultipleResultFPLibCall(), llvm::SelectionDAG::expandVAArg(), llvm::TargetLowering::expandVectorFindLastActive(), finishStackBlock(), llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::AArch64TTIImpl::getArithmeticReductionCostSVE(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::RISCVTTIImpl::getCastInstrCost(), getConstantVector(), getDivRemArgList(), llvm::SelectionDAG::getEVTAlign(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getMemsetStores(), getMemsetStringVal(), llvm::AArch64TTIImpl::getMinMaxReductionCost(), llvm::BasicTTIImplBase< BasicTTIImpl >::getNumberOfParts(), getPrefTypeAlign(), getPrefTypeAlign(), llvm::SelectionDAG::getReducedAlign(), llvm::CCState::getRemainingRegParmsForType(), llvm::CallLowering::getReturnInfo(), llvm::AArch64TTIImpl::getSpliceCost(), llvm::PPCTargetLowering::isFMAFasterThanFMulAndFAdd(), isSaturatingMinMax(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), LowerFSINCOS(), llvm::AArch64CallLowering::lowerReturn(), lowerSTOREVector(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), llvm::PPCTargetLowering::PerformDAGCombine(), replaceLoadVector(), and llvm::SITargetLowering::ReplaceNodeResults().
◆ getVectorElementCount()
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inline |
Definition at line 350 of file ValueTypes.h.
References assert(), isSimple(), and isVector().
Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineAdd(), combineBinOpOfZExt(), combineConcatVectorOfCasts(), combineConcatVectorOps(), combineShiftToAVG(), combineVectorMulToSraBitcast(), createPSADBW(), earlyExpandDIVFIX(), expandDivFix(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMULO(), llvm::SelectionDAG::expandMultipleResultFPLibCall(), llvm::TargetLowering::expandPartialReduceMLA(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVectorNaryOpBySplitting(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPCTTZElements(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtendVectorInregToExtendOfSubvector(), foldReduceOperandViaVQDOT(), getCopyFromPartsVector(), getCopyToPartsVector(), llvm::SelectionDAG::GetDependentSplitDestVTs(), getDoubleNumVectorElementsVT(), getEVTString(), getHalfNumVectorElementsVT(), llvm::BasicTTIImplBase< BasicTTIImpl >::getIntrinsicInstrCost(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::AArch64TargetLowering::getNumRegistersForCallingConv(), getPackedVectorTypeFromPredicateType(), getPow2VectorType(), llvm::AArch64TargetLowering::getRegisterTypeForCallingConv(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::X86TargetLowering::getSetCCResultType(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::TargetLoweringBase::getTypeConversion(), getVectorMinNumElements(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::SelectionDAG::getVPZeroExtendInReg(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::TargetLowering::IncrementMemoryAddress(), performActiveLaneMaskCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performLastTrueTestVectorCombine(), PerformMinMaxFpToSatCombine(), performMulVectorCmpZeroCombine(), PerformUMinFpToSatCombine(), performVectorExtCombine(), performVSelectCombine(), PromoteBinOpToF32(), reverseZExtICmpCombine(), setInfoSVEStN(), llvm::TargetLowering::SimplifyDemandedBits(), skipExtensionForVectorMULL(), llvm::SelectionDAG::SplitEVL(), llvm::AArch64SelectionDAGInfo::verifyTargetNode(), llvm::RISCVSelectionDAGInfo::verifyTargetNode(), widenIntegerVectorElementType(), and widenVectorToPartType().
◆ getVectorElementType()
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inline |
Given a vector type, return the type of each element.
Definition at line 328 of file ValueTypes.h.
References assert(), EVT(), isSimple(), and isVector().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineVUZPToVPADDL(), adjustLoadValueTypeImpl(), llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(), CollectOpsToWiden(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBitcast(), combineBitcastvxi1(), combineCastedMaskArithmetic(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOps(), combineExtractFromVectorLoad(), combineExtractWithShuffle(), combineExtSetcc(), combineFP_EXTEND(), combineFP_ROUND(), combineGatherScatter(), combineMulToPMADDWD(), combineMulToPMULDQ(), combinePMULH(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSetCC(), combineShiftToMULH(), combineShiftToPMULH(), combineSIntToFP(), combineStore(), combineTruncateWithSat(), combineUIntToFP(), combineVSelectToBLENDV(), combinevXi1ConstantToInteger(), combineX86ShufflesRecursively(), combineXor(), CompactSwizzlableVector(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), constructRetValue(), detectPMADDUBSW(), expandDivFix(), llvm::TargetLowering::expandPartialReduceMLA(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVectorSplice(), extractSubVector(), extractSubVector(), llvm::SelectionDAG::ExtractVectorElements(), findMemType(), findMoreOptimalIndexType(), llvm::SelectionDAG::FoldConstantBuildVector(), foldIndexIntoBase(), foldReduceOperandViaVQDOT(), foldVectorXorShiftIntoCmp(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), llvm::ARMTTIImpl::getArithmeticReductionCost(), getContainerForFixedLengthVector(), getCopyFromPartsVector(), getCopyToPartsVector(), llvm::SelectionDAG::GetDependentSplitDestVTs(), getDoubleNumVectorElementsVT(), getEVTString(), getExtFactor(), getHalfNumVectorElementsVT(), getInvertedVectorForFMA(), getKnownUndefForVectorBinop(), llvm::AArch64TTIImpl::getMemoryOpCost(), getMemVTFromNode(), llvm::ARMTTIImpl::getMinMaxReductionCost(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), getOneTrueElt(), getPackedVectorTypeFromPredicateType(), getParamsForOneTrueMaskedElt(), getPow2VectorType(), getPredicateForFixedLengthVector(), getPredicateRegisterClass(), getPromotedVTForPredicate(), llvm::HexagonTargetLowering::getRegisterTypeForCallingConv(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), getScalarType(), getShuffleScalarElt(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getSplatVector(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::SelectionDAG::getStepVector(), getSVEPredicateBitCast(), llvm::TargetLoweringBase::getTypeConversion(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorBitwiseReduce(), llvm::TargetLowering::getVectorElementPointer(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::HexagonTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), getVPermMask(), getZeroPaddedAdd(), llvm::HexagonTargetLowering::handleMaskRegisterForCallingConv(), INITIALIZE_PASS(), isConstantSplatVectorMaskForType(), llvm::RISCVTargetLowering::isCtpopFast(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::SITargetLowering::isExtractVecEltCheap(), isFNEG(), llvm::X86TargetLowering::isLoadBitCastBeneficial(), llvm::isMaskType(), llvm::NVPTX::isPackedElementTy(), llvm::X86TargetLowering::isTargetCanonicalSelect(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::X86TargetLowering::isTypeDesirableForOp(), isValidSplatLoad(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), legalizeScatterGatherIndexType(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), LowerCTTZ(), llvm::R600TargetLowering::LowerFormalArguments(), lowerLaneOp(), lowerMSACopyIntr(), LowerMULO(), llvm::AArch64TargetLowering::LowerOperation(), lowerScalarInsert(), LowerStore(), lowerSTOREVector(), LowerSVEIntrinsicEXT(), LowerTcgen05St(), LowerVecReduce(), LowerVecReduceMinMax(), lowerVECTOR_COMPRESS(), lowerVECTOR_SHUFFLE_VSHF(), LowerVectorINT_TO_FP(), LowerVectorMatch(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), matchPMADDWD(), matchPMADDWD_2(), matchTruncateWithPACK(), narrowIndex(), NarrowVector(), NormalizeBuildVector(), performAddUADDVCombine(), PerformARMBUILD_VECTORCombine(), performBitcastCombine(), PerformBUILD_VECTORCombine(), performBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performDupLane128Combine(), PerformEXTRACTCombine(), performExtractLastActiveCombine(), performExtractSubvectorCombine(), performFirstTrueTestVectorCombine(), performFPExtendCombine(), performGLD1Combine(), performINSERT_VECTOR_ELTCombine(), PerformInsertEltCombine(), performLastTrueTestVectorCombine(), performPostLD1Combine(), performScatterStoreCombine(), performSETCC_BITCASTCombine(), performSETCCCombine(), performSETCCCombine(), performSignExtendInRegCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), performSVEAndCombine(), performTruncateCombine(), performUnpackCombine(), PerformVDUPLANECombine(), performVecReduceAddCombine(), performVecReduceBitwiseCombine(), performVP_REVERSECombine(), performVP_STORECombine(), performVSelectCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), ReorganizeVector(), replaceBoolVectorBitcast(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceVPICKVE2GRResults(), replaceZeroVectorStore(), scalarizeBinOpOfSplats(), scalarizeExtractedBinOp(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::AMDGPUDAGToDAGISel::SelectBuildVector(), SelectOpcodeFromVT(), llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle(), llvm::RISCVTargetLowering::shouldExpandCttzElements(), llvm::AArch64TargetLowering::shouldExpandGetActiveLaneMask(), llvm::SITargetLowering::shouldExpandVectorDynExt(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), truncateAVX512SetCCNoBWI(), TryCombineBaseUpdate(), tryFormConcatFromShuffle(), TryWideExtMulCombine(), tryWidenMaskForShuffle(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAG::UnrollVectorOverflowOp(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), llvm::RISCVSelectionDAGInfo::verifyTargetNode(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::X86TargetLowering::visitMaskedStore(), widenIntegerVectorElementType(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), llvm::SelectionDAG::WidenVector(), WidenVector(), and widenVectorToPartType().
◆ getVectorMinNumElements()
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inline |
Given a vector type, return the minimum number of elements it contains.
Definition at line 359 of file ValueTypes.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), and getVectorElementCount().
Referenced by llvm::SelectionDAG::canCreateUndefOrPoison(), clampDynamicVectorIndex(), combineBitcastvxi1(), llvm::TargetLowering::expandPartialReduceMLA(), llvm::TargetLowering::expandVectorSplice(), findMoreOptimalIndexType(), foldConcatVector(), getCopyToPartsVector(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), getPromotedVTForPredicate(), getSubVectorSrc(), getZeroPaddedAdd(), llvm::isConstOrConstSplat(), llvm::isConstOrConstSplatFP(), llvm::AArch64TargetLowering::isExtractSubvectorCheap(), isPow2VectorType(), lowerShuffleViaVRegSplitting(), narrowExtractedVectorLoad(), performBuildVectorCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performUzpCombine(), PerformVECREDUCE_ADDCombine(), performVectorDeinterleaveCombine(), SelectOpcodeFromVT(), llvm::AArch64TargetLowering::shouldExpandGetActiveLaneMask(), llvm::SelectionDAG::SplitEVL(), and llvm::SelectionDAG::SplitVector().
◆ getVectorNumElements()
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inline |
Given a vector type, return the number of elements it contains.
Definition at line 336 of file ValueTypes.h.
References assert(), isScalableVector(), isSimple(), isVector(), and llvm::reportFatalInternalError().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), buildScalarToVector(), canCombineShuffleToExtendVectorInreg(), llvm::SelectionDAG::canCreateUndefOrPoison(), canonicalizeShuffleMaskWithHorizOp(), collectConcatOps(), CollectOpsToWiden(), combineAddOfPMADDWD(), combineAnd(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBitcast(), combineBitcastvxi1(), combineBITREVERSE(), combineCMP(), combineConcatVectorOfExtracts(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFP_EXTEND(), combineFP_ROUND(), combineKSHIFT(), combineLoad(), combineMaskedLoadConstantMask(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineOr(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSetCCMOVMSK(), combineShuffle(), combineShuffleOfBitcast(), combineShuffleOfScalars(), combineShuffleOfSplatVal(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToConsecutiveLoads(), combineToExtendBoolVectorInReg(), combineTruncateWithSat(), combineTruncationShuffle(), combineUIntToFP(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combinevXi1ConstantToInteger(), combineX86INT_TO_FP(), combineX86ShufflesRecursively(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SelectionDAG::computeVectorKnownZeroElements(), concatSubVectors(), constructDup(), constructRetValue(), ConvertSelectToConcatVector(), createBSWAPShuffleMask(), createShuffleMaskFromVSELECT(), llvm::createUnpackShuffleMask(), createVariablePermute(), detectEvenOddMultiplyOperand(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), llvm::TargetLowering::expandVECTOR_COMPRESS(), ExtractBitFromMaskVector(), extractSubVector(), extractSubVector(), llvm::SelectionDAG::ExtractVectorElements(), FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantBuildVector(), foldExtractSubvectorFromShuffleVector(), foldShuffleOfConcatUndefs(), foldToMaskedStore(), GenerateFixedLengthSVETBL(), getBuildVectorSplat(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::SelectionDAG::getConstant(), getConstantLaneNumOfExtractHalfOperand(), getCopyFromPartsVector(), getDemandedSrcElements(), getEXTEND_VECTOR_INREG(), getExtractVectorizedValue(), getFauxShuffleMask(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getKnownUndefForVectorBinop(), llvm::ShuffleVectorSDNode::getMask(), llvm::VECustomDAG::getMaskBroadcast(), llvm::AArch64TTIImpl::getMemoryOpCost(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), getOneTrueElt(), getPredicateForFixedLengthVector(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::HexagonTargetLowering::getSetCCResultType(), llvm::NVPTXTargetLowering::getSetCCResultType(), llvm::SITargetLowering::getSetCCResultType(), getShuffleScalarElt(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getSplatSourceVector(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::SelectionDAG::getStepVector(), getSToVPermuted(), getTargetShuffleAndZeroables(), llvm::SelectionDAG::getValidMaximumShiftAmount(), llvm::SelectionDAG::getValidMinimumShiftAmount(), llvm::SelectionDAG::getValidShiftAmount(), getVectorBitwiseReduce(), getVectorizedVT(), llvm::SelectionDAG::getVectorShuffle(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::HexagonTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), getVPermMask(), llvm::HexagonTargetLowering::handleMaskRegisterForCallingConv(), isAllConstantBuildVector(), isConcatMask(), IsElementEquivalent(), isEXTMask(), llvm::ARMTargetLowering::isExtractSubvectorCheap(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), isHorizontalBinOpPart(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::SelectionDAG::isKnownNeverNaN(), isLegalBitRotate(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::isPackedVectorType(), isReverseMask(), llvm::AArch64TargetLowering::isShuffleMaskLegal(), llvm::ARMTargetLowering::isShuffleMaskLegal(), isSingletonEXTMask(), isSingletonVEXTMask(), llvm::SelectionDAG::isSplatValue(), llvm::SelectionDAG::isSplatValue(), isTargetShuffleEquivalent(), isTRN_v_undef_Mask(), isTruncMask(), isUZP_v_undef_Mask(), isVectorElementSwap(), isVEXTMask(), isVMOVNMask(), isVMOVNTruncMask(), isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), isWideDUPMask(), isZIP_v_undef_Mask(), lowerAddSubToHorizontalOp(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORToVIDUP(), LowerCONCAT_VECTORS_i1(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), lowerLaneOp(), lowerMSASplatZExt(), LowerPredicateStore(), LowerReverse_VECTOR_SHUFFLE(), LowerStore(), lowerSTOREVector(), LowerTcgen05St(), llvm::VETargetLowering::lowerToVVP(), LowerVecReduce(), LowerVecReduceMinMax(), lowerVECTOR_COMPRESS(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_VSHF(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(), matchBinaryShuffle(), llvm::SelectionDAG::matchBinOpReduction(), matchIndexAsShuffle(), matchIndexAsWiderOp(), matchPMADDWD(), matchPMADDWD_2(), matchScalarReduction(), mergeEltWithShuffle(), narrowExtractedVectorBinOp(), NarrowVector(), partitionShuffleOfConcats(), llvm::peekThroughInsertVectorElt(), PerformARMBUILD_VECTORCombine(), performBITCASTCombine(), performBitcastCombine(), PerformBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performBUILD_VECTORCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performINSERT_VECTOR_ELTCombine(), PerformInsertEltCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), performSelectCombine(), performSETCC_BITCASTCombine(), performSETCCCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVAddCombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), PerformVQDMULHCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), performZExtDeinterleaveShuffleCombine(), performZExtUZPCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), reduceVMULWidth(), ReplaceAddWithADDP(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), ReplaceTcgen05Ld(), replaceZeroVectorStore(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::AMDGPUDAGToDAGISel::SelectBuildVector(), llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle(), llvm::AArch64TargetLowering::shouldExpandGetActiveLaneMask(), llvm::SITargetLowering::shouldExpandVectorDynExt(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), SkipExtensionForVMULL(), SplitOpsAndApply(), splitStores(), llvm::AMDGPUTargetLowering::splitVector(), splitVector(), splitVectorIntUnary(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryBuildVectorShuffle(), TryCombineBaseUpdate(), tryCombineMULLWithUZP1(), tryLowerToBSL(), trySQDMULHCombine(), tryToFoldExtendOfConstant(), TryWideExtMulCombine(), tryWidenMaskForShuffle(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAG::UnrollVectorOverflowOp(), widenBuildVec(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenSubVector(), widenVec(), llvm::SelectionDAG::WidenVector(), and WidenVector().
◆ getVectorVT() [1/2]
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inlinestatic |
Returns the EVT that represents a vector EC.Min elements in length, where each element is of type VT.
Definition at line 84 of file ValueTypes.h.
References EVT(), llvm::MVT::getVectorVT(), and llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.
◆ getVectorVT() [2/2]
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inlinestatic |
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition at line 74 of file ValueTypes.h.
References EVT(), llvm::MVT::getVectorVT(), and llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.
Referenced by AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), canCombineShuffleToExtendVectorInreg(), CollectOpsToWiden(), combineAdd(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBitcastToBoolVector(), combineConcatVectorOfCasts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractWithShuffle(), combineFP_EXTEND(), combineFP_ROUND(), combineLoad(), combinePMULH(), combineShiftToAVG(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncateWithSat(), combineUIntToFP(), combineVectorMulToSraBitcast(), combineVectorSizedSetCCEquality(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), concatSubVectors(), constructRetValue(), convertIntLogicToFPLogic(), createPSADBW(), detectPMADDUBSW(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), emitFloatCompareMask(), emitVectorComparison(), expandDivFix(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandPartialReduceMLA(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPCTTZElements(), extractSubVector(), extractSubVector(), llvm::SelectionDAG::FoldConstantBuildVector(), foldExtendVectorInregToExtendOfSubvector(), foldShuffleOfConcatUndefs(), GenerateFixedLengthSVETBL(), llvm::getApproximateEVTForLLT(), getBuildVectorizedValue(), llvm::SelectionDAG::getConstant(), getCopyFromPartsVector(), getCopyToPartsVector(), llvm::SelectionDAG::GetDependentSplitDestVTs(), getDoubleNumVectorElementsVT(), llvm::AMDGPUTargetLowering::getEquivalentMemType(), getEVT(), getHalfNumVectorElementsVT(), llvm::AArch64TTIImpl::getMemoryOpCost(), getMemsetStores(), llvm::TargetLoweringBase::getMemValueType(), getPackedVectorTypeFromPredicateType(), getPow2VectorType(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::HexagonTargetLowering::getSetCCResultType(), llvm::NVPTXTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::SITargetLowering::getSetCCResultType(), llvm::X86TargetLowering::getSetCCResultType(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::TargetLoweringBase::getValueType(), llvm::TargetLowering::getVectorElementPointer(), getVectorizedVT(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::VECustomDAG::getVectorVT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), LowerAsSplatVectorLoad(), lowerBitreverseShuffle(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SITargetLowering::LowerFormalArguments(), lowerLaneOp(), llvm::RISCVTargetLowering::LowerOperation(), LowerSVEIntrinsicEXT(), LowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVSETCC(), llvm::SelectionDAG::matchBinOpReduction(), matchPMADDWD(), matchPMADDWD_2(), memVTFromLoadIntrData(), narrowExtractedVectorBinOp(), PerformARMBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformInsertEltCombine(), PerformMinMaxFpToSatCombine(), performMulVectorCmpZeroCombine(), performSelectCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), performVecReduceAddCombine(), performVECTOR_SHUFFLECombine(), performVectorExtCombine(), PromoteBinOpToF32(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), reverseZExtICmpCombine(), setInfoSVEStN(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), skipExtensionForVectorMULL(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAG::UnrollVectorOverflowOp(), widenIntegerVectorElementType(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), and llvm::SelectionDAG::WidenVector().
◆ is1024BitVector()
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inline |
Return true if this is a 1024-bit vector type.
Definition at line 222 of file ValueTypes.h.
References isSimple().
◆ is128BitVector()
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inline |
Return true if this is a 128-bit vector type.
Definition at line 207 of file ValueTypes.h.
References isSimple().
Referenced by AddCombineVUZPToVPADDL(), AddRequiredExtensionForVMULL(), combineAndShuffleNot(), combineBitcast(), combineConcatVectorOps(), combineConstantPoolLoads(), combineHorizOpWithShuffle(), combineLoad(), combineLogicBlendIntoPBLENDV(), combinePTESTCC(), combineStore(), combineToExtendBoolVectorInReg(), combineVectorPack(), combineVSelectToBLENDV(), constructDup(), EltsFromConsecutiveLoads(), getOnesVector(), getTargetVShiftNode(), getVectorShuffleOpcode(), getVShift(), getZeroVector(), INITIALIZE_PASS(), insert128BitVector(), isLegalMaskCompare(), llvm::AArch64TargetLowering::isShuffleMaskLegal(), llvm::ARMTargetLowering::isShuffleMaskLegal(), isVMOVModifiedImm(), LowerMUL(), LowerVecReduceMinMax(), LowerVectorMatch(), performANDCombine(), performConcatVectorsCombine(), performDupLane128Combine(), PerformMULCombine(), PerformORCombine(), performPostLD1Combine(), performTruncateCombine(), PerformVECREDUCE_ADDCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), skipExtensionForVectorMULL(), supportedVectorShiftWithImm(), supportedVectorVarShift(), truncateVectorWithNARROW(), truncateVectorWithPACK(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), and widenBuildVec().
◆ is16BitVector()
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inline |
Return true if this is a 16-bit vector type.
Definition at line 192 of file ValueTypes.h.
References isSimple().
◆ is2048BitVector()
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Return true if this is a 2048-bit vector type.
Definition at line 227 of file ValueTypes.h.
References isSimple().
◆ is256BitVector()
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inline |
Return true if this is a 256-bit vector type.
Definition at line 212 of file ValueTypes.h.
References isSimple().
Referenced by combineAndShuffleNot(), combineConcatVectorOps(), combineConstantPoolLoads(), combineEXTRACT_SUBVECTOR(), combineHorizOpWithShuffle(), combineLoad(), combineLogicBlendIntoPBLENDV(), combinePMULH(), combineStore(), EltsFromConsecutiveLoads(), extract128BitVector(), getOnesVector(), INITIALIZE_PASS(), isHorizontalBinOpPart(), isLegalMaskCompare(), narrowShuffle(), narrowVectorSelect(), performEXTRACT_VECTOR_ELTCombine(), PromoteMaskArithmetic(), ReplaceAddWithADDP(), llvm::X86TargetLowering::shouldReduceLoadWidth(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitVectorIntBinary(), splitVectorIntUnary(), splitVectorStore(), supportedVectorShiftWithImm(), supportedVectorVarShift(), truncateVectorWithNARROW(), truncateVectorWithPACK(), and widenSubVector().
◆ is32BitVector()
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inline |
Return true if this is a 32-bit vector type.
Definition at line 197 of file ValueTypes.h.
References isSimple().
Referenced by PerformBUILD_VECTORCombine().
◆ is512BitVector()
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Return true if this is a 512-bit vector type.
Definition at line 217 of file ValueTypes.h.
References isSimple().
Referenced by combineAnd(), combineAndShuffleNot(), combineConcatVectorOps(), combineScalarAndWithMaskSetcc(), combineStore(), combineTruncateWithSat(), combineVSelectToBLENDV(), EltsFromConsecutiveLoads(), extract128BitVector(), extract256BitVector(), getOnesVector(), LowerVectorAllEqual(), narrowShuffle(), llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::X86TargetLowering::shouldReduceLoadWidth(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitVectorIntBinary(), splitVectorIntUnary(), splitVectorStore(), supportedVectorShiftWithImm(), supportedVectorVarShift(), and truncateVectorWithPACK().
◆ is64BitVector()
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Return true if this is a 64-bit vector type.
Definition at line 202 of file ValueTypes.h.
References isSimple().
Referenced by AddCombineVUZPToVPADDL(), combineVectorPack(), CombineVLDDUP(), getVectorShuffleOpcode(), llvm::AArch64TargetLowering::isShuffleMaskLegal(), llvm::ARMTargetLowering::isShuffleMaskLegal(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), LowerCTPOP(), LowerMUL(), performANDCombine(), performDUPCombine(), PerformMULCombine(), performPostLD1Combine(), performTruncateCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), and llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().
◆ isByteSized()
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Return true if the bit size is a multiple of 8.
Definition at line 243 of file ValueTypes.h.
References getSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf(), and isZeroSized().
Referenced by calculateSrcByte(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), getFauxShuffleMask(), llvm::TargetLoweringBase::isPaddedAtMostSignificantBitsWhenStored(), matchPERM(), narrowExtractedVectorLoad(), performVP_REVERSECombine(), performVP_STORECombine(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), and llvm::AMDGPUTargetLowering::shouldCombineMemoryType().
◆ isCheriCapability()
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Return true if this is a capability type.
Definition at line 232 of file ValueTypes.h.
References isSimple().
Referenced by getEVTString().
◆ isExtended()
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Test if the given EVT is extended (as opposed to being simple).
Definition at line 142 of file ValueTypes.h.
References isSimple().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLoweringBase::getAtomicLoadExtAction(), llvm::TargetLoweringBase::getLoadExtAction(), llvm::TargetLoweringBase::getOperationAction(), llvm::TargetLoweringBase::getTruncStoreAction(), getTypeForEVT(), llvm::SelectionDAG::getValueType(), llvm::SelectionDAG::getVTList(), and llvm::PPCTargetLowering::PerformDAGCombine().
◆ isFixedLengthVector()
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Definition at line 181 of file ValueTypes.h.
References isSimple().
Referenced by llvm::SelectionDAG::canCreateUndefOrPoison(), llvm::AArch64TargetLowering::canMergeStoresTo(), clampDynamicVectorIndex(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), convertFromScalableVector(), convertFromScalableVector(), findMoreOptimalIndexType(), llvm::SelectionDAG::FoldConstantArithmetic(), foldExtractSubvectorFromShuffleVector(), llvm::AArch64TTIImpl::getCastInstrCost(), getConstantLaneNumOfExtractHalfOperand(), getContainerForFixedLengthVector(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::AArch64TargetLowering::getNumRegistersForCallingConv(), getPredicateForFixedLengthVector(), getPredicateForVector(), llvm::AArch64TargetLowering::getRegisterTypeForCallingConv(), llvm::SelectionDAG::getValidMaximumShiftAmount(), llvm::SelectionDAG::getValidMinimumShiftAmount(), llvm::SelectionDAG::getValidShiftAmount(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorBitwiseReduce(), llvm::isConstOrConstSplat(), llvm::isConstOrConstSplatFP(), llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(), llvm::RISCVTTIImpl::isLegalMaskedLoadStore(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), isPackedVectorType(), isPassedInFPR(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::RISCVTargetLowering::LowerOperation(), narrowExtractedVectorBinOp(), llvm::peekThroughInsertVectorElt(), performBitcastCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performFP_TO_INTCombine(), performFPExtendCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performSETCCCombine(), performSETCCCombine(), performTruncateCombine(), performVecReduceBitwiseCombine(), performVectorExtCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::AArch64TargetLowering::shouldExpandCmpUsingSelects(), llvm::AArch64TargetLowering::shouldExpandGetActiveLaneMask(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::SelectionDAG::SplitEVL(), splitStores(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryToFoldExtOfLoad(), llvm::AArch64Subtarget::useSVEForFixedLengthVectors(), and llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().
◆ isFloatingPoint()
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Return true if this is a FP or a vector FP type.
Definition at line 147 of file ValueTypes.h.
References isSimple().
Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), combineBitcast(), combineBitcastToBoolVector(), combineBitOpWithMOVMSK(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractWithShuffle(), combineHorizOpWithShuffle(), combineSelect(), llvm::VETargetLowering::combineSelect(), llvm::VETargetLowering::combineSelectCC(), combineVSelectWithAllOnesOrZeros(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), decideComp(), EltsFromConsecutiveLoads(), emitComparison(), llvm::AArch64TargetLowering::enableAggressiveFMAFusion(), llvm::PPCTargetLowering::enableAggressiveFMAFusion(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::findOptimalMemOpLowering(), foldAndOrOfSETCC(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantBuildVector(), llvm::SelectionDAG::FoldSetCC(), llvm::SelectionDAG::getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getEVTString(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), getPredicateForSetCC(), llvm::XtensaTargetLowering::getRegisterTypeForCallingConv(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::AArch64TargetLowering::hasPairedLoad(), llvm::AMDGPUTargetLowering::isFAbsFree(), llvm::TargetLoweringBase::isFAbsFree(), llvm::AMDGPUTargetLowering::isFNegFree(), llvm::TargetLoweringBase::isFNegFree(), llvm::TargetLoweringBase::isFPExtFoldable(), llvm::PPCTargetLowering::isFPExtFree(), llvm::TargetLoweringBase::isFPExtFree(), isLegalT2AddressImmediate(), isLegalToCombineMinNumMaxNum(), isMImm(), llvm::RISCVTargetLowering::isMultiStoresCheaperThanBitsMerge(), llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge(), isPassedInFPR(), isSimm7(), isSupportedType(), llvm::ConstantFPSDNode::isValueValidForType(), lowerLaneOp(), LowerVectorAllEqual(), LowerVSETCC(), llvm::ARMTargetLowering::LowerXConstraint(), llvm::TargetLowering::LowerXConstraint(), llvm::X86TargetLowering::LowerXConstraint(), llvm::ARMTTIImpl::maybeLoweredToCall(), NormalizeBuildVector(), llvm::RISCVTargetLowering::PerformDAGCombine(), performGatherLoadCombine(), performLD1ReplicateCombine(), performLDNT1Combine(), performScatterStoreCombine(), performSelectCombine(), performST1Combine(), performSTNT1Combine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformVCMPCombine(), performVECTOR_SHUFFLECombine(), performVSelectCombine(), llvm::X86TargetLowering::reduceSelectOfFPConstantLoads(), ReplaceAddWithADDP(), replaceSplatVectorStore(), safeWithoutCompWithNull(), llvm::TargetLowering::SimplifyDemandedBits(), and tryWidenMaskForShuffle().
◆ isInteger()
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Return true if this is an integer or a vector integer type.
Definition at line 152 of file ValueTypes.h.
References isSimple().
Referenced by AddCombineBUILD_VECTORToVPADDL(), canCombineShuffleToExtendVectorInreg(), combineAddOrSubToADCOrSBB(), combineAndMaskToShift(), combineBinOpOfExtractToReduceTree(), combineBitcast(), combineBITREVERSE(), combineCarryThroughADD(), combineConcatVectorOfScalars(), combineExtractFromVectorLoad(), combineExtractVectorElt(), combineExtractWithShuffle(), combineExtSetcc(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMul(), combineSelect(), combineSetCC(), combineShiftLeft(), combineShuffleOfScalars(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineSubOfBoolean(), combineTruncationShuffle(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), convertValVTToLocVT(), correctParamType(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::findOptimalMemOpLowering(), foldAndOrOfSETCC(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantBuildVector(), llvm::SelectionDAG::FoldSetCC(), llvm::SelectionDAG::getAssertAlign(), llvm::SelectionDAG::getConstant(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getEVTString(), getHalfSizedIntegerVT(), llvm::SelectionDAG::getLoad(), getMemcpyLoadsAndStores(), getMemsetStringVal(), getMemsetValue(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getNumRegisters(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::TargetLoweringBase::getRegisterType(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::GetReturnInfo(), getRoundIntegerType(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::TargetLoweringBase::getTypeConversion(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SelectionDAG::getVPZeroExtendInReg(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::AArch64TargetLowering::hasPairedLoad(), llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(), isLegalT2AddressImmediate(), isMImm(), llvm::RISCVTargetLowering::isMultiStoresCheaperThanBitsMerge(), llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge(), llvm::AMDGPUTargetLowering::isNarrowingProfitable(), isSimm7(), llvm::SelectionDAG::isSplatValue(), isSupportedType(), llvm::AArch64TargetLowering::isTruncateFree(), llvm::ARMTargetLowering::isTruncateFree(), llvm::MSP430TargetLowering::isTruncateFree(), llvm::PPCTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::SystemZTargetLowering::isTruncateFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lowerBuildVectorAsBroadcast(), LowerMUL(), llvm::TargetLowering::LowerXConstraint(), llvm::ARMTTIImpl::maybeLoweredToCall(), OptimizeNoopCopyExpression(), llvm::ARMTargetLowering::PerformCMOVCombine(), performExtractVectorEltCombine(), performGatherLoadCombine(), performInsertSubvectorCombine(), performLD1Combine(), performSELECTCombine(), performSETCCCombine(), performSignExtendSetCCCombine(), llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::TargetLowering::softenSetCCOperands(), splitVSETCC(), takeInexpensiveLog2(), and llvm::AArch64SelectionDAGInfo::verifyTargetNode().
◆ isOverloaded()
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Return true if this is an overloaded type for TableGen.
Definition at line 237 of file ValueTypes.h.
◆ isPow2VectorType()
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Returns true if the given vector is a power of 2.
Definition at line 470 of file ValueTypes.h.
References getVectorMinNumElements().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::expandVecReduce(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), getPow2VectorType(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::TargetLoweringBase::getTypeConversion(), getVectorBitwiseReduce(), llvm::HexagonTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::HexagonTargetLowering::handleMaskRegisterForCallingConv(), performVecReduceBitwiseCombine(), PerformVQDMULHCombine(), trySQDMULHCombine(), and llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().
◆ isRISCVVectorTuple()
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Return true if this is a vector value type.
Definition at line 179 of file ValueTypes.h.
Referenced by getEVTString(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().
◆ isRound()
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Return true if the size is a power-of-two number of bytes.
Definition at line 248 of file ValueTypes.h.
References getSizeInBits(), and isScalableVector().
Referenced by llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), and isOnlyUsedByStores().
◆ isScalableTargetExtVT()
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Return true if this is a vector type where the runtime length is machine dependent.
Definition at line 163 of file ValueTypes.h.
References isSimple().
Referenced by isScalableVT().
◆ isScalableVector()
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Return true if this is a vector type where the runtime length is machine dependent.
Definition at line 174 of file ValueTypes.h.
References isSimple().
Referenced by llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses(), bitsGE(), bitsGT(), bitsLE(), bitsLT(), clampDynamicVectorIndex(), combineBinOpOfExtractToReduceTree(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOfShuffleAndItsOperands(), combineShuffleToZeroExtendVectorInReg(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAG::computeVectorKnownZeroElements(), convertToScalableVector(), convertToScalableVector(), convertValVTToLocVT(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorFindLastActive(), findMemType(), FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), foldConcatVector(), foldToMaskedStore(), llvm::AArch64TargetLowering::generateFMAsInMachineCombiner(), llvm::SelectionDAG::getConstant(), getCopyToPartsVector(), getEVTString(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), getPackedVectorTypeFromPredicateType(), getPredicateForScalableVector(), getPredicateRegisterClass(), getPromotedVTForPredicate(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getSplatSourceVector(), llvm::SelectionDAG::getStepVector(), getSVEPredicateBitCast(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorNumElements(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::AArch64TargetLowering::hasAndNot(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(), isPassedInFPR(), isRound(), isScalableVT(), llvm::SelectionDAG::isSplatValue(), llvm::SelectionDAG::isSplatValue(), isUnpackedVectorVT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerOperation(), LowerSVEIntrinsicEXT(), LowerVectorMatch(), performANDCombine(), performBSPExpandForSVE(), performBUILD_VECTORCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), performExtractSubvectorCombine(), performFirstTrueTestVectorCombine(), performGatherLoadCombine(), performINSERT_VECTOR_ELTCombine(), performInsertSubvectorCombine(), performLastTrueTestVectorCombine(), performScatterStoreCombine(), performSVEMulAddSubCombine(), performTruncateCombine(), performVectorDeinterleaveCombine(), performVP_TRUNCATECombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), replaceZeroVectorStore(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), SelectOpcodeFromVT(), llvm::AArch64TargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::AArch64TargetLowering::shouldReduceLoadWidth(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::SelectionDAG::SplitVector(), takeInexpensiveLog2(), tryLowerToBSL(), trySimplifySrlAddToRshrnb(), trySQDMULHCombine(), and llvm::RISCVSelectionDAGInfo::verifyTargetNode().
◆ isScalableVT()
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Return true if the type is a scalable type.
Definition at line 187 of file ValueTypes.h.
References isScalableTargetExtVT(), and isScalableVector().
Referenced by canLowerSRLToRoundingShiftForVT(), performSelectCombine(), and performVecReduceAddCombine().
◆ isScalarInteger()
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Return true if this is an integer, but not a vector.
Definition at line 157 of file ValueTypes.h.
References isSimple().
Referenced by combineBitcast(), combineBMILogicOp(), combineCastedMaskArithmetic(), combineExtractWithShuffle(), combineSetCC(), combineToExtendBoolVectorInReg(), combineToVCPOP(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), llvm::ARMTargetLowering::convertSetCCLogicToBitwiseLogic(), llvm::PPCTargetLowering::convertSetCCLogicToBitwiseLogic(), llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic(), llvm::SystemZTargetLowering::convertSetCCLogicToBitwiseLogic(), llvm::X86TargetLowering::convertSetCCLogicToBitwiseLogic(), llvm::LoongArchTargetLowering::decomposeMulByConstant(), llvm::PPCTargetLowering::decomposeMulByConstant(), llvm::RISCVTargetLowering::decomposeMulByConstant(), llvm::XtensaTargetLowering::decomposeMulByConstant(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAVG(), expandDivFix(), getReducedGprRegisterClass(), getVectorLoweringShape(), handleCMSEValue(), llvm::SystemZTTIImpl::hasDivRemOp(), llvm::TargetLoweringBase::isPaddedAtMostSignificantBitsWhenStored(), isRegRegScaleLoadOrStore(), llvm::X86TargetLowering::isTruncateFree(), isWorthFoldingAdd(), LowerSELECTWithCmpZero(), matchMergedBFX(), performAddCSelIntoCSinc(), performAddUADDVCombine(), performBitcastCombine(), performBITREVERSECombine(), performCTLZCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), performSETCCCombine(), llvm::AArch64TargetLowering::preferIncOfAddToSubOfNot(), llvm::ARMTargetLowering::preferIncOfAddToSubOfNot(), llvm::PPCTargetLowering::preferIncOfAddToSubOfNot(), promoteScalarIntegerPTX(), llvm::X86TargetLowering::shouldReduceLoadWidth(), truncateScalarIntegerArg(), tryDemorganOfBooleanCondition(), and useInversedSetcc().
◆ isSimple()
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Test if the given EVT is simple (as opposed to being extended).
Definition at line 137 of file ValueTypes.h.
References llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.
Referenced by llvm::HexagonTargetLowering::allowsMemoryAccess(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::HexagonTargetLowering::allowsMisalignedMemoryAccesses(), llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::R600TargetLowering::allowsMisalignedMemoryAccesses(), analyzeCallOperands(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), changeTypeToInteger(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineAndMaskToShift(), combineBitcastvxi1(), combineConcatVectorOps(), combineMul(), combineToVCPOP(), combineVectorInsert(), combineVSelectWithAllOnesOrZeros(), combineX86ShufflesRecursively(), llvm::createUnpackShuffleMask(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::SelectionDAG::FoldSetCC(), foldVectorXorShiftIntoCmp(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::AArch64TTIImpl::getExtendedReductionCost(), llvm::ARMTTIImpl::getExtendedReductionCost(), getExtensionTo64Bits(), getFauxShuffleMask(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::AArch64TTIImpl::getMulAccReductionCost(), llvm::ARMTTIImpl::getMulAccReductionCost(), llvm::TargetLoweringBase::getNumRegisters(), llvm::HexagonTargetLowering::getPostIndexedAddressParts(), getRawBits(), llvm::FastISel::getRegForValue(), llvm::TargetLoweringBase::getRegisterType(), llvm::X86TTIImpl::getShuffleCost(), getShuffleHalfVectors(), getSimpleVT(), getSizeInBits(), getSVEContainerType(), getTargetShuffleInputs(), getTargetShuffleInputs(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeConversion(), llvm::BasicTTIImplBase< BasicTTIImpl >::getTypeLegalizationCost(), llvm::SelectionDAG::getValueType(), getVectorElementCount(), getVectorElementType(), getVectorLoweringShape(), getVectorNumElements(), llvm::AArch64TargetLowering::hasPairedLoad(), incDecVectorConstant(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32BitVector(), is512BitVector(), is64BitVector(), isCheriCapability(), isConstantSplatVectorMaskForType(), isConstantSplatVectorMaskForType(), isExtended(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), isFixedLengthVector(), isFloatingPoint(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::TargetLoweringBase::isIndexedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedStoreLegal(), llvm::TargetLoweringBase::isIndexedStoreLegal(), isInteger(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), isSaturatingMinMax(), isScalableTargetExtVT(), isScalableVector(), isScalarInteger(), llvm::LoongArchTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), llvm::HexagonTargetLowering::isTruncateFree(), llvm::TargetLoweringBase::isTypeLegal(), isVector(), isVectorElementSwap(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), LowerADDSUBSAT(), llvm::VETargetLowering::lowerToVVP(), llvm::TargetLowering::ParseConstraints(), performBITCASTCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformEXTRACTCombine(), performTruncateCombine(), performUzpCombine(), performVSelectCombine(), ReplaceINTRINSIC_W_CHAIN(), llvm::FastISel::selectBinaryOp(), llvm::FastISel::selectCast(), llvm::FastISel::selectExtractValue(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::TargetLoweringBase::shouldFormOverflowOp(), llvm::X86TargetLowering::shouldFormOverflowOp(), llvm::TargetLowering::SimplifyDemandedBits(), supportedVectorShiftWithImm(), supportedVectorVarShift(), usePartialVectorLoads(), and llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().
◆ isVector()
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Return true if this is a vector value type.
Definition at line 168 of file ValueTypes.h.
References isSimple().
Referenced by adjustLoadValueTypeImpl(), llvm::X86TargetLowering::allowsMemoryAccess(), llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(), llvm::X86TargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canExpandVectorCTPOP(), changeElementType(), changeTypeToInteger(), CollectOpsToWiden(), combineAdd(), combineAnd(), combineAVG(), combineAVX512SetCCToKMOV(), combineBinOpOfZExt(), combineBitcast(), combineBitcastToBoolVector(), combineBITREVERSE(), combineCastedMaskArithmetic(), combineConcatVectorOfCasts(), combineConcatVectorOps(), combineExtSetcc(), combineFMinNumFMaxNum(), combineFP_EXTEND(), combineFP_ROUND(), combineLoad(), combineMul(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineOr(), combinePMULH(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), llvm::VETargetLowering::combineSelect(), combineSelectAndUse(), llvm::VETargetLowering::combineSelectCC(), combineSetCC(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftToAVG(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleOfBitcast(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineTruncatedArithmetic(), combineTruncateWithSat(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorMulToSraBitcast(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineX86ShufflesRecursively(), combineXor(), combineZext(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAG::computeVectorKnownZeroElements(), constructRetValue(), llvm::X86TargetLowering::convertSelectOfConstantsToMath(), llvm::TargetLowering::createSelectForFMINNUM_FMAXNUM(), detectEvenOddMultiplyOperand(), detectPMADDUBSW(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::SelectionDAG::expandMultipleResultFPLibCall(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVectorNaryOpBySplitting(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::SelectionDAG::FoldConstantArithmetic(), foldIndexIntoBase(), foldToMaskedStore(), foldVectorXorShiftIntoCmp(), llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(), llvm::SelectionDAG::getBitcastedSExtOrTrunc(), llvm::SelectionDAG::getBitcastedZExtOrTrunc(), llvm::VECustomDAG::getBroadcast(), getBuildVectorizedValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getDemandedSrcElements(), getEVTString(), getEXTEND_VECTOR_INREG(), getExtractVectorizedValue(), getFauxShuffleMask(), getHalfSizedIntegerVT(), getKnownUndefForVectorBinop(), llvm::SelectionDAG::getLoad(), getMemcpyLoadsAndStores(), getMemsetStores(), getMemsetStringVal(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getNumRegisters(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::PPCTargetLowering::getPreIndexedAddressParts(), getReciprocalOpName(), llvm::SelectionDAG::getReducedAlign(), llvm::TargetLoweringBase::getRegisterType(), llvm::HexagonTargetLowering::getRegisterTypeForCallingConv(), llvm::MipsTargetLowering::getRegisterTypeForCallingConv(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), getRoundIntegerType(), getScalarType(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::SelectionDAG::getSetCC(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::AVRTargetLowering::getSetCCResultType(), llvm::CSKYTargetLowering::getSetCCResultType(), llvm::HexagonTargetLowering::getSetCCResultType(), llvm::LoongArchTargetLowering::getSetCCResultType(), llvm::MipsTargetLowering::getSetCCResultType(), llvm::NVPTXTargetLowering::getSetCCResultType(), llvm::PPCTargetLowering::getSetCCResultType(), llvm::R600TargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), llvm::SITargetLowering::getSetCCResultType(), llvm::SparcTargetLowering::getSetCCResultType(), llvm::SystemZTargetLowering::getSetCCResultType(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::X86TargetLowering::getSetCCResultType(), llvm::XtensaTargetLowering::getSetCCResultType(), llvm::SelectionDAG::getShiftAmountOperand(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SelectionDAG::getStore(), getTargetShuffleInputs(), getTargetShuffleInputs(), llvm::SelectionDAG::getTruncStoreVP(), llvm::SelectionDAG::getTruncStridedStoreVP(), llvm::TargetLoweringBase::getTypeConversion(), llvm::AMDGPUTargetLowering::getTypeForExtReturn(), llvm::getTypePacking(), llvm::TargetLoweringBase::getTypeToExpandTo(), getVectorElementCount(), getVectorElementType(), getVectorizedVT(), getVectorNumElements(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::SelectionDAG::getVPZeroExtendInReg(), llvm::SelectionDAG::getZeroExtendInReg(), getZeroVector(), llvm::AArch64TargetLowering::hasAndNot(), llvm::RISCVTargetLowering::hasAndNot(), llvm::SystemZTargetLowering::hasAndNot(), llvm::VETargetLowering::hasAndNot(), llvm::X86TargetLowering::hasAndNot(), llvm::RISCVTargetLowering::hasAndNotCompare(), llvm::X86TargetLowering::hasAndNotCompare(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::RISCVTargetLowering::isCtpopFast(), llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(), IsElementEquivalent(), isExtendedFrom16Bits(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), isHorizontalBinOpPart(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::AArch64TargetLowering::isIntDivCheap(), llvm::RISCVTargetLowering::isIntDivCheap(), llvm::X86TargetLowering::isIntDivCheap(), isLegalT2AddressImmediate(), llvm::X86TargetLowering::isLoadBitCastBeneficial(), llvm::isMaskType(), isMImm(), llvm::AArch64TargetLowering::isMulAddWithConstProfitable(), llvm::ARMTargetLowering::isMulAddWithConstProfitable(), llvm::RISCVTargetLowering::isMulAddWithConstProfitable(), llvm::AMDGPUTargetLowering::isNarrowingProfitable(), isPackedVectorType(), llvm::isPackedVectorType(), isSimm7(), llvm::SelectionDAG::isSplatValue(), llvm::SelectionDAG::isSplatValue(), isSupportedType(), llvm::AArch64TargetLowering::isTruncateFree(), llvm::ARMTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::RISCVTargetLowering::isTruncateFree(), llvm::X86TargetLowering::isTypeDesirableForOp(), isVectorElementSwap(), isVShiftLImm(), isVShiftLImm(), isVShiftRImm(), isVShiftRImm(), llvm::X86TargetLowering::isXAndYEqZeroPreferableToXAndYEqY(), llvm::AArch64TargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), lowerBuildVectorAsBroadcast(), LowerCTTZ(), llvm::AMDGPUTargetLowering::lowerFEXP(), LowerFMINIMUM_FMAXIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), lowerLaneOp(), llvm::VETargetLowering::lowerLOAD(), llvm::RISCVTargetLowering::LowerOperation(), LowerShift(), lowerStatepointMetaArgs(), LowerStore(), llvm::VETargetLowering::lowerSTORE(), lowerSTOREVector(), LowerTcgen05St(), LowerTruncateVectorStore(), llvm::ARMTargetLowering::LowerXConstraint(), matchPMADDWD(), matchPMADDWD_2(), matchVPMADD52(), llvm::X86TargetLowering::mergeStoresAfterLegalization(), padEltsToUndef(), PerformADDCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformFADDCombine(), performFP_TO_INTCombine(), PerformLOADCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performMADD_MSUBCombine(), PerformMinMaxFpToSatCombine(), performMULCombine(), performMULCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), performMulCombine(), PerformMULCombineWithOperands(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), PerformORCombine(), performSelectCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), performVectorCompareAndMaskUnaryOpCombine(), performVectorNonNegToFPCombine(), PerformVQDMULHCombine(), llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(), llvm::X86TargetLowering::preferSextInRegOfTruncate(), PromoteBinOpToF32(), PromoteMaskArithmetic(), replaceBoolVectorBitcast(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceTcgen05Ld(), reverseZExtICmpCombine(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask(), llvm::X86TargetLowering::shouldFoldMaskToVariableShiftPair(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::TargetLoweringBase::shouldFormOverflowOp(), llvm::X86TargetLowering::shouldFormOverflowOp(), llvm::TargetLoweringBase::shouldReduceLoadWidth(), llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(), llvm::RISCVTargetLowering::shouldTransformSignedTruncationCheck(), llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::SelectionDAG::SplitScalar(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::AMDGPUTargetLowering::splitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), stripModuloOnShift(), takeInexpensiveLog2(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::RISCVTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), transformAddImmMulImm(), transformAddShlImm(), truncateAVX512SetCCNoBWI(), truncateVectorWithPACK(), tryFoldToZero(), tryLowerToBSL(), tryLowerToSLI(), trySQDMULHCombine(), tryToFoldExtendOfConstant(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), tryToReplaceScalarFPConversionWithSVE(), tryToWidenSetCCOperands(), llvm::SelectionDAG::UnrollVectorOp(), llvm::AArch64SelectionDAGInfo::verifyTargetNode(), widenAbs(), widenVec(), and widenVectorToPartType().
◆ isZeroSized()
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inline |
Test if the given EVT has zero size, this will fail if called on a scalable type.
Definition at line 132 of file ValueTypes.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isZero().
Referenced by llvm::TargetLoweringBase::allowsMemoryAccessForAlignment(), and isByteSized().
◆ knownBitsGE()
Return true if we know at compile time this has more than or the same bits as VT.
Definition at line 268 of file ValueTypes.h.
References EVT(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGE().
Referenced by bitsGE().
◆ knownBitsGT()
Return true if we know at compile time this has more bits than VT.
Definition at line 262 of file ValueTypes.h.
References EVT(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGT().
Referenced by bitsGT().
◆ knownBitsLE()
Return true if we know at compile time this has fewer than or the same bits as VT.
Definition at line 279 of file ValueTypes.h.
References EVT(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE().
Referenced by bitsLE().
◆ knownBitsLT()
Return true if we know at compile time this has fewer bits than VT.
Definition at line 273 of file ValueTypes.h.
References EVT(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLT().
Referenced by bitsLT().
◆ operator!=()
Definition at line 48 of file ValueTypes.h.
References EVT(), llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, and llvm::MVT::SimpleTy.
◆ operator==()
Definition at line 45 of file ValueTypes.h.
References EVT().
◆ print()
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inline |
Implement operator<<.
Definition at line 496 of file ValueTypes.h.
References getEVTString().
Referenced by dump().
◆ widenIntegerVectorElementType()
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inline |
Return a VT for an integer vector type with the size of the elements doubled.
The typed returned may be an extended type.
Definition at line 444 of file ValueTypes.h.
References EVT(), getIntegerVT(), getSizeInBits(), getVectorElementCount(), getVectorElementType(), and getVectorVT().
The documentation for this struct was generated from the following files:
- include/llvm/CodeGen/ValueTypes.h
- lib/CodeGen/ValueTypes.cpp
Generated on for LLVM by
1.14.0