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LP8545SQX/NOPB

更新时间：2025-05-03 05:35:23

品牌：TI

描述：适用于笔记本电脑的六通道高效 LED 背光驱动器，具有灵活的外部/内部 FET 控制 | RTW | 24 | -30 to 85

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LP8545SQX/NOPB 概述

适用于笔记本电脑的六通道高效 LED 背光驱动器，具有灵活的外部/内部 FET 控制 | RTW | 24 | -30 to 85 LED驱动器显示驱动器

LP8545SQX/NOPB 规格参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN, LCC24,.16SQ,20
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	6 weeks
风险等级：	5.32	数据输入模式：	SERIAL
输入特性：	STANDARD	接口集成电路类型：	LED DISPLAY DRIVER
JESD-30 代码：	S-PQCC-N24	JESD-609代码：	e3
长度：	4 mm	湿度敏感等级：	1
复用显示功能：	NO	功能数量：	1
区段数：	60	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-30 °C
输出特性：	CONSTANT-CURRENT	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装等效代码：	LCC24,.16SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	12 V
认证状态：	Not Qualified	座面最大高度：	0.8 mm
子类别：	Display Drivers	最大压摆率：	0.001 mA
最大供电电压：	22 V	最小供电电压：	5.5 V
标称供电电压：	12 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm	最小 fmax：	0.025 MHz
Base Number Matches：	1

LP8545SQX/NOPB 数据手册

通过下载LP8545SQX/NOPB数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

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LP8545

LP8545 High-Efficiency LED Backlight Driver for Notebooks

Literature Number: SNVS635B

September 23, 2011

LP8545

High-Efficiency LED Backlight Driver for Notebooks

General Description

The LP8545 is a white LED driver with integrated boost con-

verter. It has six adjustable current sinks which can be con-

trolled by PWM input or with I²C-compatible serial interface.

Features

High-voltage DC/DC boost converter with integrated FET

■

with four switching frequency options: 156/312/625/1250

kHz

Configurable for use with external FET for applications

needing higher output voltage

2.7V – 22V input voltage range to support 1x…5x cell Li-

Ion batteries

The boost converter has adaptive output voltage control

based on the LED driver voltages. This feature minimizes the

power consumption by adjusting the voltage to lowest suffi-

cient level in all conditions.

■

LED outputs have 8-bit current resolution and up to 13-bit

PWM resolution with additional 1-3 bit dithering to achieve

smooth and precise brightness control. Proprietary Phase

Shift PWM control is used for LED outputs to reduce peak

current from the boost converter, thus making the boost ca-

pacitors smaller. The Phase Shifting scheme also eliminates

audible noise.

Programmable PWM resolution

■

8 to 13 true bit (steady state)

—

Additional 1 to 3 bits using dithering during brightness

changes

I²C and PWM brightness control

■

PWM output frequency and LED current set through

resistors

Optional synchronization to display V_SYNCsignal

6 LED outputs with LED fault (short/open) detection

Internal EEPROM is used for storing the configuration data.

This makes it possible to have minimum external component

count and make the solution very small.

■

Low input voltage, over-temperature, over-current

detection and shutdown

Minimum number of external components

LLP 24-pin package, 4 x 4 x 0.8 mm

LP8545 has safety features which make it possible to detect

LED outputs with open or short fault. As well low input voltage

and boost over-current conditions are monitored and chip is

turned off in case of these events. Thermal de-rating function

prevents overheating of the device by reducing backlight

brightness when set temperature has been reached.

■

Applications

LP8545 is available in National's LLP 24-pin package.

Notebook and Netbook LCD Display LED Backlight

■

LED Lighting

Typical Application (1)

30108470

301084

www.national.com

Typical Application for Low Input Voltage (2)

30108471

Note: Separate 5V rail to V_LDOcan be also used to improve efficiency for applications with higher battery voltage. No power

sequencing requirements between V_IN/V_LDOand V_BATT

Typical Application for High Output Voltage (3)

30108468

www.national.com

Connection Diagrams and Package Mark Information

24–pin Leadless Leadframe Package (LLP)

4.0 x 4.0 x 0.8mm, 0.5 mm pitch

NS Package Number SQA24A

30108475

30108472

Top View

Bottom View

Package Mark

30108496

Package Mark - Top View

U = Fab

Z = Assembly

XY = 2–Digit Date Code

TT = Die Traceability

xxxx = Product Identification

Ordering Information

Order Number

Spec/flow

Package Marking

Supplied As

4500 units, Tape-and-Reel

LP8545SQX

NOPB / HFLF

L8545SQ

www.national.com

Pin Descriptions

Pin #

Name

GND_SW

PWM

Type

Description

Boost switch ground

PWM dimming input. This pin must be connected to GND if not used.

Set resistor for LED current. This pin can be left floating if not used.

Enable input pin

ISET

FSET

PWM frequency set resistor. This pin can be left floating if not used.

Gate driver for external FET. If not used, can be left floating.

Fault indication output. If not used, can be left floating.

Digital IO reference voltage (1.65V...5V) for I²C interface. If brightness is controlled

with PWM input pin then this pin can be connected to GND.

Signal ground

FAULT

VDDIO

GND_S

SCLK

SDA

Serial clock. This pin must be connected to GND if not used.

Serial data. This pin must be connected to GND if not used.

Current sink output

I/O

OUT1

OUT2

OUT3

GND_L

OUT4

OUT5

OUT6

VSYNC

FILTER

Current sink output

LED ground

Current sink output

V_SYNCinput. This pin must be connected to GND if not used.

Low pass filter for PLL. This pin can be left floating if not used.

Boost feedback input

VLDO

LDO output voltage. External 5V rail can be connected to this pin in low voltage

application.

VIN

Input power supply up to 22V. If 2.7V ≤ VBATT < 5.5V (Typical Application for Low

Input Voltage (2)) then external 5V rail must be used for VLDO and VIN.

Boost switch. With external FET (typ. app. (3)) this pin acts as a current sense.

A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin

www.national.com

Operating Ratings (Note 1, Note 2)

Absolute Maximum Ratings (Note 1, Note

Input Voltage Range (V_IN)

typ. app. (1), (3)

5.5V to 22.0V

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Input Voltage Range (V_IN+ V_LDO

typ. app. (2)

V_DDIO

)

4.5V to 5.5V

1.65V to 5V

0V to 40V

-30°C to +125°C

-30°C to +85°C

V_IN

-0.3V to +24.0V

-0.3V to +6.0V

V(OUT1...OUT6, SW, FB)

Junction Temperature (T_J) Range

V_LDO

Voltage on Logic Pins (VSYNC,

PWM, EN, SCLK, SDA)

Ambient Temperature (T_A) Range

(Note 6)

Voltage on Logic Pin (FAULT)

-0.3V to VDDIO +

0.3V

Thermal Properties

Junction-to-Ambient Thermal

Resistance (θ_JA), SQA Package

(Note 7)

Voltage on Analog Pins (FILTER,

GD, VDDIO, ISET, FSET)

V (OUT1...OUT6, SW, FB)

-0.3V to +6.0V

35 to 50°C/W

-0.3V to +44.0V

Internally Limited

Continuous Power Dissipation

(Note 3)

Junction Temperature (T_J-MAX

)

125°C

-65°C to +150°C

(Note 4)

Storage Temperature Range

Maximum Lead Temperature

(Soldering)

ESD Rating

Human Body Model:

Machine Model:

(Note 5)

2 kV

200V

1 kV

Charged Device Model:

Electrical Characteristics (Note 2, Note 8)

Limits in standard typeface are for T_A= 25°C. Limits in boldface type apply over the full operating ambient temperature range

(-30°C ≤ T_A≤ +85°C). Unless otherwise specified: V_IN= 12.0V, C_VLDO= 1 μF, L1 = 15 μH, C_IN= 10 μF, C_OUT= 10 μF. R_ISET= 16

kΩ (Note 9)

Symbol

Parameter

Condition

Internal LDO disabled

EN=L and PWM=L

Min

Typ

Max

Units

Standby Supply Current

μA

LDO enabled, boost enabled, no current

going through LED outputs, Internal FET

used

4.0

I_IN

5 MHz PLL Clock

Normal Mode Supply Current

10 MHz PLL Clock

20 MHz PLL Clock

40 MHz PLL Clock

4.8

6.0

8.4

f_OSC

Internal Oscillator Frequency

Accuracy

-4

-7

V_LDO

I_LDO

Internal LDO Voltage

4.5

5.0

5.5

Internal LDO External Loading

5.0

Boost Converter Electrical Characteristics

Symbol

RDS_ON

V_MAX

Parameter

Condition

Min

Typ

Max

Units

Ω

Switch ON Resistance

I_SW= 0.5A

0.12

Boost Maximum Output Voltage

450

300

180

9.0V ≤ V_BATT, V_OUT= 35V

6.0V ≤ V_BATT, V_OUT= 35V

3.0V ≤ V_BATT, V_OUT= 25V

9.0V ≤ V_BATT, V_OUT= 50V

6.0V ≤ V_BATT, V_OUT= 50V

Maximum Continuous Load

Current, Internal FET

I_LOAD

320

190

Maximum Continuous Load

Current, External FET

I_LOAD

www.national.com

Symbol

Parameter

Condition

Min

Typ

Max

Units

V_OUT/V_INConversion Ratio

BOOST_FREQ = 00

156

312

625

BOOST_FREQ = 01

BOOST_FREQ = 10

BOOST_FREQ = 11

f_SW

Switching Frequency

kHz

1250

V_BOOST+ 1.6V

V_BOOST+ 4V

V_BOOST≥ 38V

V_OV

Over-voltage Protection Voltage

Switch Pulse Minimum Width

V_BOOST< 38V

t_PULSE

no load

t_STARTUPStartup Time

(Note 10)

BOOST_IMAX[1:0] = 00

BOOST_IMAX[1:0] = 01

BOOST_IMAX[1:0] = 10

BOOST_IMAX[1:0] = 11

0.9

1.4

2.0

2.5

I_MAX

SW Pin Current Limit

V_GD

EN_EXT_FET = 1

VLDO

Gate Driver Pin Voltage

LED Driver Electrical Characteristics

Symbol

I_LEAKAGE

Parameter

Leakage Current

Condition

Min

Typ

0.1

Max

Units

Outputs OUT1...OUT6, V_OUT= 40V

EN_I_RES = 0, CURRENT[7:0] = FFh

EN_I_RES = 1

µA

Maximum Source Current

OUT1...OUT6

I_MAX

Output Current Accuracy

(Note 11)

-3

-4

I_OUT

Output current set to 23 mA, EN_I_RES = 1

I_MATCH

Matching (Note 11)

Output current set to 23 mA, EN_I_RES = 1

f_LED= 5 kHz, f_PLL= 5 MHz

0.5

f_LED= 10 kHz, f_PLL= 5 MHz

f_LED= 20 kHz, f_PLL= 5 MHz

f_LED= 5 kHz, f_PLL= 40 MHz

f_LED= 10 kHz, f_PLL= 40 MHz

f_LED= 20 kHz, f_PLL= 40 MHz

PWM Output Resolution

(Note 14)

PWM_RES

bits

PWM_FREQ[4:0] = 00000b

PLL clock 5 MHz

600

LED Switching Frequency (Note

14)

f_LED

PWM_FREQ[4:0] = 11111b

PLL clock 5 MHz

19.2k

Output current set to 20 mA

Output current set to 30 mA

120

180

175

270

V_SAT

Saturation Voltage (Note 12)

PWM Interface Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

f_PWM

PWM Frequency Range

Minimum Pulse ON time

Minimum Pulse OFF time

0.1

kHz

t_{MIN_ON}

t_{MIN_OFF}

µs

Turn on delay from standby to

backlight on

PWM input active, EN pin rise from low to

high

t_STARTUP

T_STBY

PWM input low time for turn off, slope

disabled

Turn Off Delay

f_IN< 9.0 kHz

f_IN< 4.5 kHz

f_IN< 2.2 kHz

f_IN< 1.1 kHz

PWM_RES

PWM Input Resolution

bits

www.national.com

Under-Voltage Protection

Symbol

Parameter

Condition

Min

Typ

Disabled

2.70

Max

Units

UVLO[1:0] = 00

UVLO[1:0] = 01, falling

UVLO[1:0] = 01, rising

UVLO[1:0] = 10, falling

UVLO[1:0] = 10, rising

UVLO[1:0] = 11, falling

UVLO[1:0] = 11, rising

2.55

2.62

5.11

5.38

7.75

8.36

2.94

3.00

5.68

5.98

8.45

9.20

2.76

V_UVLOV_INUVLO Threshold Voltage

5.40

5.70

8.10

8.73

Logic Interface Characteristics

Symbol

Logic Input EN

Parameter

Condition

Min

Typ

Max

0.4

Units

V_IL

V_IH

I_I

Input Low Level

1.2

Input High Level

Input Current

-1.0

1.0

0.4

µA

Logic Input VSYNC

V_IL

Input Low Level

Input High Level

Input Current

V_IH

I_I

2.2

-1.0

1.0

µA

f_VSYNC

55000

Frequency Range

Logic Input PWM

V_IL

V_IH

I_I

0.4

1.0

Input Low Level

Input High Level

Input Current

2.2

-1.0

µA

Logic Inputs SCL, SDA

V_IL

V_IH

I_I

0.2xV_DDIO

1.0

Input Low Level

Input High Level

Input Current

0.8xV_DDIO

-1.0

µA

Logic Outputs SDA, FAULT

V_OL

I_L

I_OUT= 3 mA (pull-up current)

V_OUT= 2.8V

0.3

0.5

1.0

Output Low Level

-1.0

Output Leakage Current

µA

I²C Serial Bus Timing Parameters (SDA, SCLK) (Note 13)

Limit

Symbol

Parameter

Units

Min

Max

f_SCLK

Clock Frequency

400

kHz

µs

Hold Time (repeated) START Condition

Clock Low Time

0.6

1.3

Clock High Time

600

Setup Time for a Repeated START Condition

Data Hold Time

600

Data Setup Time

100

Rise Time of SDA and SCL

Fall Time of SDA and SCL

Set-up Time for STOP condition

20+0.1C_b

15+0.1C_b

600

300

www.national.com

C_b

Bus Free Time between a STOP and a START Condition

1.3

µs

Capacitive Load Parameter for Each Bus Line

Load of 1 pF corresponds to 1 ns.

200

30108498

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins.

Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typ.) and disengages at T_J

= 130°C (typ.).

Note 4: For detailed soldering specifications and information, please refer to National Semiconductor AN1187: Leadless Leadframe Package (LLP).

Note 5: Human Body Model, applicable standard JESD22-A114C. Machine Model, applicable standard JESD22- A115-A. Charged Device Model, applicable

standard JESD22A-C101.

Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP= 125°C), the maximum power

dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the

following equation: T_A-MAX= T_J-MAX-OP– (θ_JA× P_D-MAX).

Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,

special care must be paid to thermal dissipation issues in board design.

Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

Note 10: Start-up time is measured from the moment boost is activated until the V_OUTcrosses 90% of its target value.

Note 11: Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum

difference from the average. For the constant current sinks on the part (OUT1 to OUT6), the following are determined: the maximum output current (MAX), the

minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN/

AVG). The largest number of the two (worst case) is considered the matching figure. The typical specification provided is the most likely norm of the matching

figure for all parts. Note that some manufacturers have different definitions in use.

Note 12: Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1V.

Note 13: Guaranteed by design. V_DDIO= 1.65V to 5.5V.

Note 14: PWM output resolution and frequency depend on the PLL settings. Please see section “PWM Frequency Settings” for full description

www.national.com

Typical Performance Characteristics

Unless otherwise specified: V_BATT= 12.0V, C_VLDO= 1 μF, L1 = 33 μH, C_IN= 10 μF, C_OUT= 10 μF

LED Drive Efficiency, f_LED= 19.2 kHz

LED Drive Efficiency, f_LED= 19.2 kHz, L1 = 15 μH

30108492

30108493

LED Drive Efficiency, f_LED= 19.2 kHz, External FET

Boost Converter Efficiency

30108490

30108491

Battery Current

I_LEDvs. R_ISET

30108488

30108489

www.national.com

Typical Waveforms, f_LED= 9.6 kHz

30108485

30108486

Boost Line Transient Response

30108484

www.national.com

Modes of Operation

30108403

RESET:

In the RESET mode all the internal registers are reset to the default values. Reset is entered always VLDO

voltage is low. EN pin is enable for the internal LDO. Power On Reset (POR) will activate during the chip

startup or when the supply voltage VLDO fall below POR level. Once VLDO rises above POR level, POR

will inactivate and the chip will continue to the STANDBY mode.

STANDBY:

STARTUP:

The STANDBY mode is entered if the register bit BL_CTL is LOW and external PWM input is not active and

POR is not active. This is the low-power consumption mode, when only internal 5V LDO is enabled. Registers

can be written in this mode and the control bits are effective immediately after startup.

When BL_CTL bit is written high or PWM signal is high, the INTERNAL STARTUP SEQUENCE powers up

all the needed internal blocks (VREF, Bias, Oscillator etc.). Internal EPROM and EEPROM are read in this

mode. To ensure the correct oscillator initialization etc, a 2 ms delay is generated by the internal state-

machine. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables the chip operation

and STARTUP mode is entered until no thermal shutdown event is present.

BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in low

current PWM mode during the 4 ms delay generated by the state-machine. All LED outputs are off during

the 4 ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if

EN_BOOST is HIGH.

NORMAL:

During NORMAL mode the user controls the chip using the external PWM input or with Control Registers

through I²C. The registers can be written in any sequence and any number of bits can be altered in a register

in one write.

www.national.com

Functional Overview

LP8545 is a high voltage LED driver for medium sized LCD

backlight applications. It includes high voltage boost convert-

er which can be used either with internal FET or with external

FET depending on boost output voltage requirements. Boost

voltage automatically sets to the correct level needed to drive

the LED strings. This is done by monitoring LED output volt-

age drop in real time.

heating in case of open in some of the LED strings. Chip

internal temperature is constantly monitored and based on

this LP8545 can reduce the brightness of the backlight to re-

duce thermal loading once certain trip point is reached.

Threshold is programmable in EEPROM. If chip internal tem-

perature reaches too high, the boost converter and LED

outputs are completely turned off until the internal tempera-

ture has reached acceptable level. Boost converter is pro-

tected against too high load current and over-voltage. LP8545

notifies the system about the fault through I²C register and

with FAULT pin.

Six constant current sinks with PWM control are used for driv-

ing LEDs. Constant current value is set with EEPROM bits

and with R_ISETresistor. Brightness (PWM) is controlled either

with I²C register or with PWM input. PWM frequencies are set

with EEPROM bits and with R_FSETresistor. Special Phase-

Shift PWM mode can be used to reduce boost output current

peak, thus reducing output ripple, capacitor size and audible

noise.

EEPROM programmable functions include:

•

PWM frequencies

Phase shift PWM mode

LED constant current

Boost output frequency

Temperature thresholds

Slope for brightness changes

Dithering options

With LP8545 it is possible to synchronize the PWM output

frequency to V_SYNCsignal received from video processor. In-

ternal PLL ensures that the PWM output clock is always

synchronized to the V_SYNCsignal.

Special dithering mode makes it possible to increase output

resolution during fading between two brightness values and

by this making the transition look very smooth with virtually

no stepping. Transition slope time can be adjusted with

EEPROM bits.

PWM output resolution

Boost control bits

External components R_ISETand R_FSETcan also be used for

selecting the output current and PWM frequencies.

Safety features include LED fault detection with open and

short detection. LED fault detection will prevent system over-

Block Diagram

30108474

www.national.com

the LED output PWM is always synchronized to the V_SYNC

signal and there is no clock variation between LCD display

video update and the LED backlight output frequency. Also

H_SYNCsignal up to 55 kHz can be used.

Clock Generation

LP8545 has internal 5 MHz oscillator which is used for clock-

ing the boost converter, state machine, PWM input duty cycle

measurement, internal timings such as slope time for output

brightness changes.

PLL has internal counter which has 13-bit control <PLL[12:0]

> to achieve correct output clock frequency based on the

V_SYNCfrequency.

Internal clock can be used for generating the PWM output

frequency. In this case the 5 MHz clock can be multiplied with

the internal PLL to achieve higher resolution. The higher the

clock frequency for PWM generation block, the higher the

resolution but the tradeoff is higher IQ of the part. Clock mul-

tiplication is set with <PWM_RESOLUTION[1:0]> EEPROM

Bits.

For the PLL it can take couple of seconds to synchronize to

60 Hz V_SYNCsignal in startup and before this correct PWM

clock frequency is generated from internal oscillator. FILTER

pin component selection affects the time it takes from the PLL

to lock to V_SYNCsignal. When backlight is turned off the EN

pin must be set low to ensure correct PLL behavior during

next startup.

The PLL can also be used for generating the required PWM

generation clock from the V_SYNCsignal. This makes sure that

30108404

Principle of the Clock Generation

www.national.com

different frequency than input in this mode and also phase

shift PWM mode can be used. Slope and dither are effective

in this mode. PWM input resolution is defined by the input

PWM clock frequency.

Brightness Control Methods

LP8545 controls the brightness of the backlight with PWM.

PWM control is received either from PWM input pin or from

I²C register bits. The PWM source selection is done with

<BRT_MODE[1:0]> bits as follows:

BRIGHTNESS REGISTER CONTROL

With brightness register control the output PWM is controlled

with 8-bit resolution <BRT7:0> register bits. Phase shift

scheme can be used with this and the output PWM frequency

can be freely selected. Slope and dither are effective in this

mode.

BRT_MODE BRT_MODE

PWM source

[1]

[0]

PWM input pin duty

cycle control. Default.

PWM input pin duty

cycle control.

PWM DIRECT CONTROL

With PWM direct control the output PWM will directly follow

the input PWM. Due to the internal logic structure the input is

anyway clocked with the 5 MHz clock or the PLL clock. PSP-

WM mode is not possible in this mode. Slope and dither are

not effective in this mode.

Brightness register

PWM direct control

(PWM in = PWM out)

PWM INPUT DUTY CYCLE

PWM CALCULATION DATA FLOW

With PWM input pin duty cycle control the output PWM is

controlled by PWM input duty cycle. PWM detector block

measures the duty cycle in the PWM pin and uses this 13-bit

value to generate the output PWM. Output PWM can have

Below is flow chart of the PWM calculation data flow. In PWM

direct control mode most of the blocks are bypassed and this

flow chart does not apply.

30108405

PWM Calculation Data Flow

PWM DETECTOR

SLOPER

PWM detector block measures the duty cycle of the input

PWM signal. Resolution depends on the input signal frequen-

cy. Hysteresis selection sets the minimum allowable change

to the input. If smaller change is detected, it is ignored. With

hysteresis the constant changing between two brightness val-

ues is avoided if there is small jitter in the input signal.

Sloper makes the smooth transition from one brightness val-

ue to another. Slope time can be adjusted from 0 to 500 ms

with <SLOPE[3:0]> EEPROM bits. The sloper output is 16-bit

value.

DITHER

With dithering the output resolution can be “artificially” in-

creased during sloping from one brightness value to another.

This way the brightness change steps are not visible to eye.

Dithering can be from 0 to 3 bits, and is selected with

<DITHER[1:0]> EEPROM bits.

BRIGHTNESS CONTROL

Brightness control block gets 13-bit value from the PWM de-

tector, 12-bit value from the temperature sensor and also 8-

bit value from the brightness register. <BRT_MODE[1:0]>

selects whether to use PWM input duty cycle value or the

brightness register value as described earlier. Based on the

temperature sensor value the duty cycle is reduced if the

temperature has reached the temperature limit set to the

<TEMP_LIM[1:0]> EEPROM bits.

PWM COMPARATOR

The PWM counter clocks the PWM comparator based on the

duty cycle value received from Dither block. Output of the

PWM comparator controls directly the LED drivers. If PSPWM

mode is used, then the signal to each LED output is delayed

certain amount.

RESOLUTION SELECTOR

Resolution selector takes the necessary MSB bits from the

input data to match the output resolution. For example if 11-

bit resolution is used for output, then 11 MSB bits are selected

from the input. Dither bits are not taken into account for the

output resolution. This is to make sure that in steady state

condition, there is no dithering used for the output.

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CURRENT SETTING

E.g. If 16 kΩ R_ISETresistor is used, then the LED maximum

current is 23 mA. Note: formula is only approximation for the

actual current.

Maximum current of the LED outputs is controlled with CUR-

RENT[7:0] EEPROM register bits linearly from 0 to 30 mA. If

EN_I_RES = 1 the maximum LED output current can be

scaled also with external resistor, R_ISET. R_ISETcontrols the

LED current as follows:

PWM FREQUENCY SETTING

PWM frequency is selected with PWM_FREQ[4:0] EEPROM

effect to the output PWM frequency as well. <PWM_RESO-

LUTION[1:0]> EEPROM bits will select the PLL output fre-

quency and hence the PWM frequency and resolution. Below

are listed PWM frequencies with <EN_VSYNC]> = 0. PWM

resolution setting affects the PLL clock frequency (5 MHz…

40 MHz). Highlighted frequencies with boldface can be se-

lected also with external resistor R_FSET. To activate R_FSET

frequency selection the <EN_F_RES> EEPROM bit must be

Default value for CURRENT[7:0] = 7Fh (127d). Therefore the

output current can be calculated as follows:

PWM_RES[1:0]

PWM FREQ[4:0]

11111

11110

11101

11100

11011

11010

11001

11000

10111

10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

10 MHz

20 MHz

5 MHz

19232

16828

14424

12020

9616

7963

6386

4808

4658

4508

4357

4207

4057

3907

3756

3606

3456

3306

3155

3005

2855

2705

2554

2404

2179

1953

1728

1503

1202

1052

826

40 MHz

Resolution (bits)

19232

15927

12771

9616

9316

9015

8715

8414

8114

7813

7513

7212

6912

6611

6311

6010

5710

5409

5109

4808

4357

3907

3456

3005

2404

2104

1653

1202

19232

18631

18030

17429

16828

16227

15626

15025

14424

13823

13222

12621

12020

11419

10818

10217

9616

8715

7813

6912

6010

4808

4207

3306

2404

19232

17429

15626

13823

12020

9616

8414

6611

4808

601

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R_FSETresistance values with corresponding PWM frequen-

cies:

PWM_RES[1:0]

5 MHz Clock Resolution

10 MHz

Clock

Resolution

20 MHz

Clock

Resolution

40 MHz

Clock

Resolution

RFSET (kΩ)

10...15

26...29

19232

16828

14424

12020

9616

19232

15927

12771

9616

8715

7813

6311

4808

19232

16227

14424

12020

9616

19232

17429

15626

12020

9616

36...41

50...60

85...100

135...150

200...300

450...

7963

7813

8414

6386

6010

6811

4808

PHASE SHIFT PWM SCHEME

on boost output by x6 and therefore transfers the possible

audible noise to so high frequency that human ear cannot

hear it.

Phase shift PWM scheme allows delaying the time when each

LED output is active. When the LED output are not activated

simultaneously, the peak load current from the boost output

is greatly decreased. This reduces the ripple seen on the

boost output and allows smaller output capacitors. Reduced

ripple also reduces the output ceramic capacitor audible ring-

ing. PSPWM scheme also increases the load frequency seen

Description of the PSPWM mode is seen on the following di-

agram. PSPWM mode is enabled by setting <EN_PSPWM>

EEPROM bit to 1. Shift time is the delay between outputs and

it is defined as 1 / (f_PWMx 6). If the <EN_PSPWM> bit is 0,

then the delay is 0 and all outputs are active simultaneously.

30108406

Phase Shift PWM Mode

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SLOPE AND DITHERING

ms. Same slope time is used for sloping up and down. Ad-

vanced slope makes brightness changes smooth for eye.

Dithering can be programmed with EEPROM bits <DITHER

[1:0]> from 0 to 3 bits. Example below is for 1-bit dithering,

e.g., for 3-bit dithering, every 8th pulse is made 1 LSB longer

to increase the average value by 1/8 of LSB.

During transition between two brightness (PWM) values spe-

cial dithering scheme is used if the slope is enabled. It allows

increased resolution and smaller average steps size. Dither-

ing is not used in steady state condition. Slope time can be

programmed with EEPROM bits <SLOPE[3:0]> from 0 to 500

30108483

Sloper Operation

30108494

Example of the Dithering,

1-bit dither, 10-bit resolution

DRIVER HEADROOM CONTROL

Driver headroom can be

ward voltage is the one which has highest V_Facross the

LEDs. The strings with highest forward voltage is detected

automatically. To achieve best possible efficiency smallest

possible headroom voltage should be selected. If there is high

variation between LED strings, the headroom can be raised

slightly to prevent any visual artifacts.

controlled

with

<DRV_HEADR[2:0]> EEPROM bits. Driver headroom control

sets the minimum threshold for the voltage over the LED out-

put which has the smallest driver headroom and controls the

boost output voltage accordingly. Boost output voltage step

size is 125 mV. The LED output which has the smallest for-

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written through the serial interface, and data will be effective

immediately. To read and program NVM, separate com-

mands need to be sent. Erase and program voltages are

generated on-chip charge pump, no other voltages than nor-

mal input voltage are required. A complete EEPROM memory

map is shown in the chapter LP8545 EEPROM Memory Map.

EEPROM

EEPROM memory stores various parameters for chip control.

The 64-bit EEPROM memory is organized as 8 x 8 bits. The

EEPROM structure consists of a register front-end and the

non-volatile memory (NVM). Register data can be read and

30108439

current is measured and controlled with the feedback. Switch-

ing frequency is selectable between 156 kHz and 1.25 MHz

Boost Converter

with

EEPROM

bit

<BOOST_FREQ[1:0]>.

When

<EN_BOOST> EEPROM register bit is set to 1, then boost

will activate automatically when backlight is enabled.

OPERATION

The LP8545 boost DC/DC converter generates a 10…40V

supply voltage for the LEDs from 2.7…22V input voltage. The

output voltage can be controlled either with EEPROM register

bits <VBOOST[4:0]> or automatic adaptive voltage control

can be used. Higher output voltages can be achieved with

external FET and by using resistor divider in the FB pin. GD

pin operates as gate driver for the external FET in this case.

To activate external FET gate driver, <EN_EXT_FET> bit in

EEPROM register must be set to 1. The converter is a mag-

netic switching PWM mode DC/DC converter with a current

limit. The topology of the magnetic boost converter is called

CPM (current programmed mode) control, where the inductor

In adaptive mode the boost output voltage is adjusted auto-

matically based on LED driver headroom voltage. Boost out-

put voltage control step size is, in this case, 125 mV to ensure

as small as possible driver headroom and high efficiency. En-

abling the adaptive mode is done with <EN_ADAPT> EEP-

ROM bit. If boost is started with adaptive mode enabled, then

the initial boost output voltage value is defined with the

<VBOOST[4:0]> EEPROM register bits in order to eliminate

long output voltage iteration time when boost is started for the

first time. The following figure shows the boost topology with

the protection circuitry:

30108440

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PROTECTION

ADAPTIVE BOOST CONTROL

Three different protection schemes are implemented:

Adaptive boost control function adjusts the boost output volt-

age to the minimum sufficient voltage for proper LED driver

operation. The output with highest V_FLED string is detected

and boost output voltage adjusted accordingly. Driver head-

room can be adjusted with <DRIVER_HEADR[2:0]> EEP-

ROM bits from ~300 mV to 1200 mV. Boost adaptive control

voltage step size is 125 mV. Boost adaptive control operates

similarly with and without PSPWM.

1. Over-voltage protection, limits the maximum output

voltage.

Over-voltage protection limit changes dynamically

based on output voltage setting.

—

Keeps the output below breakdown voltage.

—

Prevents boost operation if battery voltage is much

higher than desired output.

2. Over-current protection, limits the maximum inductor

current.

3. Duty cycle limiting.

MANUAL OUTPUT VOLTAGE CONTROL

User can control the boost output voltage with <VBOOST[4:0]

> EEPROM register bits when adaptive mode is disabled.

VBOOST[4:0]

Bin

Voltage (typical)

Dec

Volts

...

00000

00001

00010

00011

00100

...

30108441

Boost Adaptive Control Principle with PSPWM

...

11101

11110

11111

If resistor divider is used for the FB pin to get higher output

voltage with external FET, the boost output voltages are

scaled accordingly.

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fault bit is set in fault register. LEDs and boost will start again

when the voltage has increased above the threshold level.

Hysteresis is implemented to threshold level to avoid contin-

uous triggering of fault when threshold is reached.

Fault Detection

LP8545 has fault detection for LED fault, low-battery voltage,

over-current and thermal shutdown. The open drain output

pin (FAULT) can be used to indicate occurred fault. The cause

for the fault can be read from status register. Reading the fault

reset the faults, even if an external 5V line is used to power

VLDO pin.

Fault is cleared by setting EN pin low or by reading the fault

OVER-CURRENT PROTECTION

LP8545 has detection for too-high loading on the boost con-

verter. When over-current fault is detected, the LP8545 will

shut down.

LED FAULT DETECTION

With LED fault detection, the voltages across the LED drivers

are constantly monitored. LED fault detection is enabled with

<EN_LED_FAULT> EEPROM bit. Shorted or open LED

string is detected.

Fault is cleared by setting EN pin low or by reading the fault

DEVICE THERMAL REGULATION

If LED fault is detected:

LP8545 has an internal temperature sensor which can be

used to measure the junction temperature of the device and

protect the device from overheating. During thermal regula-

tion, LED PWM is reduced by 2% of full scale per °C whenever

the temperature threshold is reached. Temperature regula-

tion is enabled automatically when chip is enabled. 11-bit

temperature value can be read from Temp MSB and Temp

LSB registers, MSB should be read first. Temperature limit

can be programmed in EEPROM as shown in the following

table.

•

The corresponding LED string is taken out of boost

adaptive control loop;

•

Fault bits are set in the fault register to identify whether the

fault has been open/short and how many strings are faulty;

and

•

Fault open-drain pin is pulled down.

LED fault sensitivity can be adjusted with <LED_FAULT_THR

[1:0]> EEPROM bits which sets the allowable variation be-

tween LED output voltage from 2.3V to 5.3V. Depending on

application and how much variation there can be in normal

operation between LED string forward voltages this setting

can be adjusted.

Thermal regulation function does not generate fault signal.

TEMP_LIM[1:0]

Over-Temp Limit (°C)

OFF

110

120

130

Fault is cleared by setting EN pin low or by reading the fault

UNDER-VOLTAGE DETECTION

LP8545 has detection for too-low VIN voltage. Threshold level

for the voltage is set with EEPROM register bits as seen in

the following table:

THERMAL SHUTDOWN

If the LP8545 reaches thermal shutdown temperature (150°

C ) the LED outputs and boost will shut down to protect it from

damage. Also the fault pin will be pulled down to indicate the

fault state. Device will activate again when temperature drops

below 130°C degrees.

UVLO[1:0]

Threshold (V)

OFF

2.7V

5.7V

Fault is cleared by setting EN pin low or by reading the fault

8.7V

When under voltage is detected the LED outputs and boost

will shutdown, FAULT pin is pulled down and corresponding

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transfer both command/control information and data using the

synchronous serial clock.

I²C Compatible Serial Bus Interface

INTERFACE BUS OVERVIEW

The I²C-compatible synchronous serial interface provides ac-

cess to the programmable functions and registers on the

device. This protocol uses a two-wire interface for bidirec-

tional communications between the IC's connected to the bus.

The two interface lines are the Serial Data Line (SDA) and the

Serial Clock Line (SCLK). These lines should be connected

to a positive supply, via a pull-up resistor and remain HIGH

even when the bus is idle.

Every device on the bus is assigned a unique address and

acts as either a Master or a Slave depending on whether it

generates or receives the SCLK. The LP8545 is always a

slave device.

30108449

Bit Transfer

Each data transaction is composed of a Start Condition, a

number of byte transfers (set by the software) and a Stop

Condition to terminate the transaction. Every byte written to

the SDA bus must be 8 bits long and is transferred with the

most significant bit first. After each byte, an Acknowledge sig-

nal must follow. The following sections provide further details

of this process.

DATA TRANSACTIONS

One data bit is transferred during each clock pulse. Data is

sampled during the high state of the serial clock SCLK. Con-

sequently, throughout the clock’s high period, the data should

remain stable. Any changes on the SDA line during the high

state of the SCLK and in the middle of a transaction, aborts

the current transaction. New data should be sent during the

low SCLK state. This protocol permits a single data line to

30108420

Start and Stop

The Master device on the bus always generates the Start and

Stop Conditions (control codes). After a Start Condition is

generated, the bus is considered busy and it retains this sta-

tus until a certain time after a Stop Condition is generated. A

high-to-low transition of the data line (SDA) while the clock

(SCLK) is high indicates a Start Condition. A low-to-high tran-

sition of the SDA line while the SCLK is high indicates a Stop

Condition.

In addition to the first Start Condition, a repeated Start Con-

dition can be generated in the middle of a transaction. This

allows another device to be accessed, or a register read cycle.

ACKNOWLEDGE CYCLE

The Acknowledge Cycle consists of two signals: the acknowl-

edge clock pulse the master sends with each byte transferred,

and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the

ninth clock pulse of the byte transfer. The transmitter releases

the SDA line (permits it to go high) to allow the receiver to

send the acknowledge signal. The receiver must pull down

the SDA line during the acknowledge clock pulse and ensure

that SDA remains low during the high period of the clock

pulse, thus signaling the correct reception of the last data byte

and its readiness to receive the next byte.

“ACKNOWLEDGE AFTER EVERY BYTE” RULE

The master generates an acknowledge clock pulse after each

byte transfer. The receiver sends an acknowledge signal after

every byte received.

30108450

There is one exception to the “acknowledge after every byte”

rule. When the master is the receiver, it must indicate to the

transmitter an end of data by not-acknowledging (“negative

acknowledge”) the last byte clocked out of the slave. This

Start and Stop Conditions

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“negative acknowledge” still includes the acknowledge clock

pulse (generated by the master), but the SDA line is not pulled

down.

Control Register Read Cycle

•

Master device generates a start condition.

Master device sends slave address (7 bits) and the data

direction bit (r/w = 0).

ADDRESSING TRANSFER FORMATS

•

Slave device sends acknowledge signal if the slave

address is correct.

Each device on the bus has a unique slave address. The

LP8545 operates as a slave device with 7-bit address com-

bined with data direction bit. Slave address is 2Ch as 7-bit or

58h for write and 59h for read in 8-bit format.

•

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master device generates repeated start condition.

Master sends the slave address (7 bits) and the data

direction bit (r/w = 1).

Before any data is transmitted, the master transmits the ad-

dress of the slave being addressed. The slave device should

send an acknowledge signal on the SDA line, once it recog-

nizes its address.

•

Slave sends acknowledge signal if the slave address is

correct.

The slave address is the first seven bits after a Start Condi-

tion. The direction of the data transfer (R/W) depends on the

bit sent after the slave address — the eighth bit.

•

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the control

sends data byte from addressed register.

When the slave address is sent, each device in the system

compares this slave address with its own. If there is a match,

the device considers itself addressed and sends an acknowl-

edge signal. Depending upon the state of the R/W bit (1:read,

0:write), the device acts as a transmitter or a receiver.

•

Read cycle ends when the master does not generate

acknowledge signal after data byte and generates stop

condition.

Data Read and Write Cycles

Address Mode

I²C Chip Address

<Slave Address><r/w = 0>[Ack]

<Register Addr.>[Ack]

Data Read

<Slave Address><r/w = 1>[Ack]

[Register Data]<Ack or NAck>

… additional reads from subsequent

30108451

Control Register Write Cycle

•

Master device generates start condition.

Master device sends slave address (7 bits) and the data

direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave

address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master sends data byte to be written to the addressed

Slave sends acknowledge signal.

If master will send further data bytes the control register

address will be incremented by one after acknowledge

signal.

•

<Slave Address><r/w=’0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent

•

Data Write

•

<>Data from master [ ] Data from slave

•

Write cycle ends when the master creates stop condition.

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30108447

30108495

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Recommended External Components

INDUCTOR SELECTION

reduce the effective capacitance by up to 80%, which needs

to be considered in capacitance value selection. For light

loads a 4.7 µF capacitor is sufficient. Effectively the capaci-

tance should be 4 µF for < 150 mA loads. For maximum output

voltage/current 10 µF capacitor (or two 4.7 µF capacitors) is

recommended to minimize the output ripple. For high output

voltage (55V) application 100V voltage rating capacitors

should be used. 2 x 2.2 µF capacitors are enough.

There are two main considerations when choosing an induc-

tor; the inductor should not saturate, and the inductor current

ripple should be small enough to achieve the desired output

voltage ripple. Different saturation current rating specifica-

tions are followed by different manufacturers so attention

must be given to details. Saturation current ratings are typi-

cally specified at 25°C. However, ratings at the maximum

ambient temperature of application should be requested from

the manufacturer. Shielded inductors radiate less noise and

should be preferred.

LDO CAPACITOR

A 1µF ceramic capacitor with 10V voltage rating is recom-

mended for the LDO capacitor.

The saturation current should be greater than the sum of the

maximum load current and the worst case average to peak

inductor current.

OUTPUT DIODE

A Schottky diode should be used for the output diode. Peak

repetitive current should be greater than inductor peak current

(2.5A) to ensure reliable operation. Average current rating

should be greater than the maximum output current. Schottky

diodes with a low forward drop and fast switching speeds are

ideal for increasing efficiency in portable applications.

Choose a reverse breakdown voltage of the Schottky diode

significantly larger (~60V) than the output voltage. Do not use

ordinary rectifier diodes, since slow switching speeds and

long recovery times cause the efficiency and the load regu-

lation to suffer.

The equation below shows the worst case conditions.

BOOST CONVERTER TRANSISTOR

FET transistor with high enough voltage rating (VDS at least

60V) should be used. Current rating for the FET should be the

same as inductor peak current (2.5A with highest pro-

grammed inductor current). Gate drive voltage for the FET is

5V.

• I_RIPPLE: Average to peak inductor current

• I_OUTMAX: Maximum load current

• V_IN: Maximum input voltage in application

• L: Min inductor value including worst case tolerances

• f: Minimum switching frequency

RESISTOR DIVIDER FOR THE BOOST FEEDBACK

• D: Duty cycle for CCM Operation

• V_OUT: Output voltage

Recommended values for feedback resistor divider to get 55V

boost output voltage are R₁= 63.4 kΩ and R₂= 59 kΩ. Re-

sistor values can be fine tuned to get desired maximum boost

output voltage based on how many LEDs are driven in series

and what are the forward voltage specifications for the LEDs.

Voltage on FB pin must not exceed 40V any time.

Example using above equations:

•

V_IN= 12V

V_OUT= 38V

I_OUT= 400 mA

L = 15 µH − 20% = 12 µH

f = 1.25 MHz

RESISTORS FOR SETTING THE LED CURRENT AND

PWM FREQUENCY

I_SAT= 1.6A

See EEPROM register description on how to select values for

these resistors

As a result the inductor should be selected according to the

I_SAT. A more conservative and recommended approach is to

choose an inductor that has a saturation current rating greater

than the maximum current limit of 2.5A. A 15 μH inductor with

a saturation current rating of 2.5A is recommended for most

applications. The inductor’s resistance should be less than

300 mΩ for good efficiency. For high efficiency choose an in-

ductor with high frequency core material such as ferrite to

reduce core losses. To minimize radiated noise, use shielded

core inductor. Inductor should be placed as close to the SW

pin and the IC as possible. Special care should be used when

designing the PCB layout to minimize radiated noise and to

get good performance from the boost converter.

FILTER COMPONENT VALUES

Optimal components for 60 Hz V_SYNCfrequency and 4 Hz cut-

off frequency of the low-pass filter are shown in the typical

application diagrams and in the figure below. If 2 Hz cut-off

frequency i.e. slower response time is desired, filter compo-

nents are: C₁= 1 µF, C₂= 10 µF and R = 47 kΩ. If different

V_SYNCfrequency or response time is desired, please contact

National Semiconductor representative for guidance.

OUTPUT CAPACITOR

A ceramic capacitor with 50V voltage rating or higher is rec-

ommended for the output capacitor. The DC-bias effect can

30108481

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BRIGHTNESS CONTROL

Address 00h

Reset value 0000 0000b

Brightness Control register

BRT[7:0]

Name

BRT

Bit

Access

R/W

Description

Backlight PWM 8-bit linear control.

7:0

DEVICE CONTROL

Address 01h

Reset value 0000 0000b

Device Control register

BRT_MODE[1:0]

BL_CTL

Name

Bit

Access

R/W

Description

BRT_MODE

2:1

PWM source mode

00b = PWM input pin duty cycle control (default)

01b = PWM input pin duty cycle control

10b = Brightness register

11b = Direct PWM control from PWM input pin

Enable backlight

BL_CTL

R/W

0 = Backlight disabled and chip turned off if BRT_MODE[1:0] = 10. In external

PWM pin control the state of the chip is defined with the PWM pin and this bit

has no effect.

1 = Backlight enabled and chip turned on if BRT_MODE[1:0] = 10. In external

PWM pin control the state of the chip is defined with the PWM pin and this bit

has no effect.

FAULT

Address 02h

Reset value 0000 0000b

Fault register

OPEN

SHORT

2_CHANNELS

1_CHANNEL

BL_FAULT

OCP

TSD

UVLO

Name

OPEN

Bit

Access

Description

LED open fault detection

0 = No fault

1 = LED open fault detected. Fault pin is pulled to GND. Fault is cleared by

reading the register 02h or setting EN pin low.

SHORT

LED short fault detection

0 = No fault

1 = LED short fault detected. Fault pin is pulled to GND. Fault is cleared by

reading the register 02h or setting EN pin low.

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Fault register

2_CHANNEL

LED fault detection

0 = No fault

1 = 2 or more channels have generated either short or open fault. Fault pin is

pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low.

1_CHANNEL

BL_FAULT

LED fault detection

0 = No fault

1 = 1 channel has generated either short or open fault. Fault pin is pulled to GND.

Fault is cleared by reading the register 02h or setting EN pin low.

LED fault detection

0 = No fault

1 = LED fault detected. Generated with OR function of all LED faults. Fault pin

is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin

low.

OCP

Over current protection

0 = No fault

1 = Over current detected in boost output. OCP detection block monitors the

boost output and if the boost output has been too low for more than 50 ms it will

generate OCP fault and disable the boost. Fault pin is pulled to GND. Fault is

cleared by reading the register 02h or setting EN pin low. After clearing the fault

boost will startup again.

TSD

Thermal shutdown

0 = No fault

1 = Thermal fault generated, 150°C reached. Boost converted and LED outputs

will be disabled until the temperature has dropped down to 130°C. Fault pin is

pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low.

UVLO

Under voltage detection

0 = No fault

1 = Under voltage detected in VIN pin. Boost converted and LED outputs will be

disabled until V_INvoltage is above the threshold voltage. Threshold voltage is

set with EEPROM bits from 3V...9V. Fault pin is pulled to GND. Fault is cleared

by reading the register 02h or setting EN pin low.

IDENTIFICATION

Address 03h

Reset value 1111 1100b

Identification register

PANEL

MFG[3:0]

REV[2:0]

Name

PANEL

MFG

Bit

Access

Description

Panel ID code

6:3

2:0

Manufacturer ID code

Revision ID code

REV

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DIRECT CONTROL

Address 04h

Reset value 0000 0000b

Direct Control register

OUT[6:1]

Name

OUT

Bit

Access

R/W

Description

5:0

Direct control of the LED outputs

0 = Normal operation. LED output are controlled with PWM.

1 = LED output is forced to 100% PWM.

TEMP MSB

Address 05h

Reset value 0000 0000b

Temp MSB register

TEMP[10:3]

Name

TEMP

Bit

Access

Description

7:0

Device internal temperature sensor reading first 8 MSB. MSB must be read before

LSB, because reading of MSB register latches the data.

TEMP LSB

Address 06h

Reset value 0000 0000b

Temp LSB register

TEMP[2:0]

Name

TEMP

Bit

Access

Description

7:5

Device internal temperature sensor reading last 3 LSB. MSB must be read before

LSB, because reading of MSB register latches the data.

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EEPROM CONTROL

Address 72h

Reset value 0000 0000b

EEPROM Control register

EE_READY

EE_INIT

EE_PROG

EE_READ

Name

Bit

Access

Description

EE_READY

EEPROM ready

0 = EEPROM programming or read in progress

1 = EEPROM ready, not busy

EE_INIT

R/W

EEPROM initialization bit. This bit must be written 1 before EEPROM read or

programming.

EE_PROG

EEPROM programming.

0 = Normal operation

1 = Start the EEPROM programming sequence. EE_INIT must be written 1

before EEPROM programming can be started. Programs data currently in the

EEPROM registers to non volatile memory (NVM). Programming sequence

takes about 200 ms. Programming voltage is generated inside the chip.

EE_READ

R/W

EEPROM read

0 = Normal operation

1 = Reads the data from NVM to the EEPROM registers. Can be used to

restore default values if EEPROM registers are changed during testing.

Programming sequence (program data permanently from registers to NVM):

1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h)

2. Write data to EEPROM registers (address A0h…A7h).

3. Write EE_INIT to 1 in address 72h. (04h to address 72h).

4. Write EE_PROG to 1 and EE_INIT to 0 in address 72h. (02h to address 72h).

5. Wait 200 ms.

6. Write EE_PROG to 0 in address 72h. (00h to address 72h).

Read sequence (load data from NVM to registers):

1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h).

2. Write EE_INIT to 1 in address 72h. (04h to address 72h).

3. Write EE_READ to 1 and EE_INIT to 0 in address 72h. (01h to address 72h).

4. Wait 200 ms.

5. Write EE_READ to 0 in address 72h. (00h to address 72h).

Note: Data written to EEPROM registers is effective immediately even if the EEPROM programming sequence has not been done.

When power is turned off, the device will however lose the data if it is not programmed to the NVM. During startup device auto-

matically loads the data from NVM to registers.

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EEPROM Bit Explanations

EEPROM Default Values

ADDR

A0H

A1H

A2H

A3H

A4H

A5H

A6H

A7H

LP8545SQX

0111 1111

1011 0101

1010 1111

0111 1011

0010 1000

1100 1111

0110 0100

0010 1101

EEPROM ADDRESS 0

Address A0h

EEPROM ADDRESS 0 register

CURRENT[7:0]

Name

Bit

Access

R/W

Description

CURRENT

7:0

Backlight current adjustment. If EN_I_RES = 0 the maximum backlight current is

defined only with these bits as described below. If EN_I_RES = 1, then the

external resistor connected to ISET pin also scales the LED current. With 16

kΩ resistor and CURRENT set to 7FH the output current is then 23 mA.

EN_I_RES = 0

0 mA

EN_I_RES = 1

0 mA

0000 0000

0000 0001

0000 0010

...

0.12 mA

0.24 mA

...

(1/255) x 600 x 1.23V/R_ISET

(2/255) x 600 x 1.23V/R_ISET

...

0111 1111 (default)

...

15.00 mA

...

(127/255) x 600 x 1.23V/R_ISET

...

1111 1101

1111 1110

1111 1111

29.76 mA

29.88 mA

30.00 mA

(253/255) x 600 x 1.23V/R_ISET

(254/255) x 600 x 1.23V/R_ISET

(255/255) x 600 x 1.23V/R_ISET

EEPROM ADDRESS 1

Address A1h

EEPROM ADDRESS 1 register

BOOST_FREQ[1:0]

EN_LED_FAULT

TEMP_LIM[1:0]

SLOPE[2:0]

Name

Bit

Access

R/W

Description

BOOST_FREQ

7:6

Boost Converter Switch Frequency

00 = 156 kHz

01 = 312 kHz

10 = 625 kHz

11 = 1250 kHz

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EEPROM ADDRESS 1 register

EN_LED_FAULT

R/W

Enable LED fault detection

0 = LED fault detection disabled

1 = LED fault detection enabled

Thermal deration function temperature threshold

00 = thermal deration function disabled

01 = 110°C

TEMP_LIM

4:3

10 = 120°C

11 = 130°C

SLOPE

2:0

R/W

Slope time for brightness change

000 = Slope function disabled, immediate brightness change

001 = 50 ms

010 = 75 ms

011 = 100 ms

100 = 150 ms

101 = 200 ms

110 = 300 ms

111 = 500 ms

EEPROM ADDRESS 2

Address A2h

EEPROM ADDRESS 2 register

ADAPTIVE_SPEED[1:0]

ADV_SLO EN_EXT_FET EN_ADAPT

EN_BOOST

BOOST_IMAX[1:0]

Name

Bit

Access Description

ADAPTIVE

SPEED[1]

R/W

Boost converter adaptive control speed adjustment

0 = Normal mode

1 = Adaptive mode optimized for light loads. Activating this helps the voltage

droop with light loads during boost / backlight startup.

ADAPTIVE

SPEED[0]

R/W

Boost converter adaptive control speed adjustment

0 = Adjust boost once for each phase shift cycle or normal PWM cycle

1 = Adjust boost every 16th phase shift cycle or normal PWM cycle

ADV_SLOPE

Advanced slope

0 = Advanced slope is disabled

1 = Use advanced slope for brightness change to make brightness changes

smooth for eye

EN_EXT_FET

EN_ADAPT

R/W

Enable external FET gate driver

0 = Internal FET used

1 = External FET used and GD pin used for driving the external FET gate

Enable boost converter adaptive mode

0 = adaptive mode disabled, boost converter output voltage is set with

VBOOST EEPROM register bits

1 = adaptive mode enabled. Boost converter startup voltage is set with

VBOOST EEPROM register bits, and after startup voltage is reached the

boost converter will adapt to the highest LED string V_F. LED driver output

headroom is set with DRV_HEADR EEPROM control bits.

EN_BOOST

R/W

Enable boost converter

0 = boost is disabled

1 = boost is enabled and will turn on automatically when backlight is enabled

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EEPROM ADDRESS 2 register

BOOST_IMAX

1:0

R/W

Boost converter inductor maximum current

00 = 0.9A

01 = 1.4A

10 = 2.0A

11 = 2.5A (recommended)

EEPROM ADDRESS 3

Address A3h

EEPROM ADDRESS 3 register

UVLO[1:0]

EN_PSPWM

PWM_FREQ[4:0]

Name

UVLO

Bit

Access

R/W

Description

00 = Disabled

01 = 2.7V

10 = 6V

7:6

11 = 9V

EN_PSPWM

PWM_FREQ

R/W

Enable phase shift PWM scheme

0 = phase shift PWM disabled, normal PWM mode used

1 = phase shift PWM enabled

4:0

PWM output frequency setting. See pg. 15 for full description of

selectable PWM frequencies.

EEPROM ADDRESS 4

Address A4h

EEPROM ADDRESS 4 register

PWM_RESOLUTION[1:0]

EN_I_RES

LED_FAULT_THR[1:0]

DRV_HEADR[2:0]

Name

Bit

Access

R/W

Description

PWM

7:6

PWM output resolution selection. Actual resolution depends also on the

output frequency. See pg. 15 for full description.

00 = 8...10 bits (19.2 kHz...4.8 kHz)

RESOLUTION

01 = 9...11 bits (19.2 kHz... 4.8 kHz)

10 = 10...12 bits (19.2 kHz...4.8 kHz)

11 = 11...13 bits (19.2 kHz...4.8 kHz)

EN_I_RES

R/W

Enable LED current set resistor

0 = Resistor is disabled and current is set only with CURRENT EEPROM

1 = Enable LED current set resistor. LED current is defined by the R_ISET

resistor and the CURRENT EEPROM register bits.

LED_FAULT_T

4:3

LED fault detector thresholds. V_SATis the saturation voltage of the driver,

typically 200 mV.

00 = 2.3V

01 = 3.3V

10 = 4.3V

11 = 5.3V

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EEPROM ADDRESS 4 register

DRV_HEADR

2:0

R/W

LED output driver headroom control. V_SATis the saturation voltage of the

driver, typically 200 mV.

000 = V_SAT+ 125 mV

001 = V_SAT+ 250 mV

010 = V_SAT+ 375 mV

011 = V_SAT+ 500 mV

100 = V_SAT+ 625 mV

101 = V_SAT+ 750 mV

110 = V_SAT+ 875 mV

111 = V_SAT+ 1000 mV

EEPROM ADDRESS 5

Address A5h

EEPROM ADDRESS 5 register

EN_VSYNC

DITHER[1:0]

VBOOST[4:0]

Name

Bit

Access

R/W

Description

EN_VSYNC

Enable V_SYNCfunction

0 = V_SYNCinput disabled

1 = V_SYNCinput enabled. V_SYNCsignal is used by the internal PLL to generate

PWM output and boost frequency.

DITHER

6:5

4:0

R/W

Dither function controls

00 = Dither function disabled

01 = 1-bit dither used for output PWM transitions

10 = 2-bit dither used for output PWM transitions

11 = 3-bit dither used for output PWM transitions

VBOOST

Boost voltage control from 10V to 40V with 1V step (without FB resistor

divider). If adaptive boost control is enabled, this sets the initial start voltage

for the boost converter. If adaptive mode is disabled, this will directly set the

output voltage of the boost converter.

0 0000 = 10V

0 0001 = 11V

0 0010 = 12V

...

1 1101 = 39V

1 1110 = 40V

1 1111 = 40V

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EEPROM ADDRESS 6

Address A6h

EEPROM ADDRESS 6 register

PLL[12:5]

Name

PLL

Bit

Access

R/W

Description

7:0

13-bit counter value for PLL, 8 MSB bits. PLL[12:0] bits are used when

en_vsync = 1. See table below for PLL value calculation.

EEPROM ADDRESS 7

Address A7h

EEPROM ADDRESS 7 register

PLL[4:0]

EN_F_RES

HYSTERESIS[1:0]

Name

PLL

Bit

Access

R/W

Description

7:3

13-bit counter value for PLL, 5 LSB bits. PLL[12:0] bits are used when en_vsync =

1. See table below for PLL value calculation.

EN_F_RES

R/W

Enable PWM output frequency set resistor

0 = Resistor is disabled and PWM output frequency is set with PWM_FREQ

EEPROM register bits

1 = PWM frequency set resistor is enabled. R_FSETdefines the output PWM frequency.

See pg. 15 for full description of the PWM frequencies.

HYSTERESIS

1:0

R/W

PWM input hysteresis function. Will define how small changes in the PWM input are

ignored to remove constant switching between two values.

00 = OFF

01 = 1-bit hysteresis with 11-bit resolution

10 = 1-bit hysteresis with 10-bit resolution

11 = 1-bit hysteresis with 8-bit resolution

PLL value calculation

en_vsync

PLL frequency [MHz]

PLL[12:0]

not used

5, 10, 20, 40

5 MHz / (26 x f_VSYNC)

10 MHz / (50 x f_VSYNC

20 MHz / (98 x f_VSYNC

)

40 MHz / (196 x f_VSYNC

)

PLL frequency is set by PWM_RESOLUTION[1:0] bits.

For Example:

If f_PLL= 5 MHz and f_VSYNC= 60 Hz, then PLL[12:0] = 5000000 Hz / (26 * 60 Hz) = 3205d = C85h.

If f_PLL= 10 MHz and f_VSYNC= 75 Hz, then PLL[12:0] = 10000000 Hz / (50 * 75 Hz) = 2667d = A6Bh.

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Physical Dimensions inches (millimeters) unless otherwise noted

SQA24A: LLP-24, 0.5mm pitch, no pullback

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Notes

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LP8545SQX/NOPB CAD模型

原理图符号

PCB 封装图

LP8545SQX/NOPB 替代型号

型号	制造商	描述	替代类型	文档
LP8545SQE/NOPB	TI	Six channel high-efficiency LED backlight driver for notebooks with flexible ext/int FET c	类似代替

LP8545SQX/NOPB 相关器件

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LP8551	TI	High-Efficiency LED Backlight Driver for Notebooks	获取价格
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