Verilog Tutorial (Part 2)

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A simple example (comb. circuit)

Let's design a 1 bit full adder (RTL style)

a b cin cout

FA
s

module FA( input a, b, cin, output s, cout); assign s = a ^ b ^ c; assign cout = (a & b) | (a & cin) | (b & cin); endmodule

Ok, but what if we want more than 1 bit FA?

Adapted from Arvind & Asanovics MIT 6.375 lecture
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A simple D flip flop (seq. circuit)

For sequential circuits, use always blocks Always blocks (and assign) are executed in parallel!
module DFF( input clk, d, output q, q_bar); reg q, q_bar; always @ (posedge clk) // triggered on the rising edge of the clock begin q <= d; // non-blocking assignment (LHS not updated until later) q_bar <= ~d; /* q_bar <= ~q will not function correctly! Why not? */ end endmodule
Adapted from Arvind & Asanovics MIT 6.375 lecture
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Always blocks in comb. circuits

Can use continual assignment OR always blocks for combinational circuits Our 1-bit adder using always block
module FA( input a, b, cin, output s, cout); reg s, cout; // when using always block, LHS must be reg type always @ ( * ) // for comb circuits, use * so avoid errors begin s = a ^ b ^ cin; // use blocking assignment here (LHS immediately) cout = (a & b) | (a & cin) | (b & cin); end endmodule
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Blocking vs. non-blocking assignment

Order of blocking statements matter

These
c = a + b; d = c + e;

are not the same

d = c + e; c = a + b;

Order of non-blocking statements doesnt

These

are the same

c <= a + b; d <= c + e; d <= c + e; c <= a + b;

Use non-blocking with sequential, blocking with combinational

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Blocking vs. Non-blocking assignments

Order of blocking statements matters assume a = 1, b = 2, c = 4, d = 4, e = 5 initially
// ex1 c = a + b; d = c + e; //ex2 d = c + e; c = a + b;

Order of non-blocking statements doesnt Example: (same assumptions)

// ex1 c <= a + b; d <= c + e; //ex2 d <= c + e; c <= a + b;

Ex1: c = 3 , d = 8 Ex2: c = 3 , d = 9

Ex1: c = 3 , d = 9 Ex2: c = 3 , d = 9

Guideline: Use blocking for combination, non-blocking for sequential

Verilog Simulation Behavior

Always blocks and assign statements execute in parallel

Signals

in sensitivity list (@()) trigger always

blocks Assign trigged when RHS signal changes

Non-blocking assignment is 2-step processes

Step

1: Evaluate RHS (beginning of time step) Step 2: Update LHS (end of time step)

Tips for maintaining synthesizability

Only leaf modules should have functionality

All other modules are strictly structural, i.e., they only wire together sub-modules

Use only positive-edge triggered flip-flops for state Do not assign to the same variable from more than one always block Separate combinational logic from sequential logic Avoid loops like the plague

Use for and while loops only for test benches

Adapted from Arvind & Asanovics MIT 6.375 lecture

Data Types in Verilog

Basic type: bit vector

Values:

0, 1, X (don't care), Z (high impedence)

Bit vectors expressed in multiple ways:

binary:

4'b11_10 ( _ is just for readability) hex: 16'h034f decimal: 32'd270 other formats but these are the most useful
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Data types (continued)

Connect things together with wires

Single

wire: of wires

wire my_wire; wire[7:0] my_wire;

Array

Why not wire[0:7]?

For always blocks, must use reg type

Single

reg or an array of reg

reg[3:0] accum; // 4 bit reg

reg

is not necessarily a hardware register

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Verilog RTL Operators

Arithmetic Logical Relational Equality Bitwise
+ - * / % ** ! && || > < >= <= == != === !=== ~ & | ^ ^~

Reduction Shift Concatenation Conditional

& ~& | ~| ^ ^~ >> << >>> <<< { } ?:

Avoid using %, **, and / because you'll run into problems when trying to synthesis

Adapted from Arvind & Asanovics MIT 6.375 lecture

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Mystery Combinational Circuit

We can use case statements within an always block What hardware will this turn into?

module mystery( input a, b, c, d, input [1:0] sel, output out ); reg out; always @( * ) begin case ( sel ) 2d0 : out = a; 2d1 : out = b; 2d2 : out = c; 2d3 : out = d; default : out = 1bx; endcase end endmodule
Adapted from Arvind & Asanovics MIT 6.375 lecture
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Finite State Machines (FSMs)

Useful for designing many different types of circuits 3 basic components:

Combinational

logic (next state) Sequential logic (store state) Output logic

Different encodings for state:

Binary

(min FFs), Gray, One hot (good for FPGA), One cold, etc
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A simple FSM in Verilog

module simple_fsm( input clk, start, output restart); reg [1:0] state, next_state; parameter S0 = 2b00, S1 = 2b01, S2 = 2b10; // binary encode always @ (*) begin : next_state_logic case ( state ) S0: begin if ( start ) next_state = S1; else next_state = S0; end // continued from left S1: begin next_state = S2; end always @ (posedge clk) S2: begin begin: state_assignment if (restart) next_state = S0; state <= next_state; else next_state = S2; end end endmodule default: next_state = S0; endcase end // continued to the right

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Tips on FSMs

Dont forget to handle the default case Use two different always blocks for next state and state assignment
Can

do it in one big block but not as clear

Outputs can be a mix of combin. and seq.

Moore

Machine: Output only depends on state Mealy Machine: Output depends on state and inputs

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Next step: Design your own HW

You now have the basics of Verilog

Can

create simple circuits of teh Internetz

Combinational, Sequential, or Mixed A lot of code out there isnt synthesizable

Beware

How do the real HW designers code?

Next:

More advanced design techniques

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