Hardware Descriptive
Langaue (HDL)
Verilog
1
5 March 2020
Outline
n Verilog
¡ Structural constructs
¡ Describing combinational circuits
n Additional references
¡ “Starter’s Guide to Verilog 2001” by Michael
Ciletti copies for borrowing in hardware lab
¡ ASIC-WORLD: http://www.asic-
world.com/verilog/index.html
¡ https://sutherland-
hdl.com/pdfs/verilog_2001_ref_guide.pdf 2
Combinational design
n Step 1: Understand the problem
¡ Identify the inputs and outputs
¡ Draw a truth table
n Step 2: Simplify the logic
¡ Draw a K-map
¡ Write a simplified Boolean expression
n SOP or POS
n Use don’t cares
n Step 3: Implement the design
¡ Logic gates and/or
¡ Verilog
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Ways of specifying circuits
n Schematics
¡ Structural description
¡ Describe circuit as interconnected elements
n Build complex circuits using hierarchy
¡ Large circuits are unreadable
n Hardware description languages (HDLs)
¡ Not programming languages
n Parallel languages tailored to digital design
¡ Synthesize code to produce a circuit
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Verilog versus VHDL
n Both “IEEE standard” languages
n Most tools support both
n Verilog is “simpler”
¡ Less syntax, fewer constructs
n VHDL is more structured
¡ Can be better for large, complex systems
¡ Better modularization
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Simulation and synthesis
n Simulation
¡ Models what a circuit does
n Multiply is “*”, ignoring implementation options
¡ Allows you to test design options
¡ “Execute” a design to verify correctness
n Synthesis
¡ Converts your code to a "netlist"
n Can simulate synthesized design
¡ Tools map your netlist to hardware
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Simulation and synthesis
Gate or
HDL
Synthesis Transistor
Description
Description
Physical
Simulation Simulation
Implementation
Functional/
Functional Real
Timing
Validation Chip!
Validation
n Simulation and synthesis in the CSE curriculum
¡ CSE370: Learn simulation
¡ CSE467: Learn synthesis
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Simulation
n You provide an environment
¡ Using non-circuit constructs
n Active-HDL waveforms, read files, print
¡ Using Verilog simulation code
n A “test fixture”
Simulation
Test Fixture Circuit Description
(Specification) (Synthesizable)
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Specifying circuits in Verilog
n Three major styles A
AND2
E
OR2
g1
¡ Instances and wires B 1
3
g3 X
¡ Continuous assignments NOT
C Y
¡ “always” blocks 2 g2
“Structural” “Behavioral”
wire E; wire E; reg E, X, Y;
and g1(E,A,B); assign E = A & B; always @ (A or B or C)
not g2(Y,C); assign Y = ~C; begin
or g3(X,E,Y); assign X = E | Y; E = A & B;
Y = ~C;
X = E | Y;
end 9
Data types
n Values on a wire
¡ 0, 1, x (unknown or conflict), z (tristate or
unconnected)
n Vectors
¡ A[3:0] vector of 4 bits: A[3], A[2], A[1], A[0]
n Unsigned integer value
n Indices must be constants
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Manipulating vectors
n Concatenating bits/vectors, use { }
¡ e.g. sign extend
n B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};
n B[7:0] = {4{A[3]}, A[3:0]};
n Style: Use a[7:0] = b[7:0] + c[7:0]
Not a = b + c;
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Data types that do NOT exist
n Structures
n Pointers
n Objects
n Recursive types
Verilog is not C or Java or Lisp or …!
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Numbers
n Format: <sign><size><base><number>
n 14
¡ Decimal number
n –4’b11
¡ 4-bit 2’s complement binary of 0011 (is 1101)
n 12’b0000_0100_0110
¡ 12 bit binary number (_ is ignored)
n 12’h046
¡ 3-digit (12-bit) hexadecimal number
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Numbers are unsigned
n C[4:0] = A[3:0] + B[3:0];
¡ if A = 0110 (6) and B = 1010(–6),
then C = 10000 (not 00000)
¡ B is zero-padded, not sign-extended
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Operators
Similar to Java operators
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Two abstraction mechanisms
n Modules
¡ More structural, but also behavioral
¡ Heavily used in 370 and “real” Verilog
code
n Functions
¡ More behavioral
¡ Used to some extent in “real” Verilog, but
not much in 370
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Basic building blocks: modules
// first simple example
module simple (X,Y,A,B,C);
AND2
A OR2 input A,B,C;
E
g1 output X,Y;
B 1 g3 X
3 wire E
NOT and g1(E,A,B);
C Y not g2(Y,C);
2 g2
or g3(X,E,Y);
endmodule
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Basic building blocks: modules
n Instanced into a design n Name can’t begin with a
¡ Never called number
n Use wires for connections n Names are case sensitive
n Modules execute in parallel n Keywords are in lowercase
n Gate declarations (and, or, n and, or, not are keywords
etc) n Illegal to nest module
¡ List outputs first definitions
¡ Inputs second n // for comments
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Modules are circuit components
AND2
n Module has ports A OR2
E
g1
¡ External connections B 1 g3 X
3
¡ A,B,C,X,Y in example
NOT
n Port types C Y
¡ input 2 g2
¡ output
¡ inout (tristate) // previous example as a
// Boolean expression
n Use assign statements for
module simple2 (X,Y,A,B,C);
Boolean expressions
input A,B,C;
¡ and Û & output X,Y;
¡ or Û | assign X = (A&B)|~C;
¡ not Û ~ assign Y = ~C;
endmodule
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Structural Verilog
NOT AND2
module xor_gate (out,a,b); abar
a t1
input a,b; 4 and1
inva b 6
output out; OR2
wire abar, bbar, t1, t2; or1 out
8
not inva (abar,a); NOT
bbar
AND2
not invb (bbar,b); b 5 and2
and and1 (t1,abar,b); invb a 7 t2
and and2 (t2,bbar,a);
or or1 (out,t1,t2);
endmodule
8 basic gates (keywords):
and, or, nand, nor
buf, not, xor, xnor
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Behavioral Verilog
n Describe circuit behavior A
Adder Sum
¡ Not implementation B
Cout
Cin
module full_addr (Sum,Cout,A,B,Cin);
input A, B, Cin;
output Sum, Cout;
assign {Cout, Sum} = A + B + Cin;
endmodule
{Cout, Sum} is a concatenation
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Behavioral 4-bit adder
module add4 (SUM, OVER, A, B); Buses are implicitly connected—
input [3:0] A; If you write BUS[3:2], BUS[1:0],
input [3:0] B;
output [3:0] SUM; they become part of BUS[3:0]
output OVER;
assign {OVER, SUM[3:0]} = A[3:0] + B[3:0];
endmodule
“[3:0] A” is a 4-wire bus labeled “A”
Bit 3 is the MSB
Bit 0 is the LSB
Can also write “[0:3] A”
Bit 0 is the MSB
Bit 3 is the LSB
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Continuous assignment
n Assignment is continuously evaluated
¡ Corresponds to a logic gate
¡ Assignments execute in parallel
Boolean operators
(~ for bit-wise negation)
assign A = X | (Y & ~Z);
bits can assume four values
assign B[3:0] = 4'b01XX; (0, 1, X, Z)
variables can be n-bits wide
assign C[15:0] = 16'h00ff;
(MSB:LSB)
assign #3 {Cout, Sum[3:0]} = A[3:0] + B[3:0] + Cin;
gate delay (used by simulator) 23
Invalid sequential assigns
assign A = X | (Y & ~Z);
“Reusing” a variable on the left
assign B = W | A; side of several assign statements
is not allowed
assign A = Y & Z;
assign A = X | (Y & ~Z); Cyclic dependencies also are bad
assign B = W | A; A depends on X
which depends on B
assign X = B & Z; which depends on A
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Example: 4-bit comparator
module Compare1 (Equal, Alarger, Blarger, A, B);
input A, B;
output Equal, Alarger, Blarger;
assign Equal = (A & B) | (~A & ~B);
assign Alarger = (A & ~B);
assign Blarger = (~A & B);
endmodule
n Starting with 1-bit comparator
¡ Top-down design and bottom-up design are both okay
¡ Module ordering doesn’t matter because modules execute
in parallel
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4-bit comparator
// Make a 4-bit comparator from 4 1-bit comparators
module Compare4(Equal, Alarger, Blarger, A4, B4);
input [3:0] A4, B4;
output Equal, Alarger, Blarger;
wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3;
Compare1 cp0(e0, Al0, Bl0, A4[0], B4[0]);
Compare1 cp1(e1, Al1, Bl1, A4[1], B4[1]);
Compare1 cp2(e2, Al2, Bl2, A4[2], B4[2]);
Compare1 cp3(e3, Al3, Bl3, A4[3], B4[3]);
assign Equal = (e0 & e1 & e2 & e3);
assign Alarger = (Al3 | (Al2 & e3) |
(Al1 & e3 & e2) |
(Al0 & e3 & e2 & e1));
assign Blarger = (~Alarger & ~Equal);
endmodule
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Functions
n Use functions for complex combinational
logic
module and_gate (out, in1, in2);
input in1, in2;
output out;
assign out = myfunction(in1, in2);
function myfunction; Benefit:
input in1, in2;
Functions force a result
begin
myfunction = in1 & in2; Þ Compiler will fail if function
end does not generate a result
endfunction
endmodule 27
Always code blocks
Variables that appear
on the left hand side in
an always block must
be declared as “reg”s
reg A, B, C; Sensitivity list:
block is executed
each time one of
always @ (W or X or Y or Z) them changes value
begin
A = X | (Y & ~Z);
B = W | A; Statements in an always
A = Y & Z; block are executed in
if (A & B) begin sequence
B = Z;
C = W | Y;
end
end BAD: All variables must be
assigned on every control path!!!
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Assignments
n Blocking assignments (Q = A)
¡ Variable is assigned immediately
n New value is used by subsequent statements
n Non-blocking assignments (Q <= A)
¡ Variable is assigned after all scheduled
statements are executed
n Value to be assigned is computed but saved for later
parallel assignment
¡ Usual use: Register assignment
n Registers simultaneously take new values after the
clock edge
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Blocking vs. non-blocking
n Example: Swap
always @(posedge CLK) always @(posedge CLK)
begin begin
temp = B; A <= B;
B = A; B <= A;
A = temp; end
end
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Verilog tips
n Do not write C-code
¡ Think hardware, not algorithms
n Verilog is inherently parallel
n Compilers don’t map algorithms to circuits
well
n Do describe hardware circuits
¡ First draw a dataflow diagram
¡ Then start coding
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