Hardware Description Languages:

Verilog
Verilog

Structural Models
(Combinational) Behavioral Models
Syntax
Examples

CS 150 - Spring 2007 - Lecture

Quick History of HDLs

ISP (circa 1977) - research project at CMU

Abel (circa 1983) - developed by Data-I/O

Targeted to programmable logic devices

Not good for much more than state machines

Verilog (circa 1985) - developed by Gateway (now Cadence)

Simulation, but no synthesis

Similar to Pascal and C

Delays is only interaction with simulator
Fairly efficient and easy to write
IEEE standard

VHDL (circa 1987) - DoD sponsored standard

Similar to Ada (emphasis on re-use and maintainability)

Simulation semantics visible
Very general but verbose
IEEE standard

CS 150 - Spring 2007 - Lecture

Design Methodology
Structure and Function
(Behavior) of a Design

HDL
Specification

Simulation

Synthesis

Verification: Design
Behave as Required?
Functional: I/O Behavior
Register-Level (Architectural)
Logic-Level (Gates)
Transistor-Level (Electrical)
Timing: Waveform Behavior

Generation: Map
Specification to
Implementation

CS 150 - Spring 2007 - Lecture

Verilog/VHDL
The standard languages
Very similar
Many tools provide front-ends to both
Verilog is simpler
Less syntax, fewer constructs

VHDL supports large, complex systems

Better support for modularization
More grungy details
Hello world is much bigger in VHDL

CS 150 - Spring 2007 - Lecture

Verilog
Supports structural and behavioral descriptions
Structural

Explicit structure of the circuit

How a module is composed as an interconnection of more
primitive modules/components
E.g., each logic gate instantiated and connected to others

Behavioral

Program describes input/output behavior of circuit

Many structural implementations could have same behavior
E.g., different implementations of one Boolean function

CS 150 - Spring 2007 - Lecture

Verilog Introduction
the module describes a component in the circuit
Two ways to describe:
Structural Verilog

List of components and how they are connected

Just like schematics, but using text
Hard to write, hard to decode
Useful if you dont have integrated design tools

Behavioral Verilog
Describe what a component does, not how it does it
Synthesized into a circuit that has this behavior

CS 150 - Spring 2007 - Lecture

Structural Model
Composition of primitive gates to form more complex module
Note use of wire declaration!

module xor_gate (out, a, b);

By default, identifiers
input
a, b;
are wires
output
out;
wire
abar, bbar, t1, t2;
inverter
inverter
and_gate
and_gate
or_gate
endmodule

invA (abar, a);

invB (bbar, b);
and1 (t1, a, bbar);
and2 (t2, b, abar);
or1 (out, t1, t2);

CS 150 - Spring 2007 - Lecture

Structural Model
Example of full-adder
module full_addr (A, B, Cin, S, Cout);
input
A, B, Cin;
output
S, Cout;

Behavior

assign {Cout, S} = A + B + Cin;

endmodule
module adder4 (A, B, Cin, S, Cout);
input [3:0] A, B;
input
Cin;
output [3:0] S;
output
Cout;
wire
C1, C2, C3;
full_addr
full_addr
full_addr
full_addr
endmodule

fa0
fa1
fa2
fa3

(A[0],
(A[1],
(A[2],
(A[3],

B[0],
B[1],
B[2],
B[3],

Cin,
C1,
C2,
C3,

S[0],
S[1],
S[2],
S[3],

Structural
C1);
C2);
C3);
Cout);

CS 150 - Spring 2007 - Lecture

Simple Behavioral Model

Combinational logic
Describe output as a function of inputs
Note use of assign keyword: continuous assignment
module and_gate (out, in1, in2);
input
in1, in2;
Output port of a primitive must
output
out;
be first in the list of ports
assign out = in1 & in2;

Restriction does not apply to

modules

endmodule

CS 150 - Spring 2007 - Lecture

Verilog Module
Corresponds to a circuit component
Parameter list is the list of external connections, aka ports
Ports are declared input, output or inout
inout ports used on tri-state buses

Port declarations imply that the variables are wires

module name

ports

module full_addr (A, B, Cin, S, Cout);

input
A, B, Cin;
output
S, Cout;
assign {Cout, S} = A + B + Cin;
endmodule

CS 150 - Spring 2007 - Lecture

inputs/outputs

Verilog Continuous Assignment

Assignment is continuously evaluated
assign corresponds to a connection or a simple component with
the described function
Target is NEVER a reg variable

use of Boolean operators

(~ for bit-wise, ! for logical negation)

assign A = X | (Y & ~Z);

bits can take on four values

(0, 1, X, Z)

assign B[3:0] = 4'b01XX;

assign C[15:0] = 16'h00ff;

variables can be n-bits wide

(MSB:LSB)

assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;

use of arithmetic operator
multiple assignment (concatenation)
delay of performing computation, only used by simulator, not synthesis

CS 150 - Spring 2007 - Lecture

Comparator Example
module Compare1 (A, B, Equal, Alarger, Blarger);
input
A, B;
output
Equal, Alarger, Blarger;
assign Equal = (A & B) | (~A & ~B);
assign Alarger = (A & ~B);
assign Blarger = (~A & B);
endmodule

CS 150 - Spring 2007 - Lecture

Comparator Example
// Make a 4-bit comparator from 4 x 1-bit comparators
module Compare4(A4, B4, Equal, Alarger, Blarger);
input [3:0] A4, B4;
output Equal, Alarger, Blarger;
wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3;
Compare1
Compare1
Compare1
Compare1

cp0(A4[0],
cp1(A4[1],
cp2(A4[2],
cp3(A4[3],

B4[0],
B4[1],
B4[2],
B4[3],

e0,
e1,
e2,
e3,

assign Equal = (e0 & e1 & e2

assign Alarger = (Al3 | (Al2
(Al1 & e3 &
(Al0 & e3 &
assign Blarger = (~Alarger &
endmodule

Al0,
Al1,
Al2,
Al3,

Bl0);
Bl1);
Bl2);
Bl3);

& e3);
& e3) |
e2) |
e2 & e1));
~Equal);

CS 150 - Spring 2007 - Lecture

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CS 150 - Spring 2007 - Lecture

Simple Behavioral Model: the always

block
always block

Always waiting for a change to a trigger signal

Then executes the body
module and_gate (out, in1, in2);
input
in1, in2;
output out;
reg
out;
always @(in1 or in2) begin
out = in1 & in2;
end
endmodule

Not a real register!!

A Verilog register
Needed because of
assignment in always
block

Specifies when block is executed

I.e., triggered by which signals

CS 150 - Spring 2007 - Lecture

always Block
Procedure that describes the function of a circuit
Can contain many statements including if, for, while, case
Statements in the always block are executed sequentially
(Continuous assignments <= are executed in parallel)

Entire block is executed at once

Final result describes the function of the circuit for current
set of inputs
intermediate assignments dont matter, only the final result

begin/end used to group statements

CS 150 - Spring 2007 - Lecture

Complete Assignments
If an always block executes, and a variable is not
assigned
Variable keeps its old value (think implicit state!)
NOT combinational logic latch is inserted (implied memory)
This is usually not what you want: dangerous for the novice!

Any variable assigned in an always block should be

assigned for any (and every!) execution of the block

CS 150 - Spring 2007 - Lecture

Incomplete Triggers
Leaving out an input trigger usually results in a
sequential circuit
Example: Output of this and gate depends on the
input history
module and_gate (out, in1, in2);
input
in1, in2;
output
out;
reg
out;
always @(in1) begin
out = in1 & in2;
end
endmodule CS

150 - Spring 2007 - Lecture

Verilog if
Same as C if statement
// Simple 4:1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel;
// 2-bit control signal
input A, B, C, D;
output Y;
reg Y;
// target of assignment
always @(sel or A or B or C or D)
if (sel == 2b00) Y = A;
else if (sel == 2b01) Y = B;
else if (sel == 2b10) Y = C;
else if (sel == 2b11) Y = D;
endmodule

CS 150 - Spring 2007 - Lecture

Verilog if
Another way
// Simple 4:1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel;
// 2-bit control signal
input A, B, C, D;
output Y;
reg Y;
// target of assignment
always @(sel or A or
if (sel[0] == 0)
if (sel[1] == 0)
else
else
if (sel[1] == 0)
else
endmodule

B or C or D)
Y = A;
Y = B;
Y = C;
Y = D;

CS 150 - Spring 2007 - Lecture

Verilog case
Sequential execution of cases
Only first case that matches is executed (implicit break)
Default case can be used
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel;
// 2-bit control signal
input A, B, C, D;
output Y;
reg Y;
// target of assignment
always @(sel
case (sel)
2b00: Y
2b01: Y
2b10: Y
2b11: Y
endcase
endmodule

or A or B or C or D)
=
=
=
=

A;
B;
C;
D;

Conditions tested in
top to bottom order

CS 150 - Spring 2007 - Lecture

Verilog case
Note:
case (case_expression)
case_item1 : case_item_statement1;
case_item2 : case_item_statement2;
case_item3 : case_item_statement3;
case_item4 : case_item_statement4;
default
: case_item_statement5;
endcase
is the same as
if(case_expression == case_item1)
case_item_statement1;
else if (case_expression == case_item2)
case_item_statement2;
else if (case_expression == case_item3)
case_item_statement3;
else if (case_expression == case_item4)
case_item_statement4;
else case_item_statement5;

CS 150 - Spring 2007 - Lecture

Verilog case
Without the default case, this example would create a latch for Y
Assigning X to a variable means synthesis is free to assign any
value
// Simple binary encoder (input is 1-hot)
module encode (A, Y);
input [7:0] A;
// 8-bit input vector
output [2:0] Y;
// 3-bit encoded output
reg
[2:0] Y;
// target of assignment
always @(A)
case (A)
8b00000001:
8b00000010:
8b00000100:
8b00001000:
8b00010000:
8b00100000:
8b01000000:
8b10000000:
default:
endcase
endmodule

Y
Y
Y
Y
Y
Y
Y
Y
Y

=
=
=
=
=
=
=
=
=

0;
1;
2;
3;
4;
5;
6;
7;
3bXXX;

// Dont care when input is not 1-hot

CS 150 - Spring 2007 - Lecture

Verilog case (cont)

Cases are executed sequentially
Following implements a priority encoder
// Priority encoder
module encode (A, Y);
input [7:0] A;
output [2:0] Y;
reg
[2:0] Y;
always @(A)
case (1b1)
A[0]:
Y
A[1]:
Y
A[2]:
Y
A[3]:
Y
A[4]:
Y
A[5]:
Y
A[6]:
Y
A[7]:
Y
default: Y
endcase
endmodule

=
=
=
=
=
=
=
=
=

// 8-bit input vector

// 3-bit encoded output
// target of assignment

0;
1;
2;
3;
4;
5;
6;
7;
3bXXX;// Dont care when input is all 0s

CS 150 - Spring 2007 - Lecture

Parallel Case
A priority encoder is more expensive than a simple encoder

If we know the input is 1-hot, we can tell the synthesis tools

parallel-case pragma says the order of cases does not matter

// simple encoder
module encode (A, Y);
input [7:0] A;
output [2:0] Y;
reg
[2:0] Y;
always @(A)
case (1b1)
A[0]:
Y
A[1]:
Y
A[2]:
Y
A[3]:
Y
A[4]:
Y
A[5]:
Y
A[6]:
Y
A[7]:
Y
default: Y
endcase
endmodule

// 8-bit input vector

// 3-bit encoded output
// target of assignment
// synthesis parallel-case

=
=
=
=
=
=
=
=
=

0;
1;
2;
3;
4;
5;
6;
7;
3bX;

// Dont care when input is all 0s

CS 150 - Spring 2007 - Lecture

casex Example
// Priority encoder
module encode (A, valid, Y);
input [7:0] A;
output [2:0] Y;
output valid;
reg
[2:0] Y;
reg
valid;
always @(A) begin
valid = 1;
casex (A)
8bXXXXXXX1: Y =
8bXXXXXX10: Y =
8bXXXXX100: Y =
8bXXXX1000: Y =
8bXXX10000: Y =
8bXX100000: Y =
8bX1000000: Y =
8b10000000: Y =
default: begin
valid = 0;
Y = 3bX; //
end
endcase
end
endmodule

//
//
//
//

8-bit input vector

3-bit encoded output
Asserted when an input is not all 0s
target of assignment

0;
1;
2;
3;
4;
5;
6;
7;
Dont care when input is all 0s

CS 150 - Spring 2007 - Lecture