Introduction to Digital Design with Verilog

Mazen A. R. Saghir

Department of Electrical and Computer Engineering

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 1 / 51
Modules

Modules are the basic building blocks of Verilog models.

– Similar to functions in Python or C++.
– Can be used to model simple circuits or complex systems made up of
other (sub)modules.

A module describes a circuit’s interface, behavior, and/or structure.

– The interface specifies a circuit’s input and output ports.
– Circuit behavior is modeled using concurrent assignment or
procedural statements.
– Circuit structure is modeled using instances of other modules and
interconnection elements.
– Internal module elements are connected by virtual wires or data
storage elements called registers.
– Modules may also include integer or real variables.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 2 / 51
Module syntax

module module_name (port_list);

// module items
endmodule

Names are case-sensitive. Example: mux and Mux are different

names. A name must start with a letter and may only contain letters,
digits, and the underscore symbol.
The port list contains a comma-separated list of input and output
ports.
– By default, each port is a signal-carrying wire or group of wires called
a vector.
– A wire can carry a single bit; a vector can carry multiple bits.
– Ports may also store signals in which case they are declared as
registers.
Module items include declarations, assignments, and other module
instantiations.
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 3 / 51
Example: mux2to1

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 4 / 51
Module declarations module module_name (port_list);
// module items
endmodule

A module maymodule
includemodule_name
a number of(port_list);
signal declarations. The syntax of
// module items
a declaration is:
endmodule
<type> name;
<type> name;
Examples:
wire node1; // wire signal
reg Q0, Q1, Q2; // three register signals
wire [63:0] bus1; // 64-bit wire vector signal
reg [7:0] count; // 8-bit register vector signal
integer i, j; // integer variables

assign signal_name = value;

assign F1 = A & B; // assigns F1 the value of A & B

assign F2
M. Saghir (EECE 320 – Summer 2023) = 1’b0;
Introduction // Design
to Digital assigns F2 a
single bit = 0
with Verilog 5 / 51
 <type> name;
Module assignments
<type> name;
wire node1; // wire signal
reg Q0, Q1, Q2; // three register signals
wire node1;
A continuous wire // [63:0]
assignment wire
is a signal
bus1; // wire
concurrent vector signal
statement that assigns
reg Q0, Q1, Q2; //
integer three
i, j; register signals
// integer variables
the value of an expression or a constant to a signal. It has the
wire [63:0] bus1; // wire vector signal
followinginteger
syntax:
i, j; // integer variables
assign signal_name = value;
assign signal_name = value;
Examples: assign F1 = A & B; // assigns F1 the value of A & B
assign F1 = A assign F2 = 1’b0;
& B; // assigns F1 the//value
assigns
of AF2
&Ba single bit = 0
assign F2 = 1’b0; // assigns F2 a single bit = 0 an 8-bit value = 1010
assign F3 = 8’hAA; // assigns F3
assign F3 = 8’hAA; // assigns F3 an 8-bit value = 10101010

Continuous assignment statements are evaluated any time a value in

the right-hand side of the assignment changes.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 6 / 51
 integer i, j; // integer variables
assign signal_name = value;
Numbers
assign signal_name = value;
assign F1 = A & B; // assigns F1 the value of A & B
assign F2 = 1’b0; // assigns F2 a single bit = 0
assign
assign
By default, numbers are F1==as
F3
treated A &32-bit
B; // assigns
8’hAA; assigns F1 the
an value
F3However,
integers. ofVerilog
A & =B 10101
8-bit value
assign F2 = 1’b0; // assigns F2 a single bit = 0
enables numbers to beassign
specified
F3 = in different
8’hAA; bases
// assigns F3 and bit value
an 8-bit widths:
= 1010101
<size_in_bits>’<base><value>
<size_in_bits>’<base><value>
Numbers can be specified
‘b in the following
unsigned binary bases:
‘o’b unsigned
unsigned octal
binary
‘d’o unsigned
unsigned decimal
octal
‘h’d unsigned
unsigned hexadecimal
decimal
‘sb
’h signed binary
unsigned hexadecimal
‘so
’sb signed
signed octal
binary
‘sd
’so signed
signed decimal
octal
‘sh
’sd signed
signed hexadecimal
decimal
’sh signed hexadecimal

10 // 32-bit value = 10 (decimal)

10
4’b1111 // 32-bit
// value == 1111
4-bit value 10 (decimal)
4’b1111
8’b1101_0000 // 4-bit value = 1111
// 8-bit value = 11010000
M. Saghir (EECE 320 – Summer 2023) 8’b1101_0000
8’hFF
Introduction //Verilog
to Digital Design with// 8-bit
8-bit value
value==11010000
11111111 7 / 51
 ’d unsigned decimal
Numbers (2)’h
’sb
unsigned hexadecimal
signed binary
’so signed octal
’sd signed decimal
’sh signed hexadecimal
Examples:
10 // 32-bit value = 10 (decimal)
4’b1111 // 4-bit value = 1111
8’b1101_0000 // 8-bit value = 11010000
8’hFF // 8-bit value = 11111111
8’d7 // 8-bit value = 00000111
32’d0 // 32-bit value = 0 (decimal)
’b1111 // 32-bit value = 15 (decimal)

To improve readability and avoid mistakes, the digits of a number can

be separated by the underscore (_) symbol.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 8 / 51
Bitwise logic operators

These binary operators perform logic operations on pairs of bits.

When applied to vectors, the operators are applied to bits in

corresponding bit positions and the results are also associated with
the same bit position.

Verilog supports the following bitwise operators:

~ inverse
& AND
| OR
^ XOR
~^ XNOR
<< logical shift left
>> logical shift right

wire [3:0] X,Y,A,B,C,D,E,F,G;

M. Saghir (EECE 320 – Summer 2023) assign

Introduction X =Design
to Digital 4’b1010; // X
with Verilog = 1010 (binary) 9 / 51
 & AND
Bitwise logic operators
| OR(2)
^ XOR
~^ XNOR
<< logical shift left
>> logical shift right
Examples:
wire [3:0] X,Y,A,B,C,D,E,F,G;

assign X = 4’b1010; // X = 1010 (binary)

assign Y = 4’b1111; // Y = 1111 (binary)
assign A = ~X; // A = 0101 (binary)
assign B = X & Y; // B = 1010 (binary)
assign C = X | Y; // C = 1111 (binary)
assign D = X ^ Y; // D = 0101 (binary)
assign E = X ~^ Y; // E = 1010 (binary)
assign F = X << 3; // F = 0000 (binary)
assign G = Y >> 2; // G = 0011 (binary)

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 10 / 51
 assign C = X | Y;
wire [3:0] X,Y,A,B,C,D,E,F,G; // C = 1111 (binary)
Boolean logic operators
assign D = X ^ Y; // D = 0101 (binary)
assign X = 4’b1010; // X =E1010
assign = X (binary)
~^ Y; // E = 1010 (binary)
assign Y = 4’b1111; // Y = 1111 (binary)
assign F = X << 3; // F = 0000 (binary)
assign A = ~X; // A = 0101 (binary)
Used to assign
develop X & Y;assign
B =conditional =G = Y(binary)
>> 2;
// B statements
1010 that// evaluate
G = 0011to(binary)
assign
TRUE (1) C = X |(0).
or FALSE Y; // C = 1111 (binary)
assign D = X ^ Y; // D = 0101 (binary)
assign E = X ~^ Y;! // E =logical negation
1010 (binary)
assign F = X << 3;&&// F =logical AND
0000 (binary)
assign G = Y >> 2;
|| // G =logical
0011 (binary)
OR

Can be applied
! to numerical
logical negation values where non-zero values are
&&TRUE
treated as logical
andAND !X is treated as
zero // TRUE if X = all zeros, FALSE oth
FALSE.
|| logical OR X && Y // TRUE if X & Y = all ones; FALSE
X || Y // TRUE if X | Y = all ones; FALSE
Examples:
!X // TRUE if X = zero, FALSE otherwise
X && Y // TRUE
== if Xequal
& Y = to
non-zero; FALSE otherwise
X || Y // TRUE
!= if Xnot
| Y equal
= non-zero;
to FALSE otherwise
< less than
== equal to
> greater than
M. Saghir
!= not equal to<=
(EECE 320 – Summer 2023)
less than or equal to
Introduction to Digital Design with Verilog 11 / 51
 || logical OR
Relational operators
!X // TRUE if X = zero, FALSE otherwise
X && Y // TRUE if X & Y = non-zero; FALSE otherwi
X || return
Compare quantities and Y // TRUE
TRUE (1) ififXthe
| Ycorresponding
= non-zero; FALSE otherwis
relation
is satisfied and FALSE (0) otherwise.
== equal to
!= not equal to
< less than
> greater than
<= less than or equal to
>= greater than or equal to

Examples:
X == Y // TRUE if X is equal to Y; FALSE otherwise
X != Y // TRUE if X is not equal to Y; FALSE otherwise
X<Y // TRUE if X is less than Y; FALSE otherwise
X>Y // TRUE if X is greater than Y; FALSE otherwise
X <= Y // TRUE if X is less than or equal to Y; FALSE otherwise
X >= Y // TRUE if X is greater than or equal to Y; FALSE otherwise

<target_net> = <Boolean_condition>
M. Saghir (EECE 320 – Summer 2023)
? <true_assignment> : < false_assignmen
Introduction to Digital Design with Verilog 12 / 51
Conditional assignment statement
X == Y // TRUE if X is equal to Y; FALSE otherwise
X != Y // TRUE if X is not equal to Y; FALSE otherwise
X<Y // TRUE if X is less than Y; FALSE otherwise
X>Y // TRUE if X is greater than Y; FALSE otherwise
X <= Y // TRUE if X is less than or equal to Y; FALSE otherwise
Uses
== the
X >= Y ? and : operators
//// TRUE
TRUE to express
ififXXisisgreater
equal to Y; FALSE
than anotherwise
or equal if/else
to Y; FALSEconditional
otherwise
X != Y //
assignment statement. TRUE if X is not equal to Y; FALSE otherwise
X<Y // TRUE if X is less than Y; FALSE otherwise
X >Y
<target_net> =// <Boolean_condition>
TRUE if X is greater ? than Y; FALSE otherwise
<true_assignment> : < false_assignment>;
X <= Y // TRUE if X is less than or equal to Y; FALSE otherwise
X–>=If Yboolean // TRUE
conditionif X is
is greater
TRUE,than or equal
target net = to trueY; FALSE otherwise
assignment.
assign F = (A == 1’b0) ? 1’b1 : 1’b0; // F = 1 if A equals 0; otherwise F = 0
– Else,
assign F =target
(sel ==net = false
1’b0) ? A : B;assignment. // F = A if sel equals 0; otherwise F = B
assign F = ((A == 1’b0) &&
<target_net> = <Boolean_condition> (B == 1’b0)) ? 1’b0 :
? <true_assignment> : < false_assignment>;
((A == 1’b0) && (B == 1’b1)) ? 1’b1 :
Examples: ((A == 1’b1) && (B == 1’b0)) ? 1’b1 : 1’b0; // nested conditional implements
assign F = (A == 1’b0) ? 1’b1 : 1’b0; // F =//1aif2-input
A equalsxor0;function
else F = 0
assign F
assign F == (!C
(sel&& ==(!A || B))
1’b0) ?A ? :1’b1
B; : 1’b0; // //F F= =C’.(A’ + B)equals 0; else F = B
A if sel
assign F = (!C && (!A || B)) ? 1’b1 : 1’b0; // F = C’.(A’ + B)
wire[7:0]
// nested bus1, bus2, assignment
conditional bus3, busC; statement implementing a 2-input xor function
wire[3:0] busA, busB;
assign F = ((A == 1’b0) && (B == 1’b0)) ? 1’b0 :
((A == 1’b0) && (B == 1’b1)) ? 1’b1 :
bus1[7:0] = {bus2[7:4], bus3[3:0]};
((A == 1’b1) && (B == 1’b0)) ? 1’b1 : 1’b0;
busC = {busA, busB};
M. Saghir busC[7:0]
(EECE = {4’b0000,
320 – Summer 2023) busA};
Introduction to Digital Design with Verilog 13 / 51
 X != Y // TRUE if X is not equal to Y; FALSE otherwise
Nested
X <conditional
Y // TRUEassignment
if X is less than Y; statement
FALSE otherwise
X>Y // TRUE if X is greater than Y; FALSE otherwise
X <= Y // TRUE if X is less than or equal to Y; FALSE otherwise
X >= Y // TRUE if X is greater than or equal to Y; FALSE otherwise

<target_net> = <Boolean_condition> ? <true_assignment> : < false_assignment>;

Conditional assignment statements can be nested. The else clause
may include
assign one
F = (A (or more)
== 1’b0) ? 1’b1conditional
: 1’b0; assignment
// F = 1 if Astatements.
equals 0; otherwise F = 0
assign F = (sel == 1’b0) ? A : B; // F = A if sel equals 0; otherwise F =
assign F = (!C && (!A || B)) ? 1’b1 : 1’b0;
Example: // F = C’.(A’ + B)

// nested conditional assignment statement implementing a 2-input xor function

assign F = ((A == 1’b0) && (B == 1’b0)) ? 1’b0 :
((A == 1’b0) && (B == 1’b1)) ? 1’b1 :
((A == 1’b1) && (B == 1’b0)) ? 1’b1 : 1’b0;

wire[7:0] bus1, bus2, bus3, busC;

wire[3:0] busA, busB;

bus1[7:0] = {bus2[7:4], bus3[3:0]};

busC = {busA, busB};
M. Saghir busC[7:0]
(EECE = {4’b0000,
320 – Summer 2023) busA};
Introduction to Digital Design with Verilog 14 / 51
Concatenation
<target_net> = <Boolean_condition> ? <true_assignmen

assign F = (A == 1’b0) ? 1’b1 : 1’b0; // F = 1 if

Curly brackets {} are used to concatenate signals consisting of
assign F = (sel == 1’b0) ? A : B; // F = A if
individual bits or bitassign
vectorsFinto
= ((Alarger bit vectors.
== 1’b0) && (B == 1’b0)) ? 1’b0 :
((A == 1’b0) && (B == 1’b1)) ? 1’b1 :
The number of concatenated bits((A == 1’b1)
must be && (B ==
equal 1’b0))
to the ? 1’b1of
number : 1’b0;
bits // n
associated with the left hand side of the associated assignment. // a
assign F = (!C && (!A || B)) ? 1’b1 : 1’b0; // F = C’.(
Examples:
wire[7:0] bus1, bus2, bus3, busC;
wire[3:0] busA, busB;

bus1[7:0] = {bus2[7:4], bus3[3:0]};

busC = {busA, busB};
busC[7:0] = {4’b0000, busA};

{<number_of_replications>{<vector_to_be_replicated>}}
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 15 / 51
 // a 2-input xor fun
((A ==F1’b1)
assign = (!C&&
&&(B
(!A== 1’b0))
|| B)) ? 1’b1
? 1’b1 : 1’b0; ////nested
: 1’b0; conditional
F = C’.(A’ + B) imple
Replication // a 2-input xor function
assign F = (!C && (!A || B)) ? 1’b1 : 1’b0; // F = C’.(A’ + B)
wire[7:0] bus1, bus2, bus3, busC;
wire[3:0] busA, busB;
wire[7:0] bus1, bus2, bus3, busC;
wire[3:0] busA, busB;
bus1[7:0] = {bus2[7:4], bus3[3:0]};
ReplicationbusCis the repeated concatenation of a bit vector with itself for
= {busA, busB};
a bus1[7:0]
specific number
=busC[7:0] of=times.
{bus2[7:4], busA};double curly brackets {{}} and an
It uses
bus3[3:0]};
{4’b0000,
busC =to{busA,
integer specifybusB};
the desired number of replications.
busC[7:0] = {4’b0000, busA};
{<number_of_replications>{<vector_to_be_replicated>}}

{<number_of_replications>{<vector_to_be_replicated>}}
busX = {4{bus1}}; // equivalent to busx = {bus1, bus1, bus1, bus
Examples: busY = {2{A,B}}; // equivalent to busY = {A,B,A,B}
busZ =
busX = {4{bus1}}; {bus1, {2{bus2}}}; // equivalent
// equivalent to busx =to{bus1,
busZ =bus1,
{bus1, bus2,
bus1, bus2}
bus1}
busY = {2{A,B}}; // equivalent to busY = {A,B,A,B}
busZ = {bus1, {2{bus2}}}; // equivalent to busZ = {bus1, bus2, bus2}
+ addition
- subtraction (binary operator)
- negation (unary operator)
+ addition
* multiplication
- subtraction
/ (binary operator)
division
- negation
% (unary
modulus operator)
* multiplication
** power
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 16 / 51
Numerical operators
busX = {4{bus1}}; // equivalent to busx = {bus1,
busY = {2{A,B}}; // equivalent to busY = {A,B,A
busZ = {bus1, {2{bus2}}};
Perform binary (two operand) and unary (one // equivalent to busZ = {bus1,
operand) arithmetic
operations.
+ addition
- subtraction (binary operator)
- negation (unary operator)
* multiplication
/ division
% modulus
** power
<<< logical shift left
>>> arithmetic shift right

Typically, numerical arguments have the same bit size. However, if

argument sizes differ, the smaller argument is expanded to match the
size of the larger argument.
– A smaller unsigned argument is padded with zeros.
– A smaller signed argument is padded with its most-significant
(sign) bit.
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 17 / 51
Numerical operators (2)

If one of the arguments is real, the operator will operate on real

arguments and produce a real result.

If one of the arguments is unsigned, all arguments and results will be

unsigned.

Examples:
X+Y // add X to Y
X–Y // subtract Y from X
-X // negate X
X*Y // multiply X by Y
X/Y // divide X by Y
X%Y // remainder of X/Y
X <<< 3 // shift left 3 bits; fill vacated bits with zeros
X >>> 2 // shift right 2 bits; fill vacated bits with sign of X

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 18 / 51
 Example: Canonical SOP Circuit

Develop a Verilog model for the following logic function:

F(A, B, C) = Σ(m0, m2, m6) = A ′ .B ′ .C ′ + A ′ .B.C ′ + A.B.C ′

ple 3.2
national logic
M. Saghir (EECEusing continuous
320 – Summer 2023) assignment with
Introduction to Digital logical
Design operators
with Verilog 19 / 51
Gate-Level Primitives
Verilog provides a number of gate-level primitives that model the
behavior of various logic gates:
– not()
– and()
– nand()
– or()
– nor()
– xor()
– xnor()

Syntax:

Examples:

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 20 / 51
Example: Gate-Level Structural Model

Develop a gate-level structural model for the function:

F(A, B, C) = Σ(m0, m2, m6) = A ′ .B ′ .C ′ + A ′ .B.C ′ + A.B.C ′

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 21 / 51
Heirarchical Design

Building a 4:1 multiplexer from 2:1 multiplexers:

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 22 / 51
Heirarchical Structural Model

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 23 / 51
Module Instantiation

Creating an instance of a module in some design:

Explicit Port Mapping:

– Signals are mapped to module ports based on the explicit port names.

Positional Port Mapping:

– Signals are mapped to module ports based on the (implicit) port
positions in the module interface.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 24 / 51
Verilog testbench

Once a Verilog model has been developed we can validate its

functionality using a testbench.

A testbench is a Verilog module that creates an instance of the circuit

under test, drives its input ports with stimulus signals, and provides
access to its output ports for observation.

The circuit is validated by observing how its output responds to the

input stimuli (using a waveform viewer), or by writing code that
compares the circuit outputs to expected results.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 25 / 51
Verilog testbench (2)

Testbench

Unit Under
Driver
…

…
Test (UUT)

Input stimulus Output response

signals signals

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 26 / 51
mux4to1 testbench

module mux4to1_TB ();

reg TB_w0, TB_w1, TB_w2, TB_w3;

reg [1:0] TB_sel;
wire TB_f;

mux4to1 UUT (TB_w0, TB_w1, TB_w2, TB_w3, TB_sel, TB_f);

initial begin
TB_w0 = 1’b0;
TB_w1 = 1’b1;
TB_w2 = 1’b0;
TB_w3 = 1’b1;
TB_sel = 2’b00;
#10 TB_sel = 2’b01;
#10 TB_sel = 2’b10;
#10 TB_sel = 2’b11;
end

endmodule

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 27 / 51
Notes on mux4to1 testbench

Being the top-most module in a design heirarchy, testbenches do not

have ports.

Testbench signals should be declared to both drive and capture the

results of a design-under-test.

Testbenches are typically structural modules; they only instantiate the

modules under test and drive their inputs.

An initital block is procedural Verilog statement; it is executed at

simulation time zero, and all statements inside the initial block are
executed sequentially. An initial block executes only once.

The # symbol is used to advance simulation time. For example, #10

advances simulation time ten time units. This enables modifying
testbench inputs to check the output produced by the
design-under-test.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 28 / 51
 TB_w1 = 1’b1;
Procedural blocks
TB_w2 = 1’b0;
TB_w3 = 1’b1;
TB_sel = 2’b00;
#10 is
A procedural block TB_sel = 2’b01;
a Verilog construct that models circuit behavior
#10
using sequential TB_sel = 2’b10;
statements.
#10 TB_sel = 2’b11;
end
The two main procedural blocks in Verilog are initial and always.
A Verilog module may contain multiple initial and always blocks.
endmodule
Syntax of an always block:
always [@ (<sensitivity list>)] <statement(s)>

– An always block takes an optional sensitivity list, a comma-separated

list of signals that cause the block to be evaluated any time a signal in
the list changes.
– An always block may include one or more statements that are
evaluated sequentially. If the block contains multiple statements, they
must be enclosed inside a begin-end block.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 29 / 51
 #10 TB_sel = 2’b10;
TB_sel = 2’b00;
#10 TB_sel = 2’b11;
always block sensitivity#10 lists
endTB_sel = 2’b01;
#10 TB_sel = 2’b10;
#10 TB_sel = 2’b11;
endmodule
A sensitivity list specifiesend
the signals or events that cause an always
block to be evaluated during simulation.
endmodule
always [@ (<sensitivity list>)] <statement(s)>
This always block will be evaluated any time there is a change in the
logic levels of signals I0always
, I1, or[@
sel :
(<sensitivity list>)] <statement(s)>
always @ (I0, I1, sel)
begin
// statements
always
end @ (I0, I1, sel)
begin
This always block will be//always statements
evaluated @ (posedge
on every clk) positive edge (i.e. 0-to-1
end
begin
transition) of the clk signal:
// statements
always
end @ (posedge clk)
begin
// statements
end
module mux2to1 (input I0, I1, sel, output y);
always @ (I0, I1, sel) begin
if (sel == 0)
M. Saghir (EECE 320 – Summer 2023) module
Introduction mux2to1
to Digital Design with (input
Verilog I0, I1, sel, output y); 30 / 51
always block sensitivity lists (2)
always @ (I0, I1, sel)
begin
// statements
An always
end block’s sensitivity list may include positive or negative
edge signal transitions (e.g. posedge, negedge).
always @ (posedge clk)
beginlogic level transition and signal edge transition events
However,
// statements
should never be combined in the same sensitivity list at the same
end
time.
always @ (I0, I1, sel, posedge clk, negedge reset_n) // incorrect
begin
// statements
end

Logic level transitions should be used to model combinational circuits.

module
Signal mux2to1 (input
edge transitions I0, I1,
should be sel,
usedoutput y); sequential circuits.
to model
always @ (I0, I1, sel) begin
if (sel == 0)

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 31 / 51
Procedural block assignments
Blocking assignments (=) are used to model combinational circuits.
reg T, F;

reg
alwaysT, F;@ (A, B, C)
begin
always
// RHS@ (A, B,are
values C) evaluated sequentially.
begin
T = A & B;
//F RHS
= T &values
C; are evaluated sequentially.
T = A & B;
end
F = T & C;
Non-blocking end
assignments (<=) are concurrent statements used to
model sequential reg Q0, Q1, Q2;
circuits.
reg Q0, Q1, Q2;
always @ (posedge clk)
begin
always @ (posedge clk)
// RHS values are evaluated concurrently,
begin
// as soon as the always block is triggered.
// RHS values are evaluated concurrently,
//Q0as<= w; as the always block is triggered.
soon
Q1 <=
Q0 <= w;
Q0;
Q2 <=
Q1 <= Q0;Q1;
end
Q2 <= Q1;
end
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 32 / 51
 always @(2)
Procedural block assignments (posedge clk)
begin
// RHS values are evaluated concurrently,
// as soon as the always block is triggered.
Any signal or port assignedQ0 <= w; inside a procedural block must be
a value
declared as a reg. Q1 <= Q0;
Q2 <= Q1;
end
A signal or port must never be assigned in more than one procedural
block.
reg F;

always @ (A, B, C)
begin
F = A & B & C;
end

always @ (D, E)
begin
F = D ^ E;
end

module mux2to1 (input I0, I1, sel, output y);

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 33 / 51
Other procedural block statements

if-else statements for executing statements conditionally.

case statements for implementing multi-way branches based on

a selector input value.

Delay statements (#) for introducing timing delays during simulation.

System tasks for displaying messages ($display, $monitor), and

managing a simulation ($stop, $finish).

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 34 / 51
if statement

if statements are used to execute conditional statements inside

procedural blocks.
if (<condition>)
<true clause>
else
<false clause>

The if-condition can be any Boolean expression.

The true clause is executedmodule
if the specified
mux4to1condition
(input I0,isI1,True;
I2, I3,the false
[1:0] sel, o
clause is executed if the condition
always is @
False.
(I0, I1, I2, I3, sel) begin
if (sel == 2’b00)
Both the true and false clausesymay
= I0;include one or more statements;
multiple statements should beelse
enclosed
if (sel inside begin-end blocks.
== 2’b01)
y = I1;
if-statements can be nested inside other if-statements, and else
else if (sel == 2’b10)
y = I2; (e.g. else if (condition)).
clauses may include other if conditions
else
M. Saghir (EECE 320 – Summer 2023)
y = I3;
Introduction to Digital Design with Verilog 35 / 51
 <true clause>
else 4:1 multiplexer using an if statement
Example:
<false clase>

module mux4to1 (input I0, I1, I2, I3, [1:0] sel, output reg y);
always @ (I0, I1, I2, I3, sel) begin
if (sel == 2’b00)
y = I0;
else if (sel == 2’b01)
y = I1;
else if (sel == 2’b10)
y = I2;
else
y = I3;
end
endmodule

module mux4to1 (input I0, I1, I2, I3, [1:0] sel, output reg y);
always @ (I0, I1, I2, I3, sel) begin
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 36 / 51
 else
y = I3;
case statement end
endmodule
case statements are an efficient way to implement multi-way
branches:
case (<signal name>)
<signal value 1> : <clause 1>
<signal value 2> : <clause 2>
:
<signal value n> : < clause n>
default: <default clause>
endcase

A case statement evaluates a signal that can take multiple values and
executes the clause module mux4to1
matching (input I0, I1, value.
the corresponding I2, I3, [1:0] sel, output re
always @ (I0, I1, I2, I3, sel) begin
Each clause may includecase (sel)
one or more statements; if a clause contains
multiple statements, they must ybe
2’b00 : = I0;
enclosed in begin-end blocks.
2’b01 : y = I1;
A case statement may include 2’b10 : yan = I2;
optional default clause that gets
default : y = I3;
executed if the current endcase signal value does not match any of the
specified values. end
M. Saghir (EECE 320 – Summer 2023) endmodule
Introduction to Digital Design with Verilog 37 / 51
 :
Example: 4:1
<signal multiplexer
value n> a case statement
using
n> : < clause
default: <default clause>
endcase

module mux4to1 (input I0, I1, I2, I3, [1:0] sel, output reg y);
always @ (I0, I1, I2, I3, sel) begin
case (sel)
2’b00 : y = I0;
2’b01 : y = I1;
2’b10 : y = I2;
default : y = I3;
endcase
end
endmodule

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 38 / 51
Sequential circuits: T flip-flop

// T flip-flop with asynchronous, active-low reset.

module TFF (input T, clk, reset_n, output reg Q);

always @ (posedge clk, negedge reset_n) begin
if (reset_n == 1’b0)
Q <= 1’b0;
else if (T == 1’b1)
Q <= ~Q;
end
endmodule

// D flip-flop with synchronous, active-high reset.

module DFF (input Din, clk, reset, output reg Q, reg Q_bar);
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 39 / 51
 end
Sequential circuits: D flip-flop
endmodule

// D flip-flop with synchronous, active-high reset.

module DFF (input Din, clk, reset, output reg Q, reg Q_bar);
always @ (posedge clk) begin
if (reset == 1’b1)
begin
Q <= 1’b0;
Q_bar <= 1’b1;
end
else
begin
Q <= Din;
Q_bar <= ~Din;
end
end
endmodule

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 40 / 51
 Q_bar <= ~Din;
Sequential
end circuits: shift register
end
endmodule

// 4-bit shift-right register with parallel load.

module SHR4 (input clk, load, [3:0] Din, W, output reg [3:0] Q);
always @ (posedge clk) begin
if (load == 1’b1)
Q <= Din;
else
Q <= {W, Q[3:1]};
end
endmodule

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 41 / 51
Sequential circuits: modulo-10 counter

// modulo-10 up counter (counts from 0 to 9 repeatedly)

module mod10counter (input clk, reset_n, output reg [3:0] Q);

always @ (posedge clk, negedge reset_n) begin
if (reset_n == 1’b0 || Q == 4’b1001)
Q <= 4’b0000;
else
Q <= Q + 1;
end
endmodule

// generating 25 clock cycles in a testbench

// each clock cycle = 10 time units

module myTB();
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 42 / 51
 #3 // advances simulation time by 3 ns
initial begin
Modeling finite #5.5 machines
state // advances simulation time by 5.5 ns
(FSMs)
#3 // advances
#0.001 simulation
// advances time by time
simulation 3 ns by 0.001 ns = 1 ps
#5.5 end // advances simulation time by 5.5 ns
#0.001 // advances simulation time by 0.001 ns = 1 ps
end endmodule
Declare two reg signals of appropriate width1 called currentState
and nextState
endmodule .
// 2-bit current-state and next-state signals
reg [1:0] currentState, nextState;
// 2-bit current-state and next-state signals
Use thereg [1:0] currentState,
parameter constructnextState;
to create symbolic state names and
// symbolic state
associate them with specific state name declarations
values.
parameter stateA = 2’b00, stateB = 2’b01, stateC = 2’b10;
// symbolic state name declarations
parameter stateA = 2’b00, stateB = 2’b01, stateC = 2’b10;

Use three always blocks to manage the current state, next state, and
FSM output, respectively.

1
width = log2 (number of states)
M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 43 / 51
 8.5, to indicate the structure of the circuit that implements the required fini
ne.Example:
Two flip-flops Pattern Detector
represent the stateFSM
variables. In the figure we have not sp
e of flip-flops to be used; this issue is addressed in the next subsection. Fr

Present Next state Output

state w=0 w=1 z

A A B 0
B A C 0
C A C 1

We need logFigure 8.4 State table for the sequential circuit in Figure
2 (3) = 2 bits to represent each state.
We can use the following state assignments: A = 00, B = 01, C = 10.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 44 / 51
Managing the current state

module patternDetectorFSM (input clk, resetn, w, output reg z);

reg [1:0] currentState, nextState;

parameter stateA = 2’b00, stateB = 2’b01, stateC = 2’b10;

always @ (posedge clk, negedge resetn) begin

if (resetn == 1’b0)
currentState <= stateA;
else
currentState <= nextState;
end

always @ (currentState, w) begin

case (currentState)
stateA:
if (w == 1’b0)
M. Saghir (EECE 320 nextState
– Summer 2023) <= stateA;
Introduction to Digital Design with Verilog 45 / 51
 else
currentState <= nextState;
Managing the next
end
state

always @ (currentState, w) begin

case (currentState)
stateA:
if (w == 1’b0)
nextState <= stateA;
else
nextState <= stateB;
stateB:
if (w == 1’b0)
nextState <= stateA;
else
nextState <= stateC;
stateC:
if (w == 1’b0)
nextState <= stateA;
else
nextState <= stateC;
endcase
end

always
M. Saghir (EECE 320 – Summer 2023) @ (currentState)
Introduction begin
to Digital Design with Verilog 46 / 51
 nextState <= stateA;
else
Managing the output nextState <= stateC;
endcase
end

always @ (currentState) begin

case (currentState)
stateA: z = 1’b0;
stateB: z = 1’b0;
stateC: z = 1’b1;
endcase
end

endmodule

The above is for a Moore machine. A Mealy machine is modeled

similarly, but the output will depend on both the current state and the
input.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 47 / 51
 // modulo-10 up counter (counts from 0 to 9 repeatedly)
The for loop
module mod10counter (input clk, reset_n, output reg [3:0] Q)
Verilog supports
always a@number of looping
(posedge constructs
clk, negedge for, while,
such asbegin
reset_n)
repeat, andifforever.
(reset_n == 1’b0 || Q == 4’b1001)
Q <= 4’b0000;
else
Loops are generally not used to model actual hardware; they are
more commonly used+in1;testbenches to help drive simulation.
Q <= Q
end
endmodule
A for loop is used to execute one or more statements a fixed number
of times. It requires an integer iteration variable and has the
following syntax:
for (<var initialization>; <condition>; <var update>)
<statement(s)>;

– The iteration variable is first initialized to a starting value.

– The statement(s)2 in the body of a for loop continue to execute as long
// condition
as the generating 25 clock
(involving thecycles invariable)
iteration a testbench
is True.
// each variable
– The iteration clock cycle = 10 time
is updated units
at the end of each loop iteration.
2
Multiple statements should be enclosed inside a begin-end block.
module myTB();
M. Saghir (EECE 320 – Summer 2023)
Introduction to Digital Design with Verilog 48 / 51
 Q <= Q + 1;
end a for loop to generate 25 clock cycles
Example: Using
endmodule

// generating 25 clock cycles in a testbench

// each clock cycle = 10 time units

module myTB();
reg clk;
integer i;

initial begin
clk <= 0;
for (i = 0; i <= 50; i++) begin
#5 clk <= ~clk;
end
end
endmodule

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 49 / 51
 reg clk;
Controlling simulation
integertime
i;

initial begin
clk <= 0;
We have already learned that
for (i = 0; i <= 50;# i++)
the operator
beginis used to advance
simulation time by a#5specific
clk <= ~clk;
number of time units.
end
end
The ’timescale directive assigns a value to the simulation time unit to
provide accurateendmodule
time modeling. It is commonly used in the testbench
file and uses the following syntax:
`timescale <time unit>/<time precision>

– Both the time unit and time precision are expressed in metric units of
time: seconds (s), milliseconds (ms), microseconds (us), nanoseconds
(ns), picoseconds (ps), and femtoseconds (fs).
– The time precision specifies the fraction of the time unit that can be
used to advance simulation time. It must always be smaller than or
equal to the specified time unit.

M. Saghir (EECE 320 – Summer 2023) Introduction to Digital Design with Verilog 50 / 51
Example: Setting ’timescale to 1 ns with 1 ps precision

// set the simulation time unit to 1 ns with a precision of 1 ps

`timescale 1ns/1ps

module myTB();

initial begin
#3 // advances simulation time by 3 ns
#5.5 // advances simulation time by 5.5 ns
#0.001 // advances simulation time by 0.001 ns = 1 ps
end

endmodule

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