Digital Integrated Circuits

A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

Designing Sequential Logic Circuits

November 2002
Digital Integrated Circuits2nd

Sequential Circuits

Sequential Logic
Inputs COMBINATIONAL LOGIC Current State Registers
Q D

Outputs

Next state

CLK

2 storage mechanisms
positive feedback charge-based
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Sequential Circuits

Naming Conventions
In

our text:

a latch is level sensitive a register is edge-triggered

There

are many different naming conventions

For instance, many books call edgetriggered elements flip-flops This leads to confusion however

Digital Integrated Circuits2nd

Sequential Circuits

Latch versus Register

Latch stores data when clock is low

D Q Clk Clk D Q

Register stores data when clock rises

D Q Clk

Clk

D
Q
Sequential Circuits

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Latches

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Sequential Circuits

Latch-Based Design
N latch is transparent when f = 0
f

P latch is transparent when f = 1

N Latch

Logic

P Latch

Logic
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Sequential Circuits

Timing Definitions

CLK t tsu D thold Register D Q

DATA STABLE

CLK t

tc 2
Q

DATA STABLE

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Sequential Circuits

Characterizing Timing
tD 2 D Q D
Q

Clk

Clk

tC 2

tC 2

Register
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Latch
Sequential Circuits

Maximum Clock Frequency

f

FF s

LOGIC tp,comb

Also: tcdreg + tcdlogic > thold tcd: contamination delay = minimum delay

tclk-Q + tp,comb + tsetup = T

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Sequential Circuits

Positive Feedback: Bi-Stability

V o1

1 o V

Vi2

1 o V 5 2 i V
V o2

Vi1 A V i 2 = V o1

1 o V 5 2 i V

V i 1 = V o2

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Sequential Circuits

Meta-Stability

Gain should be larger than 1 in the transition region

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Sequential Circuits

Writing into a Static Latch

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
CLK

CLK
Q CLK

D CLK

CLK

Converting into a MUX

Digital Integrated Circuits2nd

Forcing the state (can implement as NMOS-only)

Sequential Circuits

Mux-Based Latches
Negative latch Positive latch (transparent when CLK= 0) (transparent when CLK= 1)

1 D 0

Q
D

0
1

CLK

CLK

Q Clk Q Clk In
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Q Clk Q Clk In
Sequential Circuits

Mux-Based Latch
CLK

Q CLK

CLK
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Sequential Circuits

Mux-Based Latch

CLK QM
QM CLK

CLK

CLK

NMOS only
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Non-overlapping clocks
Sequential Circuits

Master-Slave (Edge-Triggered) Register

Two opposite latches trigger on edge Also called master-slave latch pair
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Sequential Circuits

Master-Slave Register
Multiplexer-based latch pair

I2

T2

I3

I5

T4

I6

QM I1 T1 I4 T3

CLK

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Sequential Circuits

Clk-Q Delay
2.5

CLK
Volts

1.5

tc 2

q(lh)

tc 2

q(hl)

0.5

2 0.5 0

0.5

1 1.5 time, nsec

2.5

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Sequential Circuits

Setup Time

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Sequential Circuits

Reduced Clock Load Master-Slave Register

CLK D CLK

T1 CLK

I1 I2

T2 CLK

I3 I4

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Sequential Circuits

Avoiding Clock Overlap

CLK A X CLK Q D

CLK (a) Schematic diagram

CLK

CLK

CLK (b) Overlapping clock pairs

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Sequential Circuits

Overpowering the Feedback Loop Cross-Coupled Pairs

NOR-based set-reset
S S Q S R R Q Q Q R Q Q

0
1 0 1

0
0 1 1

Q
1 0 0

Q
0 1 0

Forbidden State

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Sequential Circuits

Cross-Coupled NAND
Cross-coupled NANDs
S

Added clock
VDD

M2
Q

M4
Q

CLK

M6

M1

M3

M8

CLK

M5

M7

This is not used in datapaths any more, but is a basic building memory cell
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Sequential Circuits

Sizing Issues
2.0 3

Q 1.5
Q (Volts)

S W = 0.5 m m W = 0.6 m m W = 0.7 m m

2
1.0

Volts

1 0.5 W = 1m m

W = 0.8 m m W = 0.9 m m

0.0 2.0

2.5

3.0 W/L 5 and 6

3.5

4.0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ns)

(a)

(b)

Output voltage dependence on transistor width

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Transient response

Sequential Circuits

Storage Mechanisms
Static

Dynamic (charge-based)
CLK

CLK

Q CLK

CLK
D

CLK

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Sequential Circuits

Making a Dynamic Latch Pseudo-Static

CLK

CLK

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Sequential Circuits

More Precise Setup Time

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Sequential Circuits

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay

CP
TClk-Q TSetup-1

Time

Data TSetup-1
t=0

Clock

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay

CP

TClk-Q

TSetup-1

Time

Data TSetup-1
t=0

Clock

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay

CP
TClk-Q TSetup-1

Time

Data TSetup-1
t=0

Clock

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay

TClk-Q

CP

TSetup-1

Time

Data TSetup-1
t=0

Clock

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2

D
Inv1

D1

SM

QM

Clk-Q Delay TClk-Q

CP

TSetup-1

Time

Data

Clock TSetup-1
t=0 Time

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Sequential Circuits

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

0
TClk-Q THold-1

Time

Clock THold-1
t=0

Data

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

0
TClk-Q THold-1

Time

Clock THold-1
t=0

Data

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

0
TClk-Q

THold-1

Time

Clock

Data THold-1
t=0 Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1
Clk-Q Delay

D
Inv1

D1

SM

Inv2

QM

TClk-Q

CP

THold-1

Time

Clock THold-1
t=0

Data

Time

Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

TClk-Q

CP

THold-1

Time

Clock

Data THold-1
t=0 Time

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Sequential Circuits

Other Latches/Registers: C2MOS

VDD VDD

M2

M6

CLK D
CLK

M4 X M3

CLK CL1

M8

Q
CLK M7

CL2

M1

M5

Master Stage

Slave Stage

Keepers can be added to make circuit pseudo-static

Digital Integrated Circuits2nd

Sequential Circuits

Insensitive to Clock-Overlap
VDD M2 0 D VDD M6 0 X VDD M2 VDD M6

M4

M8
Q D 1 M3 M1 X 1 M7 M5 Q

M1

M5

(a) (0-0) overlap

(b) (1-1) overlap

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Sequential Circuits

Pipelining
REG

REG

REG

REG

REG

REG
CLK

CLK
REG

log

Out
b

CLK
REG

log

Out

CLK

CLK

CLK

CLK

CLK

Reference

Pipelined

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Sequential Circuits

Other Latches/Registers: TSPC

VDD VDD VDD VDD

Out In CLK CLK In CLK CLK Out

Positive latch Negative latch (transparent when CLK= 1) (transparent when CLK= 0)
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Sequential Circuits

Including Logic in TSPC

VDD PUN Q In CLK CLK CLK CLK VDD In1 VDD In2 Q VDD

PDN

In1

In2

Example: logic inside the latch

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AND latch
Sequential Circuits

TSPC Register
VDD CLK VDD VDD Q Q CLK M8

M3

M6 Y

M9

CLK

M2

M5

M1

CLK

M4

M7

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Sequential Circuits

Pulse-Triggered Latches An Alternative Approach

Ways to design an edge-triggered sequential cell:
Master-Slave Latches L1
Data D Q Clk Clk

Pulse-Triggered Latch L2
D Q Clk Data Clk

L
D Q Clk

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Sequential Circuits

Pulsed Latches
VDD VDD M3 M6 CLK Q VDD

CLKG

M2

CLKG

M5

MP X

CLKG

M1

M4

MN

(a) register

(b) glitch generation

CLK CLKG (c) glitch clock

Digital Integrated Circuits2nd

Sequential Circuits

Pulsed Latches
Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :
CLK
P1 P3 M6

M3 D

M2
M1

P2

M5
M4

CLKD

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Sequential Circuits

Hybrid Latch-FF Timing

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Sequential Circuits

Latch-Based Pipeline

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Sequential Circuits

Non-Bistable Sequential Circuits Schmitt Trigger

Vou t
In Out

V OH

VTC with hysteresis Restores signal slopes

V OL

VM
Digital Integrated Circuits2nd

VM+

Vi n
Sequential Circuits

Noise Suppression using Schmitt Trigger

Digital Integrated Circuits2nd

Sequential Circuits

CMOS Schmitt Trigger

VDD

M2 Vin X

M4 Vout

M1

M3

Moves switching threshold of the first inverter Digital Integrated Circuits2nd

Sequential Circuits

Schmitt Trigger Simulated VTC

2.5 2.0 1.5 VM1 VM2 2.5 2.0 1.5

(V) 1.0 X V
0.5 0.0 0.0

(V) 1.0 x V
0.5 0.0 0.0

k=1 k=3 k=2 k=4 0.5 1.0 1.5 Vin (V) 2.0 2.5

0.5

1.0 1.5 Vin (V)

2.0

2.5

Voltage-transfer characteristics with hysteresis.

The effect of varying the ratio of the PMOS device M4. The width is k* 0.5m m.

Digital Integrated Circuits2nd

Sequential Circuits

CMOS Schmitt Trigger (2)

VDD
M4 M6 M3

In
M2 X M1

Out

M5

VDD

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Sequential Circuits

Multivibrator Circuits
R S Bistable Multivibrator flip-flop, Schmitt Trigger

T Monostable Multivibrator one-shot

Astable Multivibrator oscillator

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Sequential Circuits

Transition-Triggered Monostable

In

DELAY td Out td

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Sequential Circuits

Monostable Trigger (RC-based)

VDD In R A C B Out (a) Trigger circuit.

In

VM

(b) Waveforms.

Out t1 t2

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Sequential Circuits

Astable Multivibrators (Oscillators)

0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

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Sequential Circuits

Relaxation Oscillator
Out1 I1 I2 Out2

R Int

T = 2 (log3) RC
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Sequential Circuits

Voltage Controller Oscillator (VCO)

VD D
M6

VDD
M4

Schmitt Trigger restores signal slopes

M2

In
M1

Iref Vcontr
M3 M5

Iref

Current starved inverter

t pH L (nsec)

4 2

0.0 0.5

1.5

V co ntr (V)

2.5

propagation delay as a function of control voltage

Digital Integrated Circuits2nd

Sequential Circuits

Differential Delay Element and VCO

V o2 in 1 V o1 v1 in 2 v2 v
4

v3

V ctrl

delay cell
3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 0.5 0.5 1.5 time (ns) 2.5 3.5 V1 V2 V3 V4

two stage VCO

simulated waveforms of 2-stage VCO

Digital Integrated Circuits2nd

Sequential Circuits