FPGA Synthesizer

03-5773693 ext 166 Email: [email protected]

CIC Training Manual

HDL Design Flow & Tools - 1

Course Outline
uHDL Design Flow & Tools uHDL Coding Hints uExplore Synopsys FPGA Express Tool

CIC Training Manual

HDL Design Flow & Tools - 2

HDL Design Flow & Tools

u FPGA Design Flow
Design Ideas Detailed Design Functional Simulation Synthesis & Implementation Timing Simulation Device Programming

u Altera HDL Design Flow & Tools u Xilinx HDL Design Flow & Tools

CIC Training Manual

HDL Design Flow & Tools - 3

FPGA/CPLD Design Flow

Design Design Ideas Ideas

Detailed Detailed Design Design

Functional Functional Simulation Simulation

Device Device Programming Programming

FPGA CPLD

Timing Timing Simulation Simulation

t pd=22.1ns f max=47.1MHz

Synthesis Synthesis& & Implementation Implementation

CIC Training Manual

HDL Design Flow & Tools - 4

Design Ideas
u What are the main design considerations?
Design feasibility? Design spec? Cost? FPGA/CPLD or ASIC? Which FPGA/CPLD vendor? Which device family? Development time?

CIC Training Manual

HDL Design Flow & Tools - 5

Detailed Design
u Choose the design entry method
Schematic Gate level design Intuitive & easy to debug HDL (Hardware Description Language), e.g. Verilog & VHDL Descriptive & portable Easy to modify Mixed HDL & schematic

u Manage the design hierarchy

Design partitioning Chip partitioning Logic partitioning Use vendor-supplied libraries or parameterized libraries to reduce design time Create & manage user-created libraries (circuits)
CIC Training Manual HDL Design Flow & Tools - 6

Functional Simulation
u Preparation for simulation
Generate simulation patterns Waveform entry HDL testbench Generate simulation netlist

u Functional simulation
To verify the functionality of your design only

u Simulation results
Waveform display Text output

u Challenge
Sufficient & efficient test patterns

CIC Training Manual

HDL Design Flow & Tools - 7

HDL Synthesis
assign z=a&b

u Synthesis = Translation + Optimization

Translate HDL design files into gate-level netlist Optimize according to your design constraints Area constraints Timing constraints Power constraints ...

a b

u Main challenges
Learn synthesizable coding style Write correct & synthesizable HDL design files Specify reasonable design constraints Use HDL synthesis tool efficiently

CIC Training Manual

HDL Design Flow & Tools - 8

Design Implementation
a b z
FPGA CPLD

u Implementation flow
Netlist merging, flattening, data base building Design rule checking Logic optimization Block mapping & placement Net routing Configuration bitstream generation

01011...

u Implementation results
Design error or warnings Device utilization Timing reports

u Challenge
How to reach high performance & high utilization implementation?

CIC Training Manual

HDL Design Flow & Tools - 9

Timing Analysis & Simulation

uTiming analysis
Timing analysis is static, i.e., independent of input & output patterns To examine the timing constraints To show the detailed timing paths Can find the critical path
t pd=22.1ns f max=47.1MHz

u Timing simulation
To verify both the functionality & timing of the design

CIC Training Manual

HDL Design Flow & Tools - 10

Device Programming
u Choose the appropriate configuration scheme
SRAM-based FPGA/CPLD devices Downloading the bitstream via a download cable Programming onto a non-volatile memory device & attaching it on the circuit board OTP, EPROM, EEPROM or Flash-based FPGA/CPLD devices Using hardware programmer ISP
FPGA CPLD

u Finish the board design u Program the device u Challenge

Board design System considerations

CIC Training Manual

HDL Design Flow & Tools - 11

Our Focus: HDL Design Flow

u Why HDL?
Can express digital systems in behavior or structure domain, shortening the design time Can support all level of abstraction, including algorithm, RTL, gate and switch level Both VHDL & Verilog are formal hardware description languages, thus portable

u Typical HDL design flow

Use VHDL or Verilog to express digital systems VHDL or Verilog simulation tool is required to simulate your project Use high-level synthesis tool to obtain structural level design Then use FPGA placement & routing tools to obtain physical FPGA netlist

u We assume you are familiar with VHDL or Verilog...

In this course, we ll emphasize on FPGA HDL coding techniques for synthesis It s the key issue to reduce area and achieve high performance for your project We assume you know how to use VHDL or Verilog simulator too

CIC Training Manual

HDL Design Flow & Tools - 12

Altera HDL Design Flow

Design DesignEntry: Entry: Verilog/VHDL Verilog/VHDL Functional Simulation Design DesignVerification Verification (Verilog-XL/VSS) (Verilog-XL/VSS) Timing Simulation HDL HDLSynthesis Synthesis (FPGA (FPGACompiler) Compiler)

Third-Party Altera
MAX+PLUS MAX+PLUSII II Compiler Compiler Synthesis & Fitting, Partitioning, Placement, Routing MAX+PLUS MAX+PLUSII II Timing Analyzer Timing Analyzer Timing Analysis MAX+PLUS MAX+PLUSII II Programmer Programmer Device Programming

CIC Training Manual

HDL Design Flow & Tools - 13

Xilinx HDL Design Flow

Design DesignEntry: Entry: Verilog/VHDL Verilog/VHDL Functional Simulation Design DesignVerification Verification (Verilog-XL/VSS) (Verilog-XL/VSS) Timing Simulation Logic LogicSynthesis Synthesis (FPGA (FPGACompiler) Compiler)

Third-Party Xilinx
Alliance AllianceSeries Series XACT step XACT stepM1 M1 Optimization, Mapping, Placement & Routing M1 M1Timing Timing Analyzer Analyzer Timing Analysis M1 M1Hardware Hardware Debugger Debugger Device Programming

CIC Training Manual

HDL Design Flow & Tools - 14

Design Entry
u Write HDL design files
Must learn synthesizable RTL Verilog or VHDL coding style for the synthesis tool Tool: text editor library IEEE; use IEEE.STD_LOGIC_1164.all; xedit, textedit, vi, joe, ... entity converter is
port ( i3, i2, i1, i0: in STD_LOGIC; a, b, c, d, e, f, g: out STD_LOGIC); end converter; module converter(i3,i2,i1,i0,a,b,c,d,e,f,g); input i3, i2, i1, i0 ; output a, b, c, d, e, f, g; reg a,b,c,d,e,f,g; always @(i3 or i2 or i1 or i0) begin case({i3,i2,i1,i0}) 4'b0000: {a,b,c,d,e,f,g}=7'b1111110; 4'b0001: {a,b,c,d,e,f,g}=7'b1100000; 4'b0010: {a,b,c,d,e,f,g}=7'b1011011; 4'b0011: {a,b,c,d,e,f,g}=7'b1110011; 4'b0100: {a,b,c,d,e,f,g}=7'b1100101; 4'b0101: {a,b,c,d,e,f,g}=7'b0110111; 4'b0110: {a,b,c,d,e,f,g}=7'b0111111; 4'b0111: {a,b,c,d,e,f,g}=7'b1100010; 4'b1000: {a,b,c,d,e,f,g}=7'b1111111; 4'b1001: {a,b,c,d,e,f,g}=7'b1110111; 4'b1010: {a,b,c,d,e,f,g}=7'b1101111; 4'b1011: {a,b,c,d,e,f,g}=7'b0111101; 4'b1100: {a,b,c,d,e,f,g}=7'b0011110; 4'b1101: {a,b,c,d,e,f,g}=7'b1111001; 4'b1110: {a,b,c,d,e,f,g}=7'b0011111; 4'b1111: {a,b,c,d,e,f,g}=7'b0001111; endcase end endmodule
CIC Training Manual

architecture case_description of converter is begin P1: process(i3, i2, i1, i0) variable tmp_in: STD_LOGIC_VECTOR(3 downto 0); begin tmp_in := i3 & i2 & i1 & i0; case tmp_in is when "0000" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1111110"); when "0001" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1100000"); when "0010" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1011011"); when "0011" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1110011"); when "0100" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1100101"); when "0101" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0110111"); when "0110" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0111111"); when "0111" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1100010"); when "1000" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1111111"); when "1001" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1110111"); when "1010" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1101111"); when "1011" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0111101"); when "1100" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0011110"); when "1101" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1111001"); when "1110" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0011111"); when "1111" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("0001111"); when others => (a,b,c,d,e,f,g) <= STD_LOGIC_vector'("0000000"); end case; end process P1; end case_description;
HDL Design Flow & Tools - 15

HDL Functional Simulation

u Write HDL testbench files u Prepare technology-dependent simulation model, if necessary u Verilog functional simulation
Tool: Verilog simulator F Cadence Verilog-XL Viewlogic VCS

u VHDL functional simulation

Tool: VHDL simulator F Synopsys VSS Viewlogic SpeedWave Cadence LeapFrog

CIC Training Manual

HDL Design Flow & Tools - 16

Verilog Functional Simulation

CIC Training Manual

HDL Design Flow & Tools - 17

VHDL Functional Simulation

CIC Training Manual

HDL Design Flow & Tools - 18

HDL Synthesis
u Prepare synthesis library u Transfer HDL design file into gate-level netlist
Tool: HDL synthesis software F Synopsys: Design Analyzer, HDL/VHDL Compiler & FPGA Compiler Viewlogic ViewSynthesis (for VHDL only) Cadence Synergy Generate EDIF netlist file (*.edf) for Altera design Generate XNF netlist files (*.sxnf) for Xilinx design

CIC Training Manual

HDL Design Flow & Tools - 19

FPGA Implementation
u Gate-level netlist -> configuration bitstream & timing information
Altera development tool: Altera MAX+PLUS II software MAX+PLUS II Compiler MAX+PLUS II Floorplan Editor Xilinx development tool: Xilinx XACTstep M1 software Xilinx Design Manager Flow Engine EPIC Design Editor

CIC Training Manual

HDL Design Flow & Tools - 20

Altera Implementation

CIC Training Manual

HDL Design Flow & Tools - 21

Xilinx Implementation

CIC Training Manual

HDL Design Flow & Tools - 22

Timing Analysis
u Check critical timing path & clock rate
Altera timing analysis tool: Altera MAX+PLUS II Timing Analyzer Xilinx timing analysis tool: Xilinx Timing Analyzer

CIC Training Manual

HDL Design Flow & Tools - 23

Altera Timing Analysis

CIC Training Manual

HDL Design Flow & Tools - 24

Xilinx Timing Analysis

CIC Training Manual

HDL Design Flow & Tools - 25

Timing Simulation
u Generate timing HDL files and delay back-annotation files
Altera tool: MAX+PLUS II Compiler Xilinx tool: ngdanno, ngd2vhd, ngd2ver utilities

u Prepare testbench files u Prepare technology-dependent simulation model, if necessary u Verilog timing simulation
Tool: Verilog simulator

u VHDL timing simulation

Tool: VHDL simulator

CIC Training Manual

HDL Design Flow & Tools - 26

Verilog Timing Simulation

CIC Training Manual

HDL Design Flow & Tools - 27

VHDL Timing Simulation

CIC Training Manual

HDL Design Flow & Tools - 28

Device Programming
u Prepare the configuration bitstream file u Configure FPGA device(s)
By downloading the configuration bitstream via a download cable By programming the configuration bitstream onto a non-volatile memory device & attaching it on the circuit board

download cable

FPGA

output display
CIC Training Manual HDL Design Flow & Tools - 29