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Gate Diffusion Input(GDI):A Power Efficient Method For Digital Combinational Circuits

Presented By: Vijaya Shekhawat M.Tech (VLSI Design) IInd Year Enrollment No:080619

CONTENTS
Motivation Circuit Design Style Gate Diffusion Input (GDI) Modified GDI Technique Conclusion References

Motivation
Market demands high performance low power portable electronic

devices powered by batteries

Higher performance devices Higher integration of transistor Higher power dissipation/unit area

Higher energy densities can become explosive

Reliability issues Every 10 C increase in temperature roughly doubles electronic component failure rate Expensive packaging and cooling systems cost increase with increase in power dissipation Lower the power then delay increase
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Circuit Design Style

CMOS Logic Style
Pass Transistor Logic Style (PTL)

Transmission Gate Logic Style (TG)

Pseudo nMOS Logic Style

Complementary Pass Transistor Logic(CPL)

Double Pass Transistor Logic (DPL)
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CMOS Logic Style

Most commonly used logic in VLSI

design
Ease of use, well developed

synthesis methods

High noise margins

Low power consumption No static power dissipation Good current driving capabilities

CMOS INVERTER
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Pass Transistor Logic Style (PTL)

Widely used alternative to

complementary CMOS
Fewer transistors are required for a given function

Reduced number of transistors

means there is lower capacitance Dedicated buffers need to be inserted to boost driving strength XNOR Gate using PTL
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Transmission Gate Logic Style (TG)

It solves the problem of low logic

level swing by using pMOS as well

as nMOS It act as Bidirectional switch.

But, it require large no transistors

Design is much complex because control signal requires both true and Symbol of Transmission Gate

complementary form

Pseudo nMOS Logic Style

Used where majority of outputs are high, viz address decoder in memory No. of transistors for N-input= N+1 Less no of transistor required High Speed Swing degradation Non Zero static power dissipation Logic Network of Pseudo nMOS Style Ratio pMOS

Complementary Pass Transistor Logic(CPL)

Every signal and its complement

is generated
Modular design Useful for modular (array) circuits like adders, multipliers, barrel shifter, etc.
And and Nand Gate using CPL

Swing degradation

Buffer required

Double Pass Transistor Logic (DPL)

Double pass-transistor logic

(DPL)

uses

complementary

transistors to keep full swing operation

This eliminates the need for

restoration circuitry One disadvantage of DPL is the

large area used due to the

XNOR and XOR gate using DPL presence of PMOS transistors

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Gate Diffusion Input (GDI)

The problem of existing PTL is top-down logic design complexity

One of the main reasons for this is that no simple and universal
cell library is available for PTL-based design The new low-power design technique that allows solving most of the problems mentioned abovegate diffusion input (GDI) technique This method is suitable for design of fast, low-power circuits,

using a reduced number of transistors, while improving logic level

swing and static power characteristics and allowing simple topdown design by using small cell library
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Basic GDI Function

The GDI method is based on the use

of a simple cell as shown in Figure. At

first glance, the basic cell reminds one of the standard CMOS inverter, but there are some important differences 1) The GDI cell contains three input, P (input to the source/drain of pMOS), and N (input to the source/drain of
Basic GDI Cell

nMOS) 2) Bulks of both nMOS and pMOS are connected to N or P

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FUNCTIONS IMPLEMENTED USING GDI CELL AND THE TRANSISTORS REQUIRED USING STANDARD CMOS PROCESS

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Comparison of logic Function1 implemented by GDI and CMOS

GDI

CMOS

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Comparison of XNOR Gate implemented by GDI and CMOS

GDI

CMOS

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Analysis of GDI circuits

Operational Analysis of GDI Cell Fan-in and Fan-out Bounds in GDI Analysis of Swing-Restoring Buffers

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Operational Analysis of GDI Cell

To understand the effects of the low swing problem in a GDI cell, I suggest the analysis, based on the example of Function1 and can be easily extended to use in other GDI functions Table presents a full set of logic states and related functionality modes of Function1
A 0 0 B 0 1 Functionality PMOS Transmission Gate CMOS Inverter Output

Vtp
1

1
1

0
1

NMOS Transmission Gate

CMOS Inverter

0
0

The fact that demands special emphasis is that in about 50% of the cases (for B=1), the GDI cell operates as a regular CMOS inverter, which is widely used as a digital buffer for logic-level restoration
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Fan-in and Fan-out Bounds in GDI

Fan-out:
GDI approach allows definition of fan-out bounds by using the logic-effort concept. The logic effort is directly related to the fanout . The effort delay of the logic gate is the product of these two factors f=g.h

Fan-in:
Fan-in: The addition of diffusion inputs in GDI for the same structure results in an improved fan-in (i.e. (n+2)) where n input are in CMOS. Note that for F1 and F2 functions, where only one additional input applied to diffusion, the fan-in will increase by one compared to CMOS.
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Analysis of Swing-Restoring Buffers

The simplest method of swing restoration is to add a buffer stage after every GDI cell. Finally, several points have to be emphasized concerning the buffer insertion topology in GDI. 1) Buffer insertion has to be considered only in the case of linking GDI cells through diffusion inputs. No buffers are needed before gate inputs of GDI cells. 2) The mixed path topology can be used as an efficient method for buffer insertion. It allows one to reduce the number of buffers by intermittently involving diffusion and gate inputs in a given signal path. The designer should check the tradeoff between buffer insertion and delay, area, and power consumption to achieve an efficient swing restoration.
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Comparison between GDI and CMOS with respect to Power

60 50

40

30

GDI Power(W) CMOS Power(W)

20

10

0 MUX OR AND Function1 Function2

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Comparison between GDI and CMOS with respect to Delay

2.5

1.5 GDI Delay (nsec) CMOS Delay (nsec) 1

0.5

0 MUX OR AND Function1 Function2

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Modified GDI Technique

Gate Diffusion Input (GDI) logic style suffers from some practical

limitations like
swing degradation fabrication complexity in standard CMOS process

bulk connections
These limitations can be overcome by modified gate diffusion input (Mod-GDI) logic style.

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Basic Modified GDI Cell

The Mod-GDI cell uses standard four

terminal NMOS and PMOS transistor.

Modified-GDI [ModGDI] cell contains a low-voltage terminal SP configured to be connected to a high constant voltage and a high-voltage terminal SN configured to be connected to a low constant voltage .

In favor of improving logic level

Modified GDI Cell

swings and static power characteristics and allowing simple top-down design methodology a small cell library.
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Important feature of Modified GDI Technique

high-speed

low power circuits

using reduced number of transistors even as improving swing degradation

allowing easy top-down design by using a small cell library

The Mod-GDI cell be capable of as well implemented in all kinds of non-standard technologies, like twin-well CMOS technology, Silicon on Insulator (SOI) technology and Silicon on Sapphire (SOS) technology

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VARIOUS LOGIC FUNCTIONS

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Comparison Modified GDI and CMOS

Power
60 2.5 50

Delay

40 1.5 30 MOD-GDI Power(W) CMOS Power(W) 20 1 MOD-GDI Delay (n sec) CMOS Delay (n sec)

10

0.5

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Conclusion
Simulation results shows up to 45% reduction in power-delay product in Mod-GDI. Mod-GDI gates lower the transistor count The leakage power and switching power of Mod-GDI gates is lower than the traditional logic styles. The problem of fabrication of GDI gates in standard nano-scale CMOS process is overcome by connecting the sources of PMOS and NMOS to VDD and GND respectively in Mod-GDI logic style. The problem of threshold drop is not a very serious issue in deep sub-nm regions. The Mod-GDI logic style based design adopts interruption of inverter to alleviate the problem of signal degradation during propagation. This proposed logic style is analyzed to exploit the high speed potential and low power feature of Mod-GDI based circuit applications. In short, the proposed Mod-GDI logic style based designs can be taken a 27 better alternative in future.

References
[1]Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner, Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol. 10, No. 5, October 2002, pp. 566-581. [2]Arkadiy Morgenshtein, Alexander Fish and Israel A. Wagner, Gate Diffusion Input (GDI) - A technique for low power design of digital circuits: Analysis and characterization, Prod. IEEE 2002, pp. 477-480. [3]Padmanabhan Balsubramanian, Johince John, Low Power Digital Design using modified GDI , Prod. IEEE 2006. [4]Arkadiy Morgenshtein, Idan Shwartz and Alexander Fish, Gate Diffusion Input (GDI) Logic in Standard CMOS Nanoscale Process, IEEE 26-th Convention of Electrical and Electronics Engineers in Israel 2010, pp. 776-780. [5]Madhusudhan Dangeti, S.N.Singh, Minimization of Transistors Count and Power in an Embedded System using GDI Technique: A realization with digital circuits, International Journal of Electronics and Electrical Engineerin, ISSN : 2277-7040, Volume 2 Issue 9, September 2012, pp. 21-30. [6]Kunal and Nidhi Kedia, GDI Technique: A Power-Efficient Method for Digital Circuit,International Journal of Advanced Electrical and Electronics Engineering, (IJAEEE), ISSN (Print): 2278-8948, Volume-1, Issue-3, 2012, pp 87-93. [7]Pankaj Verma, Ruchi Singh and Y. K. Mishra,, Modified GDI Technique - A Power EfficientMethod For Digital Circuit Design, International Journal of Electronics and Computer Science Engineering, ISSN- 22771956, Volume2, Number 4, 2013, pp 1071-1080. [8]http://www.tanner.com/EDA/product/index.html [9]http://www.tanner.com/EDA/product/Tools_SchematicCapture.html

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