Chapter 1.

Basic
Structure of Computers

Functional Units

Functional Units
Arithmetic
and
logic

Input
Memory
Output

Control

I/O

Figure1.1.Basicfunctionalunitsofacomputer.

Processor

Information Handled by a
Computer
Instructions/machine

instructions

Govern the transfer of information within a computer as

well as between the computer and its I/O devices
Specify the arithmetic and logic operations to be
performed
Program

Data

Used as operands by the instructions

Source program

Encoded

in binary code 0 and 1

Memory Unit
Store

programs and data

Two classes of storage

Primary storage

Fast
Programs must be stored in memory while they are being executed
Large number of semiconductor storage cells
Processed in words
Address
RAM and memory access time
Memory hierarchy cache, main memory

Secondary storage larger and cheaper

Arithmetic and Logic Unit

(ALU)
Most

computer operations are executed in

ALU of the processor.
Load the operands into memory bring them
to the processor perform operation in ALU
store the result back to memory or retain in
the processor.
Registers
Fast control of ALU

Control Unit

All computer operations are controlled by the control

unit.
The timing signals that govern the I/O transfers are
also generated by the control unit.
Control unit is usually distributed throughout the
machine instead of standing alone.
Operations of a computer:
Accept information in the form of programs and data through an
input unit and store it in the memory
Fetch the information stored in the memory, under program control,
into an ALU, where the information is processed
Output the processed information through an output unit
Control all activities inside the machine through a control unit

The processor : Data Path and

Control

Two types of functional units:

elements that operate on data values (combinational)
elements that contain state (state elements)

Five Execution Steps

Step name

Action for R-type

instructions

Action for Memoryreference Instructions

Action for
branches

Instruction fetch

IR = MEM[PC]
PC = PC + 4

Instruction decode/ register

fetch

A = Reg[IR[25-21]]
B = Reg[IR[20-16]]
ALUOut = PC + (sign extend (IR[15-0])<<2)

Execution, address
computation, branch/jump
completion

ALUOut = A op B

ALUOut = A+sign
extend(IR[15-0])

Memory access or R-type

completion

Reg[IR[15-11]] =
ALUOut

Load:MDR =Mem[ALUOut]
or
Store:Mem[ALUOut] = B

Memory read completion

Load: Reg[IR[20-16]] =
MDR

IF(A==B) Then
PC=ALUOut

Action for
jumps

PC=PC[3128]||(IR[250]<<2)

Basic Operational
Concepts

Review

Activity in a computer is governed by instructions.

To perform a task, an appropriate program
consisting of a list of instructions is stored in the
memory.
Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
Data to be used as operands are also stored in the
memory.

A Typical Instruction

Add LOCA, R0
Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
Place the sum into register R0.
The original contents of LOCA are preserved.
The original contents of R0 is overwritten.
Instruction is fetched from the memory into the
processor the operand at LOCA is fetched and
added to the contents of R0 the resulting sum is
stored in register R0.

Separate Memory Access and

ALU Operation
Load

LOCA, R1
Add R1, R0
Whose contents will be overwritten?

Connection Between the

Processor and the Memory
Memory

MAR

MDR
Control

PC

R0
R1

Processor

IR
ALU
Rn

ngeneralpurpose
registers

Figure1.2.Connectionsbetweentheprocessorandthememory.

Registers
Instruction

register (IR)
Program counter (PC)
General-purpose register (R0 Rn-1)
Memory

address register (MAR)

Memory data register (MDR)

Typical Operating Steps

Programs

reside in the memory through input

devices
PC is set to point to the first instruction
The contents of PC are transferred to MAR
A Read signal is sent to the memory
The first instruction is read out and loaded
into MDR
The contents of MDR are transferred to IR
Decode and execute the instruction

Typical Operating Steps

(Cont)
Get

operands for ALU

General-purpose register
Memory (address to MAR Read MDR to ALU)

Perform

operation in ALU
Store the result back

To general-purpose register
To memory (address to MAR, result to MDR Write)

During

the execution, PC is incremented

to the next instruction

Interrupt

Normal execution of programs may be preempted if

some device requires urgent servicing.
The normal execution of the current program must
be interrupted the device raises an interrupt
signal.
Interrupt-service routine
Current system information backup and restore (PC,
general-purpose registers, control information,
specific information)

Bus Structures
There

are many ways to connect different

parts inside a computer together.
A group of lines that serves as a connecting
path for several devices is called a bus.
Address/data/control

Bus Structure
Single-bus

Input

Output

Memory

Figure1.3.Singlebusstructure.

Processor

Speed Issue
Different

devices have different

transfer/operate speed.
If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be
very low.
How to solve this?
A common approach use buffers.

Performance

Performance
The

most important measure of a computer is

how quickly it can execute programs.
Three factors affect performance:

Hardware design
Instruction set
Compiler

Performance

Processor time to execute a program depends on the hardware

involved in the execution of individual machine instructions.
Main
memory

Cache
memory

Bus

Figure1.5.

Theprocessorcache.

Processor

Performance
The

processor and a relatively small cache

memory can be fabricated on a single
integrated circuit chip.
Speed
Cost
Memory management

Processor Clock
Clock,

clock cycle, and clock rate

The execution of each instruction is divided
into several steps, each of which completes
in one clock cycle.
Hertz cycles per second

Basic Performance Equation

T processor time required to execute a program that has been

prepared in high-level language
N number of actual machine language instructions needed to
complete the execution (note: loop)
S average number of basic steps needed to execute one
machine instruction. Each step completes in one clock cycle
R clock rate
Note: these are not independent to each other

N S
T
R
How to improve T?

Pipeline and Superscalar

Operation

Instructions are not necessarily executed one after

another.
The value of S doesnt have to be the number of
clock cycles to execute one instruction.
Pipelining overlapping the execution of successive
instructions.
Add R1, R2, R3
Superscalar operation multiple instruction
pipelines are implemented in the processor.
Goal reduce S (could become <1!)

Clock Rate
Increase

clock rate

Improve the integrated-circuit (IC) technology to make

the circuits faster
Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps
needed)

Increases

in R that are entirely caused by

improvements in IC technology affect all
aspects of the processors operation equally
except the time to access the main memory.

CISC and RISC

Tradeoff

between N and S
A key consideration is the use of pipelining

S is close to 1 even though the number of basic steps

per instruction may be considerably larger
It is much easier to implement efficient pipelining in
processor with simple instruction sets

Reduced

Instruction Set Computers (RISC)

Complex Instruction Set Computers (CISC)

Compiler

A compiler translates a high-level language program

into a sequence of machine instructions.
To reduce N, we need a suitable machine instruction
set and a compiler that makes good use of it.
Goal reduce NS
A compiler may not be designed for a specific
processor; however, a high-quality compiler is
usually designed for, and with, a specific processor.

Performance Measurement

T is difficult to compute.
Measure computer performance using benchmark programs.
System Performance Evaluation Corporation (SPEC) selects and
publishes representative application programs for different application
domains, together with test results for many commercially available
computers.
Compile and run (no simulation)
Reference computer

Running time on the reference computer

SPEC rating
Running time on the computer under test
n

SPEC rating ( SPECi )

i 1

1
n

Multiprocessors and
Multicomputers

Multiprocessor computer

Execute a number of different application tasks in parallel

Execute subtasks of a single large task in parallel
All processors have access to all of the memory shared-memory
multiprocessor
Cost processors, memory units, complex interconnection networks

Multicomputers

Each computer only have access to its own memory

Exchange message via a communication network messagepassing multicomputers

Chapter 2. Machine
Instructions and
Programs

Objectives

Machine instructions and program execution,

including branching and subroutine call and return
operations.
Number representation and addition/subtraction in
the 2s-complement system.
Addressing methods for accessing register and
memory operands.
Assembly language for representing machine
instructions, data, and programs.
Program-controlled Input/Output operations.

Number, Arithmetic
Operations, and
Characters

Signed Integer
3

major representations:
Sign and magnitude
Ones complement
Twos complement

Assumptions:

4-bit machine word

16 different values can be represented
Roughly half are positive, half are negative

Sign and Magnitude

Representation
-7
-6
-5

1111
1110

+0
+1

0000
0001

1101

0010

+2

-4

1100

0011

+3

0 100 = + 4

-3

1011

0100

+4

1 100 = - 4

-2

1010

0101

1001

-1

0110
1000

-0

0111

+5

+6

+7

High order bit is sign: 0 = positive (or zero), 1 = negative

Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0

Ones Complement
Representation
-0
-1
-2

1111
1110

+0
0000
0001

1101

+1

0010

+2

-3

1100

0011

+3

0 100 = + 4

-4

1011

0100

+4

1 011 = - 4

-5

1010

0101

1001

-6

0110
1000

-7

0111

+5

+6

+7

Subtraction implemented by addition & 1's complement

Still two representations of 0! This causes some problems
Some complexities in addition

Twos Complement
Representation
-1
-2
-3
like 1's comp
except shifted
one position
clockwise

1111
1110

+0
0000
0001

1101

+1

0010

+2

-4

1100

0011

+3

0 100 = + 4

-5

1011

0100

+4

1 100 = - 4

-6

1010

0101

1001

-7

0110
1000

-8

0111

+5

+6

+7

Only one representation for 0

One more negative number than positive
number

Binary, Signed-Integer
Representations
B

Page 28

Valuesrepresented

b3 b2b1b0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1

1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1

Signand
magnitude
+7
+6
+5
+4
+3
+2
+1
+0
0
1
2
3
4
5
6
7

1' scomplement
+7
+6
+5
+4
+3
+2
+1
+0
7
6
5
4
3
2
1
0

2' scomplement
+
+
+
+
+
+
+
+

Figure2.1.Binary,signedintegerrepresentations.

7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1

Addition and Subtraction 2s

Complement

If carry-in to the high

order bit =
carry-out then ignore
carry
if carry-in differs from
carry-out then overflow

0100

-4

1100

+3

0011

+ (-3)

1101

0111

-7

11001

0100

-4

1100

-3

1101

+3

0011

10001

-1

1111

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems

2s-Complement Add and

Subtract Operations
(a)

0010
+ 0011

( + 2)
( + 3)

0101

( + 5)

(c)

1011
+ 1110
1001

5
2
7

(e)

1101
1001

3
7

Page 31

(f)

(g)

(h)

(i)

(j)

0010
0100
0110
0011
1001
1011
1001
0001
0010
1101

( + 2)
( + 4)
( + 6)
( + 3)
7
5
7
( + 1)
( + 2)
3

(b)

0111
+ 1101
0100

( + 4)
6
2
( + 7)
3
( + 4)

1101
+ 0111
0100

( + 4)

0100
+ 1010
1110

(d)

0010
+ 1100
1110
0110
+ 1101
0011
1001
+ 0101
1110

( + 3)

1001
+ 1111
1000

0010
+ 0011
0101

( + 5)

Figure2.4.2'scomplementAddandSubtractoperations.

Overflow - Add two positive numbers to get a

negative number or two negative numbers to
get a positive number
-1
-2

0000

0010

1100

0100

1010

0101

1001

-7

0110
1000

-8

0111

+6

+7
5 + 3 = -8

+3
+4
+5

1111

0000

+1

0001

1101

-4
-5

+0

1110

-3

+2

0011

1011

-6

-2

+1

0001

1101

-4
-5

1111
1110

-3

-1

+0

0010

1100
1011
1010

-6

0110
1000

-8
-7 - 2 = +7

0011

+3

0100

+4

0101

1001

-7

+2

0111

+7

+6

+5

Overflow Conditions
5

0111
0101

-7

1000
1001

0011

-2

1100

-8

1000

10111

Overflow

Overflow
5

0000
0101

-3

1111
1101

0010

-5

1011

0111

-8

11000

No overflow

No overflow

Overflow when carry-in to the high-order bit does not equal carry out

Sign Extension

Task:
Given w-bit signed integer x
Convert it to w+k-bit integer with same value
Rule:
Make k copies of sign bit:
X = xw1 ,, xw1 , xw1 , xw2 ,, x0
X

k copies of MSB

Sign Extension Example

short int x = 15213;

int
ix = (int) x;
short int y = -15213;
int
iy = (int) y;
x
ix
y
iy

Decimal
Hex
Binary
3B6D
0011101101101101
15213
15213 0000C492 00000000000000000011101101101101
C493
1100010010010011
-15213
-15213 FFFFC493 11111111111111111100010010010011

Memory Locations,
Addresses, and
Operations

Memory Location, Addresses,

and Operation
nbits

Memory consists
of many millions of
storage cells,
each of which can
store 1 bit.
Data is usually
accessed in n-bit
groups. n is called
word length.

firstword
secondword

ithword

lastword

Figure2.5.Memorywords.

Memory Location, Addresses,

and Operation
32-bit

word length example

32bits

b 31 b 30

b1

Signbit: b 31= 0 forpositivenumbers

b 31= 1 fornegativenumbers
(a)Asignedinteger

8bits

8bits

8bits

8bits

ASCII
character

ASCII
character

ASCII
character

ASCII
character

(b)Fourcharacters

b0

Memory Location, Addresses,

and Operation

To retrieve information from memory, either for one

word or one byte (8-bit), addresses for each location
are needed.
A k-bit address memory has 2k memory locations,
namely 0 2k-1, called memory space.
24-bit memory: 224 = 16,777,216 = 16M (1M=220)
32-bit memory: 232 = 4G (1G=230)
1K(kilo)=210
1T(tera)=240

Memory Location, Addresses,

and Operation
It

is impractical to assign distinct addresses to

individual bit locations in the memory.
The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory byteaddressable memory.
Byte locations have addresses 0, 1, 2, If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,

Big-Endian and Little-Endian

Assignments

Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address

Byteaddress

Byteaddress

2 4

2 4

2 3

2 2

2 1

(a)Bigendianassignment

2 4

2 1

2 2

2 3

2 4

(b)Littleendianassignment

Figure2.7.Byteandwordaddressing.

Memory Location, Addresses,

and Operation
Address

ordering of bytes
Word alignment

Words are said to be aligned in memory if they

begin at a byte addr. that is a multiple of the num
of bytes in a word.

16-bit word: word addresses: 0, 2, 4,.

32-bit word: word addresses: 0, 4, 8,.
64-bit word: word addresses: 0, 8,16,.

Access

strings

numbers, characters, and character

Memory Operation
Load

Copy the content. The memory content doesnt change.

Address Load
Registers can be used

Store

(or Read or Fetch)

(or Write)

Overwrite the content in memory

Address and Data Store
Registers can be used

Instruction and
Instruction
Sequencing

Must-Perform Operations
Data

transfers between the memory and the

processor registers
Arithmetic and logic operations on data
Program sequencing and control
I/O transfers

Register Transfer Notation

Identify

a location by a symbolic name

standing for its hardware binary address
(LOC, R0,)
Contents of a location are denoted by placing
square brackets around the name of the
location (R1[LOC], R3 [R1]+[R2])
Register Transfer Notation (RTN)

Assembly Language Notation

Represent

machine instructions and

programs.
Move LOC, R1 = R1[LOC]
Add R1, R2, R3 = R3 [R1]+[R2]

CPU Organization
Single

Accumulator

Result usually goes to the Accumulator

Accumulator has to be saved to memory quite often

General

Register

Registers hold operands thus reduce memory traffic

Register bookkeeping

Stack

Operands and result are always in the stack

Instruction Formats

Three-Address Instructions

ADD

R1, R2

R1 R1 + R2

ADD

AC AC + M[AR]

Zero-Address Instructions

R1 R2 + R3

One-Address Instructions

R1, R2, R3

Two-Address Instructions

ADD

ADD

TOS TOS + (TOS 1)

RISC Instructions

Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

Instruction Formats
Example: Evaluate (A+B) (C+D)
Three-Address
1.
2.
3.

ADD
ADD
MUL

R1, A, B
R2, C, D
X, R1, R2

; R1 M[A] + M[B]
; R2 M[C] + M[D]
; M[X] R1 R2

Instruction Formats
Example: Evaluate (A+B) (C+D)
Two-Address
1.
2.
3.
4.
5.
6.

MOV
ADD
MOV
ADD
MUL
MOV

R1, A
R1, B
R2, C
R2, D
R1, R2
X, R1

; R1 M[A]
; R1 R1 + M[B]
; R2 M[C]
; R2 R2 + M[D]
; R1 R1 R2
; M[X] R1

Instruction Formats
Example: Evaluate (A+B) (C+D)
One-Address
1.
2.
3.
4.
5.
6.
7.

LOAD A
ADD B
STORET
LOAD C
ADD D
MUL T
STOREX

; AC M[A]
; AC AC + M[B]
; M[T] AC
; AC M[C]
; AC AC + M[D]
; AC AC M[T]
; M[X] AC

Instruction Formats
Example: Evaluate (A+B) (C+D)
Zero-Address
1.
2.
3.
4.
5.
6.
7.

8.

PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
(C+D)(A+B)
POP X

; TOS A
; TOS B
; TOS (A + B)
; TOS C
; TOS D
; TOS (C + D)
; TOS
; M[X] TOS

Instruction Formats
Example: Evaluate (A+B) (C+D)
RISC
1.
2.
3.
4.
5.
6.
7.
8.

LOAD R1, A
LOAD R2, B
LOAD R3, C
LOAD R4, D
ADD R1, R1, R2
ADD R3, R3, R4
MUL R1, R1, R3
STOREX, R1

; R1 M[A]
; R2 M[B]
; R3 M[C]
; R4 M[D]
; R1 R1 + R2
; R3 R3 + R4
; R1 R1 R3
; M[X] R1

Using Registers
Registers

are faster
Shorter instructions

The number of registers is smaller (e.g. 32

registers need 5 bits)

Potential

speedup
Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.

Instruction Execution and

Straight-Line Sequencing
Address
Beginexecutionhere

Contents

Move A,R0

i+4

Add

i+8

Move R0,C

B,R0

3instruction
program
segment

Datafor
theprogram

Assumptions:
- One memory operand
per instruction
- 32-bit word length
- Memory is byte
addressable
- Full memory address
can be directly specified
in a single-word instruction
Two-phase procedure
-Instruction fetch
-Instruction execute
Page 43

Figure2.8.AprogramforC+

Branching

Move

NUM1,R0

i+4

Add

NUM2,R0

i+8

Add

NUM3,R0

i + 4n 4

Add

NUMn,R0

i + 4n

Move

R0,SUM

SUM

NUM1
NUM2

NUMn

Figure2.9.Astraightlineprogramforaddingnnumbers.

Branching

LOOP
Program
loop

Branch target

Move

N,R1

Clear

R0

Determineaddressof
"Next"numberandadd
"Next"numbertoR0
Decrement

R1

Branch>0

LOOP

Move

R0,SUM

Conditional branch

SUM
N

NUM1

Figure2.10.Usingalooptoaddnnumbers.

NUM2

NUMn

Condition Codes
Condition

code flags
Condition code register / status register
N (negative)
Z (zero)
V (overflow)
C (carry)
Different instructions affect different flags

Conditional Branch
Instructions
Example:

A: 1 1 1 1 0 0 0 0
B: 0 0 0 1 0 1 0 0

A:

11110000

+(B): 1 1 1 0 1 1 0 0
11011100
C=1
S=1
V=0

Z=0

Status Bits
Cn-1

ALU

Cn

C
Fn-1

Zero Check

Addressing
Modes

Generating Memory Addresses

How

to specify the address of branch target?

Can we give the memory operand address
directly in a single Add instruction in the
loop?
Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.

Addressing Modes
Implied

Opcode Mode

...

AC is implied in ADD M[AR] in One-Address

instr.
TOS is implied in ADD in Zero-Address instr.

Immediate

The use of a constant in MOV R1, 5, i.e. R1

5

Register

Indicate which register holds the operand

Addressing Modes
Register

Indirect

Indicate the register that holds the number of the

register that holds the operand
R1

MOV

R1, (R2)

Autoincrement

Access & update in 1 instr.

Direct

/ Autodecrement

R2 = 3
R3 = 5

Address

Use the given address to access a memory location

Addressing Modes
Indirect

Address

Indicate the memory location that holds the

address of the memory location that holds the
data
AR = 101
100
101
102
103
104

0 1 0 4

1 1 0 A

Addressing Modes
Relative

Address

EA = PC + Relative Addr
PC = 2

0
1
2

AR = 100

Could be Positive
or Negative
(2s Complement)

100
101
102
103
104

1 1 0 A

Addressing Modes
Indexed

EA = Index Register + Relative Addr

Useful with
Autoincrement or
Autodecrement

XR = 2
+

AR = 100
Could be Positive
or Negative
(2s Complement)

100
101
102
103
104

1 1 0 A

Addressing Modes
Base

Register

EA = Base Register + Relative Addr

Could be Positive
or Negative
(2s Complement)

AR = 2
+

BR = 100

Usually points
to the beginning
of an array

100
101
102
103
104

0
0
0
0
0

0
0
0
1
0

0
1
0
0
5

5
2
A
7
9

Addressing Modes
Name

The different
ways in which
the location of
an operand is
specified in
an instruction
are referred to
as addressing
modes.

Assembler syntax

Addressing
function

Immediate

#Value

Operand=Value

Register

Ri

EA = Ri

Absolute(Direct)

LOC

EA = LOC

Indirect

(Ri )
(LOC)

EA = [Ri ]
EA = [LOC]

Index

X(Ri)

EA = [Ri ] + X

Basewithindex

(Ri ,Rj )

EA = [Ri ] + [Rj ]

Basewithindex
andoffset

X(Ri,Rj )

EA = [Ri ] + [Rj ] + X

Relative

X(PC)

EA = [PC] + X

(Ri )+

EA = [Ri ] ;
Incremen
t Ri

(Ri )

Decremen
t Ri ;
EA = [Ri]

Autoincremen
t
Autodecrement

Indexing and Arrays

Index mode the effective address of the operand is

generated by adding a constant value to the
contents of a register.
Index register
X(Ri): EA = X + [Ri]
The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
If X is shorter than a word, sign-extension is needed.

Indexing and Arrays

In

general, the Index mode facilitates access

to an operand whose location is defined
relative to a reference point within the data
structure in which the operand appears.
Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]

Relative Addressing

Relative mode the effective address is determined

by the Index mode using the program counter in
place of the general-purpose register.
X(PC) note that X is a signed number
Branch>0
LOOP
This location is computed by specifying it as an
offset from the current value of PC.
Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.

Additional Modes

Autoincrement mode the effective address of the operand is the

contents of a register specified in the instruction. After accessing
the operand, the contents of this register are automatically
incremented to point to the next item in a list.
(Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
Autodecrement mode: -(Ri) decrement first

LOOP

Move
Move
Clear
Add
Decrement
Branch>0
Move

N,R1
#NUM1,R2
R0
(R2)+,R0
R1
LOOP
R0,SUM

Initialization

Figure2.16.TheAutoincrementaddressingmodeusedintheprogramofFigure2.12.

Assembly
Language

Types of Instructions
Data

Transfer Instructions
Name Mnemonic
Load
LD
Store
ST
Move
MOV
Exchange
XCH
Input
IN
Output
OUT
Push
PUSH
Pop
POP

Data value is
not modified

Data Transfer Instructions

Mode

Assembly

Register Transfer

Direct address

LD ADR

AC M[ADR]

Indirect address

LD @ADR

AC M[M[ADR]]

Relative address

LD $ADR

AC M[PC+ADR]

Immediate operand

LD #NBR

AC NBR

Index addressing

LD ADR(X)

AC M[ADR+XR]

Register

LD R1

AC R1

Register indirect

LD (R1)

AC M[R1]

Autoincrement

LD (R1)+

AC M[R1], R1 R1+1

Data Manipulation Instructions

Arithmetic

Name
Mnemonic
Increment
INC
Logical & Bit Manipulation
Decrement
DEC
Add
ADD
Shift
Subtract
SUB
Multiply
MUL
Divide
DIV
Add with carry
ADDC
Name
Mnemonic
Subtract with borrow SUBB
Clear
CLR
Complement
COM
Name Negate MnemonicNEG
AND
AND
Logical shift right
SHR
OR
OR
Logical shift left
SHL
Exclusive-OR
XOR
Arithmetic shift right
SHRA
Clear carry
CLRC
Arithmetic shift left
SHLA
Set carry
SETC
Rotate right
ROR
Complement
Rotate left
ROL
COMC
carry
Rotate right through
RORC
Enable interrupt
EI
carry

Program Control Instructions

Name

Mnemonic

Branch

BR

Jump

JMP

Skip

SKP

Call

CALL

Return

RET

Compare
(Subtract)

CMP

Test (AND)

TST

Subtract A B but
dont store the result

10110001
00001000
Mask
00000000

Conditional Branch
Instructions
Mnemonic Branch Condition Tested Condition
BZ
Branch if zero
Z=1
BNZ
Branch if not zero
Z=0
BC
Branch if carry
C=1
BNC
Branch if no carry
C=0
BP
Branch if plus
S=0
BM
Branch if minus
S=1
BV
Branch if overflow
V=1
Branch if no
BNV
V=0
overflow

Basic
Input/Output
Operations

I/O
The

data on which the instructions operate

are not necessarily already stored in memory.
Data need to be transferred between
processor and outside world (disk, keyboard,
etc.)
I/O operations are essential, the way they are
performed can have a significant effect on the
performance of the computer.

Program-Controlled I/O
Example
Read

in character input from a keyboard and

produce character output on a display screen.

Rate of data transfer (keyboard, display, processor)

Difference in speed between processor and I/O device
creates the need for mechanisms to synchronize the
transfer of data.
A solution: on output, the processor sends the first
character and then waits for a signal from the display that
the character has been received. It then sends the
second character. Input is sent from the keyboard in a
similar way.

Program-Controlled I/O
Example
Bus

Processor

DATAIN

SIN

- Registers
- Flags
- Device interface

Keyboard

DATAOUT

SOUT
Display

Figure2.19 Busconnectionforprocessor,keyboard,anddisplay.

Program-Controlled I/O
Example
Machine

instructions that can check the state

of the status flags and transfer data:
READWAIT Branch to READWAIT if SIN = 0
Input from DATAIN to R1
WRITEWAIT Branch to WRITEWAIT if SOUT = 0
Output from R1 to DATAOUT

Program-Controlled I/O
Example
Memory-Mapped

I/O some memory

address values are used to refer to peripheral
device buffer registers. No special
instructions are needed. Also use device
status registers.
READWAIT Testbit #3, INSTATUS
Branch=0 READWAIT
MoveByte DATAIN, R1

Program-Controlled I/O
Example
Assumption

the initial state of SIN is 0 and the

initial state of SOUT is 1.
Any drawback of this mechanism in terms of
efficiency?

Two wait loopsprocessor execution time is wasted

Alternate

Interrupt

solution?

Stacks

Home Work
For

each Addressing modes mentioned

before, state one example for each
addressing mode stating the specific benefit
for using such addressing mode for such an
application.

Stack Organization
LIFO

Last In First Out

Current
Top of Stack
TOS

SP
FULL

EMPTY

Stack Bottom

0
1
2
3
4
5
6
7
8
9
10

0
0
0
0
0

1
0
0
0
0

2
5
0
2
1

3
5
8
5
5

Stack

Stack Organization
Current
Top of Stack
TOS

PUSH

SP SP 1
M[SP] DR
If (SP = 0) then (FULL 1)
EMPTY 0
SP
FULL

EMPTY

Stack Bottom

1 6 9 0
0
1
2
3
4
5
6
7
8
9
10

1
0
0
0
0
0

6
1
0
0
0
0

9
2
5
0
2
1

0
3
5
8
5
5

Stack

Stack Organization
Current
Top of Stack
TOS

POP

DR M[SP]
SP SP + 1
If (SP = 11) then (EMPTY 1)
FULL 0
SP
FULL

EMPTY

Stack Bottom

0
1
2
3
4
5
6
7
8
9
10

1
0
0
0
0
0

6
1
0
0
0
0

9
2
5
0
2
1

0
3
5
8
5
5

Stack

Stack Organization
Memory

Stack

PUSH

PC

0
1
2

AR

100
101
102

SP SP 1
M[SP] DR

POP

DR M[SP]
SP SP + 1
SP

200
201
202

Reverse Polish Notation

Infix

Notation

A+B
Prefix

or Polish Notation

+AB
Postfix

or Reverse Polish Notation (RPN)

AB+
(2) (4) (3) (3) +
AB+CD

RPN

ABCD+

(8) (3) (3) +

(8) (9) +
17

Reverse Polish Notation

Example

(A + B) [C (D + E) + F]
(A B +) (D E +) C F +

Reverse Polish Notation

Stack

Operation

(3) (4) (5) (6) +

PUSH

PUSH

MULT

PUSH

30
4
5

PUSH

3
42
12

MULT
ADD

Additional
Instructions

SHIFT & ROTATE INSTRUCTION

There are many applications that require bits of an operand to be shifted right or left.
The details of how the shifts are performed depends on operand.
For general operands

We use logical shift

For numbers
We use arithmetic shift.

Two logical shift operations are needed

Shifting left (LshiftL)
Shifting right (LshiftR)
These instruction shift an operand over a number of bit position specification on a count operand contained in the instruction.
LshiftL count, dst
The count operand may be given as an immediate operand or processor register.
The shift position filled with zeros.
LshiftL #2, R0

Logical Shifts

Logical shift shifting left (LShiftL) and shifting right

(LShiftR)
C

R0

. . .

before:

after:

. .

(a)Logicalshiftleft

LShiftL#2,R0

R0

before:

. .

after:

. . .

(b)Logicalshiftright

LShiftR#2,R0

Arithmetic Shifts

R0

before:

. . .

after:

(c)Arithmeticshiftright

. .

AShiftR#2,R0

Rotate Shifts

In the shift operations, the bits shifted out of the

operand are lost, except for the last bit shifted out
which is retained in the carry flag C.
To preserve all bits, a set of rotate instruction can be
used.
They move the bits that are shifted out of one end of
the operand back in to the other end.
Two type of left and right rotate instruction.
In one version, the bits of the operand are simply
rotated and another include the C flag.

Rotate

R0
0

. . .

before:

after:

. . .

(a)Rotateleftwithoutcarr
y

RotateL#2,R0

R0
0

. . .

before:

after:

. . .

(b)Rotateleftwithcarr
y

RotateLC#2,R0

R0

before:

. . .

after:

. . .

(c)Rotaterightwithoutcarry

RotateR#2,R0

R0

before:

. . .

after:

(d)Rotaterightwithcarry

. . .

RotateRC#2,R0

Figure2.32.Rotateinstructions.

Multiplication and Division

Not

very popular (especially division)

Multiply Ri, Rj
Rj [Ri] [Rj]
2n-bit

product case: high-order half in R(j+1)

Divide Ri, Rj
Rj [Ri] / [Rj]
Quotient is in Rj, remainder may be placed in R(j+1)

Encoding of
Machine
Instructions

Encoding of Machine
Instructions

Assembly language program needs to be converted into machine

instructions. (ADD = 0100 in ARM instruction set)
In the previous section, an assumption was made that all
instructions are one word in length.
OP code: the type of operation to be performed and the type of
operands used may be specified using an encoded binary pattern
Suppose 32-bit word length, 8-bit OP code (how many instructions
can we have?), 16 registers in total (how many bits?), 3-bit
addressing mode indicator.
8
7
7
10
Add R1, R2
Move 24(R0), R5
OPcode
Source
Dest
Otherinfo
LshiftR #2, R0
Move #$3A, R1
(a)Onewordinstruction
Branch>0 LOOP

Encoding of Machine
Instructions

What happens if we want to specify a memory

operand using the Absolute addressing mode?
Move R2, LOC
14-bit for LOC insufficient
Solution use two words
OPcode

Source

Dest

Otherinfo

Memoryaddress/Immediateoperand
(b)Twowordinstruction

Encoding of Machine
Instructions

Then what if an instruction in which two operands

can be specified using the Absolute addressing
mode?
Move LOC1, LOC2
Solution use two additional words
This approach results in instructions of variable
length. Complex instructions can be implemented,
closely resembling operations in high-level
programming languages Complex Instruction Set
Computer (CISC)

Encoding of Machine
Instructions

If we insist that all instructions must fit into a single

32-bit word, it is not possible to provide a 32-bit
address or a 32-bit immediate operand within the
instruction.
It is still possible to define a highly functional
instruction set, which makes extensive use of the
processor registers.
Add R1, R2 ----- yes
Add LOC, R2 ----- no
Add (R3), R2 ----- yes

SUBROUTINES

It is often necessary to perform a particular subtask many times on

different data values, called subroutines.
Calling Program, Call Program
The way in which computer makes it possible to call and return from
subroutines is referred to as its subroutine linkage.
The simplest subroutine linkage method is to save the return address
in a specific location, which may be a register dedicated to this
function, such a register is called Link register.
The call instruction perform the following operations:
Store the contents of the PC in the link Register.
Branch to the target address specified by the instruction.
The return Branch perform following:
Branch to the address contained in the link register.

Memory
Location

200

204

Calling Program
.
.
Call SUB
Next instruction
.

Memory Location

1000

SUB

first ins

Return