Silicon Photonics

Dries Van Thourhout ACP 2010 - Tutorial

Presentation will be available from http://photonics.intec.ugent.be/download

Photonics Research Group

http://photonics.intec.ugent.be

Silicon Photonics
Dries Van Thourhout OFC 2010 - Tutorial Fiber matched Intermediate Strip waveguide

H ~ 10um H ~ 3um
Si Si Si

H ~ 200nm

BOx

BOx

BOx

Photonics Research Group

http://photonics.intec.ugent.be

Silicon Photonics
Dries Van Thourhout OFC 2010 - Tutorial Fiber matched Intermediate Strip waveguide

H ~ 10um H ~ 3um
Si Si Si

H ~ 200nm

BOx

BOx

BOx

Photonics Research Group

http://photonics.intec.ugent.be

Disclaimer
This is a tutorial

Experts in the field are welcome but not intended public Not covering advanced topics

Photonic crystals Plasmonics

Material available:

References in green: available from www.photonics.intec.ugent.be

References in blue: available from literature Complete presentation: will be available from http://photonics.intec.ugent.be/download

Bogaerts e.a. , JSTQE 16, 3344 (2010) Gnan e.a., Electronic Lett. 44, p115 (2008)

Strip waveguide

Si

H ~ 200nm

Why Silicon ?

BOx

Silicon is transparent in telecom range Processing using very large existing equipment base !!! High index contrast compact circuits

But others also have sufficient contrast (e.g. SiN, HfO ) High thermo-optic effect Carrier plasma effect Integration with Germanium, III-V
http://photonics.intec.ugent.be

Active functionality possible

Photonics Research Group

Strip waveguide

Si

H ~ 200nm

Why strip waveguide ?

BOx

Very compact circuits Processing more compatible with electronics processing Active functionality enhanced

Increased light-material interaction Faster devices Lower power consumption Higher non-linear effects
http://photonics.intec.ugent.be

Photonics Research Group

Strip waveguide

Si

H ~ 200nm

What do we need?

BOx

low loss bend complex filters

sources switches modulators

Passives
coupling

Actives
detectors

all functions with electronics

Integration
Photonics Research Group

applications

http://photonics.intec.ugent.be

Outline
low loss bend complex filters sources switches modulators

Passives
coupling

Actives
detectors

all functions with electronics

Integration
applications

Photonics Research Group

http://photonics.intec.ugent.be

Outline
low loss bend complex filters sources switches modulators

Passives
coupling

Actives
detectors

all functions with electronics

Integration
applications

Photonics Research Group

http://photonics.intec.ugent.be

Straight waveguide
Our standard waveguide: 450nm x 220nm Si

Fabricated using 193nm DUV lithography

In standard pilot line, on 200mm wafer Starting from SOI or amorphous silicon 1.84dB/cm Si

SiO2
[2um box]

Bogaerts e.a. , JSTQE 16, 33-44 (2010)

Straight waveguide
Origin of losses ?

Surface roughness Surface absorption

Gnan e.a., Electronic Lett. 44, p115 (2008)

How to decrease losses further ?

eBEAM lithography + HSQ resist 0.9dB/cm Surface treatment

Wet or dry oxidation

Hydrogen or other treatment

Encapsulation

Borselli, Painter, e.a., APL 91, 131117 (2007)

Straight waveguide
Origin of losses

Surface roughness Surface absorption

Gnan e.a., Electronic Lett. 44, p115 (2008)

How to decrease losses further ?

eBEAM lithography + HSQ resist 0.9dB/cm Surface treatment

Wet or dry oxidation

Hydrogen or other treatment

Encapsulation Locally multimode waveguide 0.3dB/cm Include single mode filters
(narrow sections or bends)

Borselli, Painter, e.a., APL 91, 131117 (2007)

Use wider waveguide

Spector e.a., IPRNA IThE5 (2004) Toliver e.a. , OFC OWJ4 (2010) Bogaerts e.a , GPF (2010)

Change waveguide shape

Popovic, PhD Thesis, MIT (2008)

Optimize confinement at interface

Straight waveguide
Question:

Given certain optimization criteria What is optimal aspect ratio for waveguide ?

Single mode size TE Aspect ratio [%] Height [um]

Popovic e.a. :

Optimisation for:

Low loss, Low sensitivity to dimensional variations High thermal optic effect

Choose AR = 6:1 !!!

Standard

Alternative optimisation criteria:

High non-linear effects

Vaillitis, Leuthold, e.a. OE 17 pp. 17357 (2009)

Width [um]
Popovic, PhD Thesis, MIT (2008) (http://dspace.mit.edu)

Optimized sensing (overlap with outside world)

Debackere, PhD thesis UGent (2010)

Dispersion

Bend waveguide
Our standard waveguide: 450nm x 220nm Si

Fabricated using 193nm DUV lithography In standard pilot line, on 200mm wafer Starting from SOI or amorphous silicon

Si SiO2

- In agreement with FDTD calculations - Offset straigth-bend might improve (?)

0.02dB/900

S.K. Selvaraja, JLT 27, p.4070 (2009) Y. A. Vlasov and S. J. McNab, Optics Express, p. 1622 (2004)

The waveguide bend

FDTD calulcations in line with recent experimental results Bends may introduce unwanted polarization rotation

Dots: experimental results (outdated) Lines: FDTD calculations (dash: TE, dotted: TM)

A. Sakai, JLT 22, pp 520 (2004)

15

Crossings
Standard Crossing
>1dB excess loss

<70dB crosstalk

~0.2dB excess loss

>-10dB crosstalk

Not practical ! Improved version

Bogaerts e.a. , JSTQE 16, 33-44 (2010)

The Y-junction
Large losses for standard Y-junction Need improved design !!! Example

Simulation: <0.1dB excess loss

Sakai e.a., IEICE Trans E85-C 1033 (2002)

Experiment: 0.3dB excess loss

Some imbalance due to opt. Prox.

Fukazawa e.a. Jpn JAP 41, p L1461 (2002)

The Y-junction
Use Y-junctions to fabricate TO-switches

4 x 4 switch

Yamada e.a., PIERS proc., Beijing, p. 22 (2009)

18

Passive guiding structures

Standard MMI splitter Improved version

0.3dB excess loss

0.2dB excess loss

Bogaerts e.a. , JSTQE 16, 33-44 (2010)

Arrayed waveguide grating routers

Original devices
200m

Compact, but

High loss (8dB) High crosstalk (only 7dB down)

1540 1560 1580 1600

Wavelength [nm]
1500 -5 1520

Transmission [dB]

-10

-15

-20

-25
Dumon e.a. , GFP 2004

Arrayed Waveguide Grating

8-channel, 400GHz FSR = 30nm footprint = 200 x 350 m2

Improved devices
0 -5 -10

-25 dB crosstalk level -1 dB insertion loss (center channel) 1.5 dB non-uniformity

-15 -20 -25 -30 -35 -40 1545

1550

1555

1560

1565

1570

1575

1580

Arrayed Waveguide Grating

8-channel, 400GHz FSR = 30nm footprint = 200 x 350 m2

0 -5 -10

-25 dB crosstalk level -1 dB insertion loss (center channel) 1.5 dB non-uniformity

-15 -20 -25 -30 -35 -40 1545

Decrease phase errors

Use wider waveguides

Align1550 1555 1560to 1565 waveguides grid See also:

1570

1575

1580

P. Dumon, PhD thesis UGent 2007 (http://photonics.intec.ugent.be)

Use of shallowly etched waveguides for crosstalk reduction

DJ Kim e.a. PTL 20 (17-20) p 1615 (2008)

23

Arrayed Waveguide Grating

Example: 320GB/s receiver

Fang e.a., OE 18 pp. 5106 (2010)

Silicon AWG for wavelength selective operations

Channels spacing globally fixed Low loss (1dB) 1 x N and N x N operation with same device Crosstalk > 25dB difficult to obtain Small channel spacings (<=100GHz) difficult

Reproducibility
18 identical AWGs

-30

-35

shift in channel peak ~ 2.5nm

-40 strong correlation with location of the AWG on chip -45

Possible causes

center-to-edge on wafer lithography scanning mask fabrication mask loading

-50

wafer

-55 1560

1562

1564

1566

1568

6mm

Fabrication uniformity
Measurements: IR Camera setup
screen Infrared Camera

Collimated IR beam from tunable laser

6mm

Camera view
1588nm 1587nm 1586nm 1585nm 1584nm 1583nm 1582nm 1581nm 1580nm 1579nm 1578nm 1577nm 1576nm 1575nm 1574nm 1573nm 1572nm 1571nm 1570nm 1569nm 1568nm 1567nm 1566nm 1565nm 1564nm 1563nm 1562nm 1561nm 1560nm

Measurements
All rows
wavl

all channel positions

1585 1580 1575 1570 1565 1560 0

10

20

30

device#

Challenges: sensitivity
Fabrication:

Sensitivity to fabrication errors

Depends on waveguide shape

Roughly: 1nm variation in line width / thickness

1nm variation in central wavelength of device

Device uniformity
Influence of fabrication technology
248nm deep UV
-10 -15
-50 -40

MZI - 1 MZI - 2 MZI - 3 MZI - 4

193nm deep UV

Transmission [dBm]

-20 -25 -30 -35 -40

-80

MZI11 MZI21 MZI12 MZI22 MZI13 MZI23

Transmission [dB]

-60

-70

-45 -50 1520 1530 1540 1550 1560 1570 1580

-90 1520

1530

1540

1550

1560

1570

1580

1590

1600

Wavelength [nm]

Wavelength [nm]

6 MZIs located 2mm apart

248nm very far of from specs 193nm <2nm variation over die

Wafer Uniformity
Thickness variation over incoming (SOITEC)

wafer
SiO2
[2um box]

Si

4nm variation within wafer 3nm variation wafer-to-wafer (within lot) 4nm lot-to-lot

Lot A
230

Lot B
226

Si thickness [nm]

Si thickness [nm]

228 226 224 222 220 218 216 8 4 0 0 2 4 6 8 10 12

Within wafer mean Within wafer stad. deviation

224 222 220 218 216 214 212 210 8

Within wafer mean Within wafer stad. deviation

3 [nm]

3 [nm]
14 16 18 20 22 24

4 0 0 2 4 6 8 10 12 14 16 18 20 22 24

# Wafer

# Wafer

(circular within wafer pattern determined by CMP process)

Wafer Uniformity
Si

Linewidth variations

Measured using top-down SEM

w
SiO2
[2um box]

Following 193nm DUV lithography

Following etching

Variations in linewidth over 200mm wafer

Less than 1% line width variation over 200mm wafer Much better than typical CMOS specs 1% is still 5nm !! Pure passive, further post processing may increase problem (e.g. stress ) SEM not accurate enough to characterize within die uniformity !!

Mean Range

: 451nm : 2nm : 5nm

Mean Range

: 470nm : 2.6nm : 7.5nm

(No particular pattern)

(Donut shape related to plasma etch)

Manufacturability
Proposed solution

Planar Concave Gratings

Diffraction grating in slab waveguide

deeply etched teeth

free propagation region

1 m

shallow-etch apertures

500 nm wide photonic wires

50 m
J. Brouckaert et al. JLT 25(5), p1269 (2007)

Planar concave gratings

Why PCG in nanophotonic silicon ?

(Hopefully) Less sensitive to phase errors

PCG: transmission in slab AWG: transmission in waveguides

Horst, OFC 2010, OWJ3

Properties less sensitive to process variations Compared to other material systems:

No deep etch required

Coupling loss due to angle

angle

Less sensitive to side wall

angle

Si waveguide has high NA !!

Core height [um]

Grating Demultiplexer
Channel spacing: Insertion loss: Channel uniformity: Crosstalk: Footprint: 20nm 7.5dB 0.6dB better than -30dB 250 x 150 m2

0 -5 -10

R~30%
1 m

Transmisson (dB)

-15 -20 -25 -30 -35 -40 -45 1500

1520

1540

1560

1580

Wavelength (nm) J. Brouckaert et al. JLT 25(5), p1269 (2007)

Grating Demultiplexer
High Fresnel reflection loss at grating ?

Use metal coating Use DBR mirror Use TIR mirror

TIR-mirror

DBR-mirror

J. Brouckaert et al. PTL 20(4), p309 (2008)

Horst e.a., PTL 21, pp 1743 (2009) See also: Horst, OFC 2010, OWJ3 (invited)

Ring resonators

1 0.9

Normalized transmission

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1564.5

fit: Q = 15600500

R=1.5um Q=9000
1565 1565.5 1566

Wavelength [nm]

Bogaerts e.a. , JSTQE 16, 33-44 (2010)

Xu e.a. , OE 16, pp 4309 (2008)

Ring resonators for sensing

0.6 0.5 wavelength shift [nm] 0.4 0.3 0.2 HSA - HSA 0.1 BSA receptor 0 0 -0.1 Devos e.a., IEEE Photonics Journal, 1(4), p.225-235 (2009) 20 40 60 time [min] 80 no receptor 100 120 HuIgG - HuIgG Serum with anti-HuIgG
Serum with anti-HSA

Ring resonator based devices

For applications in data- and telecom Need multi-ring devices with tailored pass band
Layout and channel transfer Response of 8-channel device

Switching 40Gb/s signal using probe

Vlasov e.a., Nat Phot 2 pp. 242 (2008)

Ring resonators
Ring resonators for label extractor

EU-project BOOM Need 0.1nm bandwidth filter Use silicon ring resonator ??
Label extractor Wavelength conversion

Tuning current

Tunable laser

TE-Microring meeting BOOM specs? NO

R = 20um, gap = 400nm

Ring resonators conclusion

TE ring resonators

Very sensitive to random back scattering Behaviour very unpredictable High losses

TM ring resonators ?

TM-Microring meeting BOOM specs? YES !

R = 20um, gap = 1um

Ring resonators conclusion

TE ring resonators

Very sensitive to random back scattering Behaviour very unpredictable High losses

TM ring resonators

Lower confinement at side walls Lower loss, lower back scattering

Record high Q values demonstrated (Qi=340.000)

DeHeyn e.a. , submitted to OFC 2011

Higher order devices

Hitless add-drop filter

Popovic e.a. , OFC2008, paper OTuF4

Interleaver

Assymmetric heating of directional coupler for optimizing coupling ratio

Song e.a. , IEEE PTL 20, pp 2165 (2008)

Thermo-optic effect
Silicon strongly temperature dependent

Roughly: 80pm/K

P. Dumon, PhD Thesis UGent (2007) (http://photonics.intec.ugent.be )

Opportunity for tuning & trimming devices

Gnan e.a. , Photonics in Switching 2007, paper TuB3.3

17uW/GHz

~10us switching

Problem for fixed filters: need for athermal devices

Teng e.a. , OE 17 p.14627-14633 (2009)

Amorphous silicon wires

Low-temperature PECVD a-Si:H deposition Low material losses

deep-etch wire (480nm width): 3.54dB/cm shallow rib waveguide: 1.4dB/cm

Fiber - Fiber Transmited power[dBm]

-10

Bulk loss

1.4 + 0.09 dB/cm

-20

-30

Wire loss

3.54 + 0.09 dB/cm

-40

0.0

1.5

3.0

4.5

6.0

Photonic wire length [cm]

Amorphous silicon wires

Amorphous silicon

Shows improved non-linear performance

Lower non-linear absorption Higher non-linear n2

Demonstrated 26dB parametric gain (on-chip)

Results presented at IEEE Photonics Society annual meeting (Denver, 2010)

Fiber chip coupling

We would like

1mm

Low loss Broadband High coupling tolerance No facet reflections Waferscale testability Easy to fabricate

SOI wire

A solution for the polarization problem

Single-mode fiber

Two solutions
Two widely used solutions
Inverted taper
0.4mm

0.2mm

Grating coupler

80nm

polished facet
500 mm

Single mode fiber core

spot size convertor

Comparison
0.4m m 0.2m m

Single mode fiber core

80n m 500 mm

spot size convert or

Loss (best) Loss (in real live) Broadband Misalignment tolerance Facet reflections

<1dB 3dB-7dB > 100nm 1um (1dB) Low

<1dB 3dB-7dB 35nm (1dB) 2.5um (1dB) -20dB

Waferscale testing
Fabrication Robustness Polarization

No
Additional layer Facet critical Facet preparation Need additional structures High performance applications

Yes
Easy to difficult Etch depth control Build in polarization diversity Low cost applications + Testing

Increase effieciency standard coupler ?

Standard coupler (33%)
Mode mismatch
air Si SiO2 box-layer Si-substrate

Loss to substrate

Improvement: add bottom mirror + apodize

90% simulated !

Gratings with bottom mirror

DBR bottom mirror
Poly silicon DBR mirror a-Si waveguides

Gold bottom mirror

Use waferbonding c-Si waveguides

Grating fiber coupler in a-Si:H Buffer Silicon dioxide DBR mirror

Poly Si SiO2 Poly Si

Isolation Silicon dioxide

6.4 %

69% coupling efficiency

Selvaraja et al. CLEO/IQEC 2009

Van Laere et al., JLT 25(1), p.151 (2007)

Overlay gratings
Break top-bottom symmetry
380nm teeth 220nm Si
0.0 -0.5

2m SiO2 silicon substrate 68% coupling efficiency

Insertion loss for 1 coupler [dB]

-1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 1510 1520 1530

1540

1550

1560

1570

Wavelength [nm]

Grating zoo
Focusing grating Metal gratings Polymer wedge for vertical coupling

F. Van Laere, PTL 19, p. 1919 (2006)

Scheerlinck, APL 92 p.031104 (2008)

Schrauwen e.a.Phot. West, 7218, , p.72180B (2009)

Photonic crystal grating for low reflection deep etch

Apodized grating

Liu e.a. , OFC2010, paper OWJ2

Tang e.a. , OFC2010, paper OWJ6

TE/TM interaction
TE-polarization TE-polarization Effective index

Waveguide width [um]

TE/TM interaction
TM-polarization

Effective index

Anticrossings TM-polarization

Solution:
Use SiO2 cover or index matching oil Vermeulen e.a. , ECIO 2010 Waveguide width [um]

Polarization diversity
Process both polarizations separately

split polarizations convert to the same polarization on the chip combine polarization back into the fiber

TE TM TE/TM TM TE/TM
two identical circuits

TE/TM TE

Polarization diversity
Polarization diversity with inverted taper

Need on-chip polarization splitter + rotator

TE TM

TE

Coupling length TM << TE

TE/TM
Watts et al, OL 30(9), p.937 (2005)

Fukuda e.a., OE 14(25), p. 12401 (2006)

Polarization diversity
Polarization diversity with inverted taper

Need on-chip polarization splitter + rotator

Polarization conversion efficiency

Vermeulen e.a. GPF 2010, paper WC6 See also: Wang & Dai, JOSA B, pp. 747-753 (2008)

Polarisation Diversity Circuit

light in y x single-mode fiber

on-chip components are polarisation dependent fiber-to-fiber transmission is polarisation independent

light out

x-polarization

2-D grating split polarisations identical circuits

y-polarization

z
y x

combine polarisations

2-D grating
D. Taillaert, PhD Thesis UGent, 2004

Polarization diversity circuit

See Halir e.a. , OFC 2010, paper OWJ1

What we did not cover in passives

Details of fabrication Special waveguides

S.K. Selvaraja, JLT 27, p.4070 (2009)

Slot waveguides Photonic crystal waveguides Interesting science But also: big headache

Non linearities

And much more

Outline
low loss bend complex filters sources switches modulators

Passives
coupling

Actives
detectors

all functions with electronics

Integration
applications

Photonics Research Group

http://photonics.intec.ugent.be

Outline
low loss bend complex filters sources switches modulators

Passives
coupling

Actives

all functions with electronics

detectors

Integration
applications

Photonics Research Group

http://photonics.intec.ugent.be

Detector
1. Hybrid integration

Prefabricated diode, E.g. flip-chip on top of grating coupler Cost effective for low density, medium speed

Detector
1. Hybrid integration 2. Heterogeneous integration through waferbonding

See next section Example: 33GHZ, 0.45A/W

Binetti e.a., EU PICMOS project

Detector
1. Hybrid integration 2. Heterogeneous integration through waferbonding 3. Implanted silicon, silicides

Low efficiency + slow Easy to process Useful monitor

Kotura, OFC2010, Monday

Detector
1. Hybrid integration 2. Heterogeneous integration through waferbonding 3. Implanted silicon, silicides 4. Germanium

Efficient absorber up to 1600nm Large lattice mismatch (~4%). How to integrate ?

Buffer layer ? Requires 1-10um Two step growth process Rapid melt growth

: Too thick !!

Ge-epitaxy
Two-step growth process:

Direct growth of Ge on Si at low temperature ( ~350) CVD

Thin (a few 10nm) highly-dislocated Ge layer High quality Ge absorbing layer

Growth of thick Ge layer (few 100nm) at high temperature (~600)

Thermal annealing to reduce the dislocation density

Using MBE, UHV-CVD, RP-CVD

HT Ge (~600C, 300-500nm) LT Ge (~350C, ~50nm) Si

BOx

Ge-epitaxy
Two-step growth process:

Direct growth of Ge on Si at low temperature ( ~350) CVD

Thin (a few 10nm) highly-dislocated Ge layer High quality Ge absorbing layer

Growth of thick Ge layer (few 100nm) at high temperature (~600)

Thermal annealing to reduce the dislocation density

Using MBE, UHV-CVD, RP-CVD

Different integration approaches:

Butt Coupling Evanescent Coupling Two level

Si

Si

Si

BOx

BOx

BOx

Ge-detector
Two step growth butt coupling

Vivien e.a. , OE 17, pp. 6252 (2009)

Ge-detector
Rapid melt growth
1. Ge CVD deposition on SiON mask with small opening 2. Encapsulation 3. RTA induces melt + recristallisation to single crystal

Assefa e.a. , OE 18, pp4997 (2010) Assefa e.a. , Nature (2010)

Ge-detector
Rapid melt growth: results

40GB/s operation as PD APD operation with

Assefa e.a. , OE 18, pp4997 (2010) Assefa e.a. , Nature (2010)

10dB gain at low bias !! >30GHz bandwidth

Detector state-of-the-art

Table compiled by L. Vivien e.a. (IEF) for EU HELIOS project Extracted from D003 Silicon Photonics State-of-the-Art, public deliverable (http://www.helios-project.eu/)

Outline
low loss bend complex filters sources

Passives
coupling

modulators
Actives
detectors all functions

switches

with electronics

Integration
applications

Photonics Research Group

http://photonics.intec.ugent.be

Modulation of light
How to make a modulator in silicon

Silicon has no intrinsic EO-effect

But:

Free carriers induce absorption And index modulation

Soref , JQE 23, (1987).

Plasma dispersion effect

Empiric relations determined

(in silicon at 1550nm carrier densities in cm-3)

Change carrier densities by

Doping Injection/extraction of carriers

Injection vs. depletion

Carrier injection

p-i-n diode in forward bias Inject carriers into waveguides Strong effect (many carriers) Slow effect (~1GHz) p n

Carrier depletion

p-n diode in reverse bias Extract carriers from waveguide Weaker effect Fast effect (>40GHz)

Carrier accumulation

Accumulation at oxide Similar to capacitor Fast

n p

Injection Modulator
100-200m length p-i-n diode MZI configuration

W. Green, OpEx 15, p17106 (2007)

Ring Modulator
Speed ~2GB/s With preemphasis: >20GB/s

Q. Xu et al, nature 435(19), p03569 (2005)

Example: depletion modulator

Complex multi-doping profile

Larger index change Lower RC

But

Still a long device (4mm) Requires travelling wave electrodes

signal

phase shifter

4mm long mach zehnder

D. Marris-Morini, OpEx 16 (2008)

Ring modulator
Ring resonator in p-i-n junction

Carrier injection Change refractive index Change resonance

operating
Ground ground CW light in Bus Waveguide High-speed electrical signal

signal

Ground ground

Ring Waveguide

High-speed modulation region waveguide in p-i-n (pn diode)

C. Gunn, IEEE Micro, 2006

SiGe electroabsorption modulator

Operation at 1550nm Compact: 30m But: one operation point.

Liu, Nature Photonics 2, p.433 (2008)

Outline
low loss bend complex filters

sources
switches modulators

Passives
coupling

Actives
detectors

all functions with electronics

Integration
applications

Photonics Research Group

http://photonics.intec.ugent.be

Sources on Silicon
1. Hybrid integration

Song e.a. OE 17, 14063-14068 (2009).

Sources on Silicon
1. Hybrid integration

2. Monolithic integration
Strained Ge-laser Er-doped Si nanocrystals III-V on silicon epitaxy

Zhizhong, Y. et al. Proc of the IEEE 97, 1250 (2009).

Junesand e.a., IPRM 2009 pp59

MIT press release

Sources on Silicon
1. Hybrid integration

2. Monolithic integration
3. Integration through waferbonding techniques
SOI-wafer Planarization Bonding

(a)

(b)

(c)

Substrate Removal

Pattern definition

III-V processing

(d)

(e)

(f)

III-V/Silicon photonics
Bonding of III-V epitaxial layers

Molecular die-to-wafer bonding, direct bonding

Based on van der Waals attraction between wafer surfaces Requires atomic contact between both surfaces - very sensitive to particles - very sensitive to roughness - very sensitive to contamination of surfaces

Adhesive die-to-wafer bonding

Uses an adhesive layer as a glue to stick both surfaces Requirements are more relaxed compared to Molecular - glue compensates for particles (some) - glue compensates for roughness (all) - glue allows (some) contamination of surfaces

Bonding Technology
Cross-sectional image of III-V/Silicon substrate
InP/InGaAsP epitaxial layer stack InP-InGaAsP epitaxial layer stack Si DVS-BCB SiO2 Si DVS-BCB Si WG SiO2

200nm
200nm

200nm bonding layer routinely and reliably obtained Recently : focus on thin

bonding layer develoment (<100nm)

intec 2009 - Photonics Research Group - http://photonics.intec.ugent.be

Business model ?
Option I : all CMOS-fab processing
200mm SOI wafer Bond III-V dies Process in CMOS fab

Need to cover full 200mm wafer (or 300mm ?) Need to adapt processes to CMOS fab

Gold free contacts

III-V etching

intec 2009 - Photonics Research Group - http://photonics.intec.ugent.be

200mm process development

InP processing in CMOS-fab ?

YES !!!

CEA/LETI demonstrated full laser processing in CMOS pilot line

CH4/H2 RIE process in 200mm reactor Gold free contacts demonstrated (AlCu/TiN/Ti)
SiO2 hard mask
2 1 0 -1 -2 -100 -50 0 50 100
112m 56m 28m 14m 7m 3.5m AlCu/TiN/Ti/n-InP Chemistry before deposition Unannealed

InP

Voltage (V)

InGaAs

Current (mA)
L. Grenouillet e.a., CMOS compatible contacts and etching for InP-on-silicon active devices, GFP 2009, San Fransisco

intec 2009 - Photonics Research Group - http://photonics.intec.ugent.be

WP5

FP lasers on silicon
AlGaInAs active layer 1.3m individual die processed
CH4/H2/O2 dry etching metallization + lift off process

pulsed operation:
L = 1mm = 1.3m P >20 mW max T = 40 C

1mm-long stripe, pulsed current, 50ns, 1%

25
15C 20C 25C 30C 35C 40C

20

2007

Power (mW)

15

10

0 0 20 40 60 80 100 120 140 160 180 200

CEA 2009. All rights reserved
Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA

Current (mA)

Confidential

93

Business model ?
Option I : all CMOS-fab processing
200mm SOI wafer

III-V processing in existing fabs

Bond III-V dies

Process in CMOS fab

CMOS compatible III-V processing currently not commercially available ! Only if silicon is cheap !

Considerable loss of silicon real estate

Option II : CMOS-fab + III-V fab processing

Cut to smaller wafers Bond Process in III-V lab

200mm SOI wafer

intec 2009 - Photonics Research Group - http://photonics.intec.ugent.be

Option II: example

InP HBTs on IBM CMOS (HRL Labs)
Collective processing after bonding

IBM 130nm RF-CMOS cut to 3 inch wafers BCB-bonded unprocessed InP dies
Y. Royter e.a. , "Technology for Dense Heterogeneous Integration of InP HBTs and CMOS," in CS Mantech, Tampa, Florida, 2009

intec 2009 - Photonics Research Group - http://photonics.intec.ugent.be

Business model
Die bonding

OR

Wafer bonding...

Edge effects may induce bonding effects Independent of size silicon wafer (200mm, 300mm ) Total required material may be smaller Rapid pick and place process required

Currently more reliable process Largest wafers now available 150mm, 100mm more standard Single step process

CEA-LETI

UCSB-INTEL
intec 2009 - Photonics Research Group - http://photonics.intec.ugent.be

Design options
Light centred in Silicon Light centred in III-V

High overlap with silicon:

High gain Coupling to silicon may require special structures

Allows for modal control Easy coupling to waveguide

Low overlap with III-V : low gain high saturation threshold Not compatible with sub400nm silicon thickness

Hybrid evanescent laser

Hybrid evanescent laser (UCSB/INTEL)
DFB-laser

Also:

DBR-laser, SGDBR-laser, EA-modulator, Detector, Disk laser

Liang, D. et al. Appl Phys a 95, 1045-1057 (2009).

Microdisk laser
2Rdisk top contact active layer InP t tunnel junction ts dox Si waveguide wSi SiO2

Microdisk laser

Si substrate

om contact

Whispering gallery mode Evanescent coupling to silicon 150-350uA threshold 120uW output power (CW)
45 40 35 30 25 20 15 10 5 0 0 1 2 Current [mA] 3 4 2.5 2 1.5 1 0.5 0 -0.5 Voltage [V]

-10 -20 -30 -40 -50 -60 -70 -80 1544 1564 1584 1604 1624 Fiber coupled output power [uW] Wavelength [nm] Spectral power [dBm]

Spuesens e.a. ,GPF2009c

Microdisk device
Very flexible device

Direct modulation Multi-wavelength source

20GHz All-optical wavelength conversion 10GHz All-optical gate Electro-optic modulation All-optical switching All-optical flip-flop

Raz e.a. ,OFC2010, paper OMQ5

Kumar e.a. ,OFC2010, paper JWA44 Liu e.a. , Optics Letters, 33(21), p.2518 (2008)

Liu e.a. , Nat. Phot 2010 + Kumar e.a. , OFC2010, Tuesday

Whats next ?
WDM optical intraconnections on chip with a fully CMOS compatible process (EU WADIMOS project http://wadimos.intec.ugent.be/)

III-V disk heaters

2007

filters III-V photodetector waveguides

Now lasing !!!!!

Group Four Photonics Conference, FA1

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September, 11th, 2009

102

Outline

low loss bend complex filters

sources switches modulators

Passives
coupling

Actives
detectors

all functions with electronics

Integration
applications

Photonics Research Group

http://photonics.intec.ugent.be

Monolithic vs. 3-D integration

Front-end: no thermal budget Integrated in CMOS flow (on SOI only) High process development cost Compound yield Little flexibility Optical layer buried

Back-end: thermal budget < 400C

3-D: on top of CMOS No thermal budget

On top of CMOS (or in metal layers) Parallel process No compound yield Serial process problem with die-to- wafer Compound yield stacking (known good die)

Optical on top is possible

Flexible choice of electronics and photonics Other layers possible: MEMS, antennas Optical layer on top is possible

Monolithic vs. 3-D integration

Luxtera

EPIC project

Front-end: no thermal budget Integrated in CMOS flow (on SOI only) High process development cost Compound yield Little flexibility Optical layer buried
Beals e.a., SPIE Phot West 2008

MIT

Batten, C. et al. in IEEE Symp. on HP Interconnects 21-30Stanford, CA, USA; 2008).

Monolithic vs. 3-D integration

IBM

CEA-Leti

3-D: on top of CMOS No thermal budget Parallel process No compound yield problem with die-to- wafer stacking (known good die) Flexible choice of electronics and photonics Other layers possible: MEMS, antennas Optical layer on top is possible

IMEC

Top chip

Cu nail

Bottom chip

Cu pad

low loss bend complex filters

sources switches modulators

Passives Actives Building blocs available !!! coupling

all functions

detectors

Time to integrate and find the right application with electronics Integration
applications

Photonics Research Group

http://photonics.intec.ugent.be

ePIXfab
Silicon photonics in CMOS fab

Cheap for volume production Expensive and difficult access for research and prototyping

Solution ? ePIXfab

Multi-project wafer shuttles allow cost sharing Joint initiative of IMEC and LETI Supported by EU-commission Open for research and prototyping

ePIXfab: serving the research community

send in design users
mask integration fabrication

www.epixfab.eu

wafers distributed

Supported by PhotonFAB

ePIXfab: Practical information

Visit our web site: www.epixfab.eu or www.siliconphotonics.eu

Information on calls Technical docs

Coordinator:
Pieter Dumon [email protected]

Acknowledgements
Thanks to

Ghent University/IMEC Photonics Research Group

(in particular Wim Bogaerts who provided a lot of the slides)

ePIXfab project for silicon fabrication

See www.epixfab.eu : also for YOU!!!

Funding through national and EU research projects