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DSP Architecture for EEE Students

The document discusses the architecture of the TMS320C54x digital signal processor. It describes the CPU registers including the status register 1 and processor mode status register. It also details the ALU, barrel shifter, MAC unit, compare select and store unit, and exponent encoder components of the processor architecture.

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100% found this document useful (1 vote)
129 views27 pages

DSP Architecture for EEE Students

The document discusses the architecture of the TMS320C54x digital signal processor. It describes the CPU registers including the status register 1 and processor mode status register. It also details the ALU, barrel shifter, MAC unit, compare select and store unit, and exponent encoder components of the processor architecture.

Uploaded by

vipulugale
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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EEE C415:

DIGITAL SIGNAL
PROCESSING

Lecture 08

Architecture of TMS320C54x Cont..


Last Session
• Architecture of TMS 320C54x Processor

24 January 2009 EEE C415 / Shikha Tripathi 2


Today’s Session
• CPU registers : ST1,PMST
• ALU
• Barrel Shifter, MAC units
• Exponent encoder

24 January 2009 EEE C415 / Shikha Tripathi 3


Status Register (ST1)
15 14 13 12 11 10 9 8 7 6 5 4-0
BRAF CPL XF HM INTM 0 OVM SXM C16 FRCT CMPT ASM

• BRAF: Block-Rep active flag


– BRAF=0, when BRC< zero; BRAF=1, when RPTB
• CPL: Compiler mode.
– CPL=0, DP is selected; CPL=1, SP is selected
• XF: External flag, a GP O/P pin for multiprocessor
configuration.
– SSBX; RSBX
• HM: Hold Mode, determines whether the CPU stops or continues
execution when acknowledging an active HOLD signal.
24 January 2009 EEE C415 / Shikha Tripathi 4
Status register 1
15 14 13 12 11 10 9 8 7 6 5 4-0
BRAF CPL XF HM INTM 0 OVM SXM C16 FRCT CMPT ASM

• INTM: Interrupt mode.

0, all unmasked ints are enabled.

1, all maskable ints are enabled.

• OVM: Overflow mode, enables (1) / disables(0) the


accumulator to saturate on overflow.
• SXM: Sign extension mode, enables / disables sign extension
of an arithmetic operation.
24 January 2009 EEE C415 / Shikha Tripathi 5
Status register 1…..
15 14 13 12 11 10 9 8 7 6 5 4-0
BRAF CPL XF HM INTM 0 OVM SXM C16 FRCT CMPT ASM

• C16: Dual 16-bit/ Double precision arithmetic mode.


• FRCT: Fractional mode (multiplication)
– If 1, multiplier output is left shifted by 1 bit to compensate for
extra sign bit
• CMPT: Compatibility mode for ARP.(ARP not updated(0), ARP
updated(1))
• ASM: Accumulator shift mode.
– Specifies a shift value of -16 to +15 range and is coded as 2’s
complement value
24 January 2009 EEE C415 / Shikha Tripathi 6
Processor Mode Status Register
15-7 6 5 4 3 2 1 0

IPTR MP/¯MC OVLY AVIS DROM CLKOFF SMUL* SST*

• IPTR: Interrupt vector pointer. 9-bit =>


128-word program page of IVs.
• MP/MC: enables/disables on-chip ROM to be
addressable in program mem space.
0= enabled & addressable.
1= not available.
• OVLY: RAM overlay, enables on-chip DARAM to be
mapped into program space.
24 January 2009 EEE C415 / Shikha Tripathi 7
Processor Mode Status Register
15-7 6 5 4 3 2 1 0

IPTR MP/¯MC OVLY AVIS DROM CLKOFF SMUL* SST*

• AVIS: Address visibility mode, enables/disables the internal


program addr to be visible at the addr pins.
• DROM: Data ROM, enables on-chip ROM to be mapped into
data space.
• CLKOFF: Clock Out off, disables the output CLKOUT
• SMUL: Saturation on multiplication.
• SST: Saturation on store

24 January 2009 EEE C415 / Shikha Tripathi 8


Barrel Shifter

ALU

MAC Unit
24 January 2009 EEE C415 / Shikha Tripathi CSSU
9
ALU

24 January 2009 EEE C415 / Shikha Tripathi 10


Barrel Shifter
• Used for scaling operations…
– Prescaling an input data memory operand or the Acc value
before an ALU operation
• Performing a logical / arithmetic shift of the Acc.
• Normalizing the Acc?
• Post scaling the Acc before storing the Acc value into data
memory.

24 January 2009 EEE C415 / Shikha Tripathi 11


Barrel Shifter

24 January 2009 EEE C415 / Shikha Tripathi 12


Shifter…

24 January 2009 EEE C415 / Shikha Tripathi 13


Multiply & Add (MAC)Unit

• 17-bit x 17-bit hardware multiplier


• 40-bit adder
• MAC in one pipeline phase cycle.
• Signed / unsigned multiplication.
• Contains a zero detector, a rounder and
overflow / saturation logic.

24 January 2009 EEE C415 / Shikha Tripathi 14


24 January 2009 EEE C415 / Shikha Tripathi 15
24 January 2009 EEE C415 / Shikha Tripathi 16
MAC Unit…

24 January 2009 EEE C415 / Shikha Tripathi 17


Compare Select & Store Unit
• 3 functions:
– Compare, Select and Store in a single cycle.
• Application-specific hardware to add/compare/select
(ACS) operations for viterbi operator.
• Supports various viterbi butterfly algorithms used in
equalizers and channel decoders.
• With ALU performs fast ACS operation

24 January 2009 EEE C415 / Shikha Tripathi 18


CSSU…

24 January 2009 EEE C415 / Shikha Tripathi 19


CSSU…

• Compare & Select operation, CMPS


• Compares 2 16-bit part of the result in ACC and
shifts the decision into bit 0 of TRN.
• This decision is also stored in TC bit of ST0.
• Store it in data memory.

24 January 2009 EEE C415 / Shikha Tripathi 20


Exponent Encoder

24 January 2009 EEE C415 / Shikha Tripathi 21


24 January 2009 EEE C415 / Shikha Tripathi 22
EE…

24 January 2009 EEE C415 / Shikha Tripathi 23


Example
• EXP A
Before: A = FF FFFF FFCB h
contains 33 leading 1’s. (Exclude sign bit)
33 – 8 = 25
Hence after execution:
A = FF FFFF FFCB h & T = 0019 h.

24 January 2009 EEE C415 / Shikha Tripathi 24


Example
• EXP B
Before: B = 07 8600 1234 h
contains 4 leading 0’s exclude sign bit
4 – 8 = -4 => FFFC h (2’S compl)
Hence after execution:
A = 07 8600 1234 h & T = FFFC h.

24 January 2009 EEE C415 / Shikha Tripathi 25


Next Session
• Architecture cont..
• Addressing modes

24 January 2009 EEE C415 / Shikha Tripathi 26


Thank You

24 January 2009 EEE C415 / Shikha Tripathi 27

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