EEE C415:
DIGITAL SIGNAL
PROCESSING
Lecture 07
Architecture of TMS320C54x
Last Session
• DSP Vs GPP
• Some Architectural aspects
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Today’s Session
• Architecture of TMS 320C54x Processor
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Reference:
TMS320C54x manual available with
CCS Simulator
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Architecture of C54x
• Fixed Point processor
• Advanced Harvard Architecture, CISC Processor
– Separate memory bus structures for program & data.
• High degree of parallelism.
– Multiply, load/store, add/sub to/from ACC and new address
generation can be done simultaneously.
• Powerful Instruction set & most of the operations are
of single cycle.
• Targeted for portable devices (cellular phones, MP3
players, digital cameras …)
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Bus structure
• Has several buses:
1. Program Bus (PB): carries instruction codes &
immediate operands from program memory to CPU.
2. Program Address Bus (PAB): provides addresses to
program memory for both read/write operations.
3. Data Bus (DB): carries data between data memory
space and CPU.
4. Data Address Bus (DAB): provides addresses to
access data memory.
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Buses in C54x
• 8 major 16-bit buses.
– 4 program / data buses
• 1 Program bus, PB
• 3 Data buses
• CB & DB for READ
• EB for Write
– 4 address buses
• PAB, CAB, DAB & EAB
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• All CPU registers, peripheral registers and
I/O ports occupy data memory space.
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Buses…
• Can generate upto 2 data-mem addr per cycle
– ARAU0 & ARAU1
• PB can carry data operands stored in program space
to MAC.
• One coeff from program mem
Two data values from data mem using ARAU0 &
ARAU1
Ex: [x(i) + x(N-1-i)] * h(i)
symmetric FIR in single cycle.
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Barrel Shifter
ALU
MAC Unit
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12
Memory organization
• Minimum address range of 192K words
– 64K words for program space
– 64K words for data space
– 64K words for I/O space
• ROM, DARAM, SARAM, two way shared
RAM
• On-chip Memory Security option.
• MMR: 26 CPU Regs and peripheral regs and
scratch pad RAM block located on data page 0.
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Memory mapped Registers
• 96 registers mapped into page 0 of the data
memory space.
– 28 CPU reg
– 16 I/O port regs
– Peripheral & reserved regs
• Register operation == mem operation
ex: AR0 maps to mem 16h in 5x and maps to
10h in 54x.
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CPU
• CPU Registers
• 40-bit ALU
• Two 40-bit Acc Regs (AccA & AccB)
• Barrel Shifter Supporting 0-31 bit left shift
& 0-16 bit right shift range
• MAC Block
• 16-bit Temp Reg (T)
• 16-bit Transition Reg (TRN)
• Compare, Select and Store Unit (CSSU)
• Exponent Encoder
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Accumulators A & B
39-32 31-15 15-0
AG AH AL
Guard bits High-Order Bits Low-Order Bits
39-32 31-15 15-0
BG BH BL
Guard bits High-Order Bits Low-Order Bits
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CPU registers
• IMR, IFR
• ST0 & ST1
• PMST
• AR0 – AR7
• SP reg
• Circular-Buffer size Register (BK)
• Block-Rep Regs (BRC, RSA and REA)
• PC Extension Reg (XPC)
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ST0 register
15 - 13 12 11 10 9 8-0
ARP TC C OVA OVB DP
• DP : Data memory page pointer, concatenated
with the 7-LSBs of an instruction word to form a
direct memory address of 16-bits, if CPL = 0.
• OVB: Overflow for AccB.
• OVA: Overflow for AccA.
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ST0 register Cont..
15 - 13 12 11 10 9 8-0
ARP TC C OVA OVB DP
• C: Carry,
1 for Carry generated by addition.
0 for Borrow generated by subtraction
otherwise,
0 for add & 1 for sub.
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ST0 register cont..
15 - 13 12 11 10 9 8-0
ARP TC C OVA OVB DP
• TC: Test/Control flag,Stores the result of ALU
test bit operations.
• ARP: Auxiliary Register Pointer, Selects AR0 –
AR7 for indirect single-operand addressing.
Set to 0 if CMPT = 0.
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Next Session
• ST1,PMST registers
• ALU
• Barrel Shifter, MAC units
• Exponent encoder
• Addressing Modes
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Thank You
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