B.
Supmonchai
July 5th, 2004
B.Supmonchai
Design Rules
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Interface between the circuit designer and process engineer Guidelines for constructing process masks Rules constructed to ensure that design works even when small fabrication errors (within some tolerance) occur
Tutorial 1
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Design Rules and Layout Techniques
Boonchuay Supmonchai
Integrated Design Application Research ( IDAR ) Laboratory
July 5th, 2004
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Design Rules and Layout Techniques
B.Supmonchai
B.Supmonchai
Why Having Design Rules?
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Design Rule Components
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To be able to tolerate some level of fabrication errors such as
1. Mask misalignment 2. Dust 3. Process parameters (e.g., lateral diffusion) 4. Rough surfaces
A complete set includes
set of layers intra-layer constraints: relations between objects in
the same layer
inter-layer constraints: relations between objects on
different layers
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Unit dimension: minimum line width
scalable design rules: lambda parameter absolute dimensions: micron rules
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Design Rules and Layout Techniques
2102-545 Digital ICs
Design Rules and Layout Techniques
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July 5th, 2004
B.Supmonchai
B.Supmonchai
Layers in CMOS 0.25 m Process
Intra-Layer Design Rule Origins
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Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fabrication
minimum line width is set by the resolution of the
patterning process (photolithography)
Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab.
0.3 micron 0.15 0.15 0.3 micron
Select regions are the diffusions of an invert type to implement contacts to the wells or to the substrate.
2102-545 Digital ICs
Design Rules and Layout Techniques
2102-545 Digital ICs
Design Rules and Layout Techniques
B.Supmonchai
B.Supmonchai
Intra-Layer Design Rules
Same Potential
0 or 6 3 2 2
Inter-Layer Design Rule Origins
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Different Potential
1. Transistor rules transistor formed by the overlap of active and poly layers
Transistors
Catastrophic error
Well
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Polysilicon
2 2
Active
3
Metal1
3
Unrelated Poly & Diffusion
4
Select
2
Contact or Via Hole
Metal2
3
Thinner diffusion, but still working
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2102-545 Digital ICs
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July 5th, 2004
B.Supmonchai
B.Supmonchai
Transistor Rule Example
PMOS devices
Inter-Layer Design Rule Origins II
2. Contact and Via rules
M1 contact to p-diffusion M1 contact to n-diffusion M1 contact to poly Mx contact to My
Contact Mask Via Masks mask misaligned
both materials
0.3
Contact: 0.44 x 0.44
0.14
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B.Supmonchai
B.Supmonchai
Contact and Via Rule Examples
Inter-Layer Design Rule Origins III
3. Well and Substrate Contacts - inadequate number of contacts creates a high resistive path between substrate and supply rails Latchup
VDD p+ n+ n+ p+ n-well Rpsubs p-substrate (a) Origin of latchup p+ n+ Rnwell n-source Rpsubs VDD Rnwell p-source
(b) Equivalent circuit
Overlapping layers are marked by merged colors
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Well Contact and Select Layer Examples
Inverter Layout in 0.25 um Process
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B.Supmonchai
Lambda-Based Design Rule
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MOSIS Scalable Rule Example
One lambda = one half of the minimum mask dimension
Typically the length of a transistor channel.
Usually all edges must be on grid
For example, in the MOSIS scalable rules, all edges
must be on a lambda grid.
See example on the next few slides
More info at: http://www.mosis.org/Technical/Designrules/scmos/cmos-main.html
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Sample Lambda Layout
Sample Sea-of-Gates Layout
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Lambda vs Micron Rules
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Lambda vs Micron Rules II
Lambda-based design rules are based on the assumption that one can scale a design to the appropriate size before manufacture The assumption is that all manufacturing dimensions scale equally
For example: if a design is completed with a poly
width of 2l and a metal width of 3l then minimum width metal will always be 50% wider than minmum width poly wires
It works only over some modest span of time
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Scaled design is legal but much larger than it needs to be!
Data from Weste, Table 3.2
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When Lambda Rules be used?
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Retargetable Layouts
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Probably for retargeting between similar processes, e.g., when later process is a simple shrink of the earlier process.
This often happens between generations as a mid-life
Invent some way of entering a design symbolically but use a more sophisticated technique for producing the masks for a particular process.
Relative sizes may change but topological Instead of shrinking a design, compact it!
rejuvenation for a process.
relationship between components does not.
Can be useful for fabless semiconductor companies
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Most industrial designs use micron rules to get the extra space efficiency.
Cost of retargeting by hand is acceptable for a
More often nowadays, designs are described by HDLs, such as VHDL or Verilog
Re-compiled and mapped to a new technology Best performance functional units are laid by hands -
successful product, but usually its time for a redesign anyway
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difficult to shrinks
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Stick Diagrams and Compaction
Layout Styles
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Avoid long (> 50 squares) Poly runs Do not capture white space in a cell Do not obsess over the layout, instead make a second pass, optimize when it counts
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Optimizing Connections
Big vs. Parallel
Which is the better gate layouts?
Which is the better gate layouts? Considering node capacitances? Considering composibility with the neighboring gates?
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Eleminating Gaps
Replicating Cells
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What does this cell do? What if we want to replicate this cell vertically, i.e., make a stack of cells to process many bits in parallel?
Which nodes are shared
among the cells? shared?
Which nodes are not How should we arrange
the cell vertically?
Use Logic Graphs and the method of Euler path to reorder inputs
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July 5th, 2004
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B.Supmonchai
Vertical Replication
Vertical Intercell Routing
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Building a Datapath
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Rule of Thumbs for Datapath Designs
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It is often the case that we want to operate on many bits in parallel. A sensible way to arrange the layout of this sort of logic is as a datapath where
data signals run
Logic that generates the control signals can be placed at the bottom of the datapath. If control logic is complicated or irregular, it might be placed in a separate standard cell block
Only the control signal buffers can be placed just
horizontally between functional units
control signals run
below the data path
vertically to all the bits of a particular functional unit
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Although it is tempting to run control signals in Poly (so they can control FETs) this is unwise for tall datapaths because of poly resistance
E.g., 32 bits x 20u/bit = 640u = ~1000 sqs. ~ 20 k
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Datapath Bit Pitch
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Example: Adder
Hall tall we make each bit of the datapath depends on
The width of the NMOS and PMOS FETs How much in-cell routing there is How much over the cell global routing there is
Global routes can be determined from datapath schematic:
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Example: Shifter
Think Globally
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B.Supmonchai
Verifying the Layout
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Design Rule Checker (DRC)
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Make sure that all the design rules are not violated Verification of the Layout usually takes a very long time.
Old timers use room-size layout plots. Newbies use computer-aided design tools.
Design Rule Checkers (DRC) Layout vs Schematic (LVS)
A program that checks each piece of the layout against the process design rules
Canonicalize layout into a set of leading and trailing
non-overlapping mask edges. Some boolean mask operations may be needed. edge with the node it belongs to.
Determine electrical connectivity and label each Test each edge end point against neighboring edges
to check for spacing (leading edges) and width (trailing edges) violations.
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Computationally Intensive - A slow process!
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Circuit Extraction
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Layout vs Schmetic (LVS)
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Circuit Extractor derives a circuit schematic from a physical layout
Scan various layers and their interactions. Reconstruct the transistor network, topologically Generate a netlist file which describes all the
First a netlist is extracted from the layout. Use the electrical info generated by the DRC and then recognize which transistors are juxtapositions of channel with diffusion See if extracted netlist is isomorphic to the schematic netlist
Initialize all nodes to the same color Compute a new color for each node as some hashing Worry about parallel FETs, ambiguous nodes
interconnection in the network.
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The netlist file contains precise information on the parasitics
diffusion and wiring capacitances and resistance
function involving the colored node in other network
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