Device Matching Mechanisms

Spatial effects
Wafer-to-wafer Long range
Gradients

Short range
Statistics

Circuit effects
Differential structures
Differential pair Current mirror

Bias

Layout effects
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Mismatch Model
What is modeled?
Short-range, random processes, e.g.
Dopant fluctuations Mobility fluctuations Oxide trap variations

What is NOT modeled?

Batch-to-batch or wafer-to-wafer variations Long-range effects such as gradients Electrical, lithographic, or timing offsets
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References
M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of SolidState Circuits, vol. 24, pp. 1433 - 1439, October 1989.
Mismatch model Statistical data for 2.5m CMOS

Jeroen A. Croon, Maarten Rosmeulen, Stefaan Decoutere, Willy Sansen, Herman E. Maes; An easy-to-use mismatch model for the MOS transistor, IEEE Journal of Solid-State Circuits, vol. 37, pp. 1056 - 1064, August 2002.
0.18m CMOS data Qualitative analysis of short-channel effects on matching
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Mismatch Statistics
Composed of many single events E.g. dopant atoms Individual effects are small linear superposition applies Correlation distance << device dimensions Mismatch has Gaussian distribution, zero mean
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MOSFET Mismatch Parameter

M1 M2

Experimental result applies to one particular configuration What about:

Device size
W L Area

Bias
Experiment: VGS

I D = 1% ID

Physical proximity

Need parameterized model

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Geometry Effects
2 AP 2 2 (P ) = + SP Dx WL 2

2 (P ) :
WL : Dx : AP : SP : :

standard deviation of P active gate area distance between device centers measured area parameter measured distance parameter, 0 for common - centroid layout

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Example: VTH
2 (VTH 0 ) =
2 AP ,VTH 0

WL

2 2 + SP D ,VTH 0 x

AP , NMOS 30 mV m AP ,PMOS 35 mV m ( 2.5m CMOS process)

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Drain Bias, VDS

VTH0 virtually independent of VDS

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Back-Gate Bias, VSB

Pair 3 exhibits significant VSB dependence Why?
Non-uniform doping profile (VTH adjust)
VTH = VTH 0 +

B VBS B

2 (VTH ) = ... 2 ( ) = ...

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Current Matching, ID/ID

Strong bias dependence (we knew that already)

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Current Factor

W = Cox L

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Edge Effects

Relative Matching? Model?

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Edge Model
2 ( ) 2 (W ) 2 (L ) 2 (Cox ) 2 (n ) = + + + 2 2 2 W2 L2 Cox n
for
2 (W ) 1W
and

2 (L ) 1 L

this simplifies to
2 2 AC A 2 ( ) AL AW 2 2 = + + + + S D 2 WL2 W 2 L WL WL 2 2
ox

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Orientation Effect

Si and transistors are not (perfectly) isotropic keep direction of current flow same!

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Distance Effect

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Model Summary

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Example: Current Mirror

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Example: Bandgap Reference

VBG = 25 mV Dominated by amplifier offset Area offset tradeoff

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Process Dependence
Example: VTH vs. tox VTH matching appears strongly correlated with tox Reason?
tox is not only difference Doping concentration?

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0.18 m CMOS

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0.18 m CMOS

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Example: Current Mirror

I D g m = VTH + ID ID

I D

ID

2 2 2 2 * VTH + ( 1 ) V

100m/0.25m NMOS
2 V
TH

Ao 33.3 106 V 2m 2 2 = = (1.15mV ) WL 100m 0.25m

4 2 4 3

6.1 103 V m A2 0.91 103 V m A2 Ao AW 2 W 2 2 + 2 = = (15.6 V A ) ( 1 ) 2 WL W L 100m 0.25m (100m ) 0.25m L

I D

ID

1.15mV A V2 2 + 200 2 15.6 = (0.66% ) 200 mV V A 4 2 4 3 14 4 4 244 4 3 1 0.31% 0.58%

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Example: Differential Pair

Vos = VTH
2 2 = V V
os

V * + 2
2

TH

V * 2 2 + 2 ( 1 )

100m/0.25m NMOS

2 2 VTH

Ao 33.3 106 V 2m 2 2 = = (1.15mV ) WL 100m 0.25m

4 2 4 3

6.1 103 V m A2 0.91 103 V m A2 Ao AW 2 W 2 2 + 2 = = (15.6 V A ) ( 1 ) 2 WL W L 100m 0.25m (100m ) 0.25m L

2 V

os

2 120 mV A V 2 2 (1.15mV ) + 200 2 15.6 = (1.17mV ) 2 444 V A 4 2 4444 4 3 14 0.19 mV

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Careful Layout
Minimize systematic errors
Geometry
Proximity effects: diffusion, etch rate Orientation

Gradients
Process Temperature Stress

Ref: A. Hastings, The art of analog layout, Prentice Hall, 2001

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Layout Tradeoffs
Matching often involves tradeoffs:
Increased channel length Increased circuit area increased power dissipation, reduced speed,

Determine required level of matching

Minimal:
3Vos > 10mV, 3ID/ID > 2% Unit elements, matched orientation, compact layout

Moderate:
3Vos > 2mV, 3ID/ID > 0.1% Apply most or all layout rules

Precise:
Trimming or self-calibration

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1. Unit elements
Equal L Equal W (use M)

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2. Large Active Areas

Reduce random variations Use statistical analysis as a guide

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3. Bias Point
Voltage matching (differential pair):
Small V* Long L

Current matching (mirror):

Large V* Same VDS
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4. Same Orientation
Transistors look symmetrical Actual devices are not:
Silicon is not isotropic Implants are not isotropic

What about ac?

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5. Compact Layout
Minimize stress and temperature variations & random fluctuations Avoid poor MOSFET aspect ratio
E.g. W/L = 1000/0.35 Use fingers: 50/0.35, M=20 ~ square layout

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6. Common Centroid Layout

Cancels linear gradients Required for moderate matching Common-centroid rules:
Coincidence Symmetry Dispersion Compactness Orientation
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7. Dummy Segments
Place dummy segments at ends of arrayed devices Protects from processing non-uniformity e.g. etch-rate

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8. Stress Gradients
Global: from package
Place devices in areas of low stress Generally center of chip At odds mixed-signal floor plans

Local: metalization
Do not route metal across active area If unavoidable: add dummies so that each device sees same amount of metal
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9. Contacts
Do not place contacts on top of active area
Induce threshold mismatch God knows why

Compromise: minimize the number and make each gate identical Beware of proximity effects when connecting multiple gates with poly
Use metal interconnects or Use poly connectors on either side of transistor
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10. Junctions
Keep all junctions and deep diffusions away from transistors (except S/D)
Extend well boundary at least 2x junction depth Just because the layout rule permits it, minimum spacing is not always the best solution
Not all spaces are critical for overall layout area
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11. Oxide thickness

Devices with thinner oxide usually exhibit better matching
Use minimum tox devices for best matching if the process offers a choice

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12. NMOS vs PMOS

NMOS usually exhibit better matching than PMOS
Why? Random matching, 0.18m data:
VTH of PMOS has better matching (2x) of NMOS matches better (4.5x !)

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13. Power Devices

Power devices create temperature gradients and inject carriers into the substrate
dVTH / dT = -2mV/oC !

Keep matched devices away from power sources (>50mW) Beware of Temperature Memory Effect: Use common-centroid layout for matched devices with different current density
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Common-Centroid Layout

Determine groups of matched components

Depends on circuit function E.g.
All transistors in a mirror Diff-pair and load in an amplifier
Should they be matched individually or jointly?

Divide into segments

Unity element Avoid small (<70%) fractional elements if no GCD

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Common-Centroid Patterns

Coincidence:
Center of all matched devices co-incide

Symmetry:
X- and Y-axis Rs and Cs exhibit 1-axis symmetry

Dispersion:
High dispersion reduces sensitivity to higher order (nonlinear) gradients E.g.
ABBAABBA: 2 runs (ABBA) of 2 segments (AB, BA) ABABBABA: 1 run of 2 segments (AB, BA) ABABBABA has higher dispersion (preferable)
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Common-Centroid Patterns
Compactness:
Approximately square layout 2D patterns
Better approximation of square layout Usually higher dispersion possible, e.g.
DBSAD DASBD DASBDBSAD DBSADASBD DASBDBSAD DBSADASBD DASBDBSAD DBSADASBD

Orientation:
Stress induced mobility variations: several percent error Tilted wafers: ~5% error

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