DATASHEET

VC Verification IP for DDR3

Highlights Overview
• Native SystemVerilog/UVM Synopsys VC Verification IP for DDR3 provides a comprehensive set of protocol,
• Runs natively on all major simulators methodology, verification and productivity features, enabling users to achieve
accelerated verification closure of DDR3 based designs.
• Verdi Protocol-aware debug
• Built-in verification plan and coverage VIP can be integrated, configured and customized with minimal effort. Testbench
• Built-in protocol and timing checks development is accelerated with built-in verification plans, example tests, and
functional coverage. VIP is natively integrated with Verdi Protocol Analyzer,
• Runtime JEDEC and vendor part selection
a protocol-centric debug environment that gives users graphical view of VIP
• Overriding timing parameters operations, transactions, and memory content view for easy and fast debug.
• Backdoor memory access
• Bypass/fast initialization Coverage
• Error injection & exceptions
Sequence Configuration User
• Trace files and debug ports library MemCfg creator test plan

• Configuration creator GUI Testbench

VIP
test plan
Memory VIP
Key Features
Configuration Coverage
• JESD79-3F DDR3, JESD79-3-1A-01 DDR3L
database
and JESD79-3-2 DDR3U JEDEC SDRAM Sequencer
Virtual sequencer
User tests

device standards
User tests

MemServer
• MRAM support
• Built-in UDIMM, SODIMM, Reactive driver
Debug
RDIMM, and LRDIMM
Verdi
• 512Mb to 8Gb densities and x4, x8 and Monitor
Protocol and
x16 wide SDRAM devices Functional coverage memory analyzer
DUT
• BL switch on the fly, 8 banks, Protocol checks
Source code
8 bit pre-fetch Analysis port visibility
• Write leveling, read leveling, jitter,
auto self refresh
• Address mirroring Figure 1: VIP block diagram

• Delay modeling: Fly by Delay, Trace Delays,

Pre and Post buffer delays
• DFI monitor Methodology Support
Synopsys VC VIP, based on its next generation architecture, is implemented 100%
in native SystemVerilog and UVM. It also supports Verilog testbenches and runs
natively on all major simulators for optimum performance.

synopsys.com/VIP
DDR3 Verification Features
• Support configurations for memory vendors and randomization to model all possible legal JEDEC parts
• Support to specify part details using runtime parameters without re-compilation
• JEDEC virtual part approach
• Bypass and fast-memory initialization to reduce simulation time
• Error injection and exception mechanism
• Easy method to vary timing parameters and clock
• Support to override logical address formatting as per application level address of host
• Extensive protocol and timing checks
• Checks can be enabled or disabled
• Complete functional coverage
• Back annotation of coverage
• Backdoor access to memory contents and mode registers
• Debug port for high level of abstractions including logical address, commands, states etc.
• Visibility of interfaces and buffers inside DIMM models
• Readable trace log file to debug and analyze memory transactions

Verdi Memory Aware Debug

The growth in complexity and increasing number of protocols used in SoCs is creating a rapidly increasing verification challenge and
debug bottleneck for verification engineers. Verification engineers must quickly become protocol experts and try to correlate information
across different sources to find root cause of problems. Verdi Protocol Analyzer provides protocol-centric debug which enables user
to quickly understand protocol activity, identify bottlenecks and quickly find and debug unexpected behavior. Protocol analyzer shows
signals as well as transactions across protocol layers for unified debugging.

Transaction
view

MemValue
view

Color indicates most recent activity

Time range "kind" (for currently-displayed time)
Address range
= write = read = file load
= poke = peek = pattern

Figure 2: Verdi memory aware debug

2
Verification Plan and Functional Coverage
Synopsys VIP comes with a XML verification plan. The verification plan shows how each functional coverage group is directly
mapped to the protocol specification. This verification plan is hierarchical with sub-plans based on the DUT feature set. The functional
coverage support in VIP includes coverage for protocol, toggle, transaction, configuration along with cross coverage. In addition,
sequential coverage is provided that covers complex sequences that are hard to derive directly from the protocol specification.
Coverage is “configuration aware” which means bins are ignored if they are not applicable to the VIP configuration. Users can extend
the built in coverage to add their own bins based on built in VIP sampling events and groups or create their own groups with any
sampling event or data.

Configuration Creator
The Configuration Creator offers an interactive GUI that provides an easy to use protocol-aware environment to create, edit and export
VIP configuration files. Configuration Creator provides users a simple process for creating custom VIP configuration files and validating
them before simulation with the Synopsys VIP.

Information on New Features

This data sheet provides a summary of supported protocol features and may not reflect all the features added in recent releases.
Please contact your local Synopsys sales office for complete information about new features and enhancements.

Synopsys offers a broad portfolio of interface, bus and memory Verification IP and Test Suites.
For more information visit: synopsys.com/VIP

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available at synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.
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