Abdu Rahiman V
Lecturer in ECE Govt. College of Engineering, Kannur, Kerala, India
Abdu Rahiman V. Govt. College of Engg. Kannur.
Memory
Store instruction and data Memory requirements Should be as fast as processor Large size Low cost Essential in any processing unit
Abdu Rahiman V. Govt. College of Engg. Kannur.
Processor and memory interface
MAR k Bit address bus
Memory
n bit Data bus Upto 2k addressable locations Word length n bits
MDR
Control bus
Abdu Rahiman V. Govt. College of Engg. Kannur.
Memory
Units used with memory Byte, KB, MB, GB, TB Memory access time- time between giving read signal and
receiving MFC Memory cycle time minimum time required between two successive read signals Random access memory any location can be read or written in a fixed time Serial access memory memory access time depends on the position of data Types of memory
Main memory or primary memory Secondary memory Cache memory
Abdu Rahiman V. Govt. College of Engg. Kannur.
Organization of memory cells in a memory unit - Example b7 b1 b0
b7 b1 A0 A1 A2 A3 Address decoder W0 . . .
FF
b0
. . .
W1
W15
RD/WR
. . .
Sense/ Write RD/WR Sense/ Write RD/WR Sense/ Write
b7
Abdu Rahiman V. Govt. College of Engg. Kannur.
b1
b0
Bipolar Memory Cell
T1 OFF & T2 ON Logic 1 T1 ON & T2 OFF Logic 0 Read operation Make word line zero volt A voltage is applied on bit lines Diode near the transistor in ON state will draw a current Write Operation Set voltages on the bits lines and make word line low Respective transistor will turn ON and the other will become OFF
Bit Line Vcc Bit Line
R1
R2
D1
D2
T1
T2
Word Line
Abdu Rahiman V. Govt. College of Engg. Kannur.
CMOS Memory Cell
T1 OFF & T2 ON Logic 1 T1 ON & T2 OFF Logic 0 Bit Line Read operation Make word line high T5 & T6 ON, voltages at the points are available on bit lines Write Operation Set voltages on the bit Word lines and make word line Line high
Bit Line Vcc
T3
T4
T5
T6
T1
T2
Ground
Abdu Rahiman V. Govt. College of Engg. Kannur.
Dynamic Memory
Minimum number of
transistors required High density memory fabrication is possible Volatile Refresh circuitry is required Low cost per bit
Word Line
Bit Line
Abdu Rahiman V. Govt. College of Engg. Kannur.
Addressing multiple module memory system
Module
ABR- Address Buffer Register DBR- Data Buffer Register
Address in Module
Data Bus
ABR DBR ...
ABR DBR ...
ABR DBR
Consecutive memory locations
are stored in same module
Abdu Rahiman V. Govt. College of Engg. Kannur.
Addressing multiple module memory system
Address in Module
ABR- Address Buffer Register DBR- Data Buffer Register
Module
Data Bus
ABR DBR ...
ABR DBR ...
ABR DBR
Consecutive memory locations are stored in same consecutive
module Memory interleaving
Abdu Rahiman V. Govt. College of Engg. Kannur.
Memory interleaving
It is possible to access multiple words in one cycle Reduces the total time to read the required data
Abdu Rahiman V. Govt. College of Engg. Kannur.
Cache Memory
Processor
Cache memory
Main Memory
Secondary Memory
Small size High speed High cost
Medium size Medium speed Medium cost
Large size low speed Low cost
Abdu Rahiman V. Govt. College of Engg. Kannur.
Cache Memory
Locality of reference
Spatial:-the instructions stored in nearby locations are
likely to be executed repeatedly
Temporal:- the instructions executed recently are
likely to be executed repeatedly
Abdu Rahiman V. Govt. College of Engg. Kannur.
Cache Memory
High speed memory to store small portion of main
memory Cache and main memories are divide in to small blocks Block containing the data referenced is brought in to the cache memory
Abdu Rahiman V. Govt. College of Engg. Kannur.
Main memory
Block 0 Block 1
Cache memory
. . Block m-1 Block m Block m+1 . . Block 2m-1 Block 2m Block 2m+1 . . Block pm-1
Block 0 Block 1 . . Block m-1
Abdu Rahiman V. Govt. College of Engg. Kannur.
Cache Memory
Any modification made in cache has to be made in
main memory also Write through : write to main memory along with the write to cache Write back : write to cache, if it is modified, before discarding the cache content Dirty/modified bit: set to 1 if the content of cache is modified Valid bit:- to indicate cache contain valid data
Abdu Rahiman V. Govt. College of Engg. Kannur.
Cache memory mapping functions
Direct Mapping
Block 0 Block 1 Block 0 Block 1 . . Block m-1 . . Block m-1 Block m Block m+1
Searching is easy
Tag field used to identify
the block
. .
Block 2m-1
Main Memory Address Cache Tag Word Address block
Abdu Rahiman V. Govt. College of Engg. Kannur.
Block 2m Block 2m+1 . . Block pm-1
Direct mapping - Example
Block size 16 bytes
Block 0 Block 1 Block 0 Block 1 . . Block 63 . . Block 63 Block 64 Block 65
Total main memory 16
KB Number of blocks in main memory 1024 Cache size 1 KB, 64 blocks
. .
Block 127 Block 128 Block 129 . . Block 1023
Main Memory Address Cache Tag Word Address block 4 bits 4 bits 6 bits
Abdu Rahiman V. Govt. College of Engg. Kannur.
Associative mapping
Any block can be loaded
Block 0 Block 1 Block 0 Block 1 . . Block m-1 . . Block m-1 Block m Block m+1
to any available block in cache
. .
Block 2m-1
Main Memory Address Tag Word Address
Block 2m Block 2m+1 . . Block pm-1
Abdu Rahiman V. Govt. College of Engg. Kannur.
Associative mapping - Example
Block size 16 bytes
Block 0 Block 1 Block 0 Block 1 . . Block 63 . . Block 63 Block 64 Block 65
Total main memory 16
KB Number of blocks in main memory 1024 Cache size 1 KB, 64 blocks
Tag 10 bits
. .
Block 127 Block 128 Block 129 . . Block 1023
Main Memory Address Word Address 4 bits
Abdu Rahiman V. Govt. College of Engg. Kannur.
Set Associative mapping
Blocks can be moved
Block 0 Block 1
to free blocks in the set
Set 1
Set 2
Block 0 Block 1 Block 2 Block 3 . .
. . Block m-1 Block m Block m+1
. .
Block 2m-1 Block 2m Block 2m+1 . . Block pm-1
Set p
Block m-2 Block m-1
Main Memory Address
Tag
Set Number
Word Address
Abdu Rahiman V. Govt. College of Engg. Kannur.
Set Associative mapping - Example
Block 0 Block 1
Block size 16 bytes
Set 0 Set 2
Block 0 Block 1 Block 2
. . Block 63 Block 64 Block 65 . . Block 127
Total main memory 16
KB . Number of blocks in . Block m-2 main memory 1024 Set 31 Block 63 Cache size 1 KB, 64 blocks and 32 sets Two way set associative Main Memory Address mapping
Block 3
Block 128
Block 129 . .
Block 1023
Tag 5 bits
Set No. 5 bits
Word Address 4 bits
Abdu Rahiman V. Govt. College of Engg. Kannur.
Cache memory
Cache hit - accessed data is present in cache Cache miss accessed data is not present in cache
Hit rate Number of hits / total access attemps
In case of cache miss, new data block has to be moved
to cache memory Miss penalty The delay to fetch the block after cache miss
Abdu Rahiman V. Govt. College of Engg. Kannur.
Cache Replacement Schemes
Least Recently Used :- Remove the LRU block and
replace with the new one Oldest block:- Remove the oldest block and copy the new one
Performance of this method is very poor
Random replacement:- Randomly select the block to
be replace.
This method has relatively good performance
Abdu Rahiman V. Govt. College of Engg. Kannur.
Thank You
Abdu Rahiman V. Govt. College of Engg. Kannur.
