Modeling IC Packages with FLOTHERM & FLOPACK
Package Level Modeling Goals and Challenges Basic Packaging Concepts Package Characterization Introduction to FLOPACK
Modeling Goals
Why is package level modeling necessary ?
The only reliable way to obtain accurate case temperature The only reliable way of obtaining accurate junction temperature Junction temperature drives reliability; Case temperature provided to end-user
Modeling Challenges
Keeping
up with the rapidly changing field of IC packaging is difficult, especially for system designers (end-users). Some modeling assumptions are not obvious
Do I model my trace layers in a PBGA discretely? Can I neglect the bond wires in modeling a PQFP? Can I represent my thermal vias as a lumped block?
Generating
and tedious Information about the internal details of a package may be difficult to obtain
component models is time consuming
Basic Packaging Concepts
What
is an electronics package?
The combination of engineering and manufacturing technologies required to convert an electronic circuit into a manufactured assembly Martin Miller, Electronic Packaging, Microelectronics and Interconnection Dictionary
What
is an electronics package? (Intelligible definition)
An intermediary between the IC chip (die) and the PCB
Basic Packaging Concepts
Highly
multi-disciplinary field:
Materials Manufacturing Thermal Electrical
Functions
of a package:
Electrical
Power distribution Interconnection
Mechanical
Die protection
Thermal
Heat dissipation
Basic Packaging Concepts
Die enclosure
Die
Level 1 interconnect Level 2 interconnect PCB Substrate
A package need not have all of the above elements The die, of course, is always present!
Basic Packaging Concepts
Package Classifications:
Plastic Packages
Generally, more challenging to model Cheaper Less reliable Non-hermetic Often need thermal enhancements Majority of the worlds packages Applications: ASICs, Logic chips, Memory chips, low powerprocessors
Ceramic Packages
More expensive More reliable Best electrical characteristics (fine line widths, multiple layers) Hermetic Excellent thermal performance Small number of packages in use Applications: High-power processors
Package Characterization
Standard
test methods defined by JEDEC are provided as a basis for comparison between various packages and devices. Well defined environments are used to ensure reliability and consistency between vendors. The thermal resistance values are not meant to and will not predict the performance of a package in an application-specific environment.
Package Characterization
Thermal
Resistance of a Package:
Defined as the resistance to heat transfer between two specified points.
jx
T j Tx P
Tj = temperature at active surface of die (junction) Tx = temperature at some reference point P = package power
Package Characterization
ja
(Natural Convection)
Most common concept Defined by JEDEC 51_2 :
ja
T j Ta P
Ta = ambient temperature, taken inside a specific enclosure defined by JEDEC (Still-Air Test) Measurements taken either with a High-k (2S2P) and Low-k (1S0P) board
Package Characterization
jma
(Forced Convection)
Speeds from 0-1000 LFM Defined by JEDEC 51_6 :
jma
T j Ta P
Ta = ambient temperature, taken upstream in the wind tunnel Board orientation is an important factor
Package Characterization
jc (junction to case resistance) The thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that same surface is properly heat sunk so as to minimize temperature variation across that surface.
jc
Ambient Die
T j Tc P
Case Junction
Substrate PCB
Package Characterization
Thermal Resistance of a Package
Convection/Radiation Conduction Convection Conduction Radiation Convection/Radiation
Case
qjc
Junction
Conduction
Package Characterization
jb (junction to case resistance) The thermal resistance from the junction to the board.
jb
T j Tb P
Package Characterization
Thermal Resistance of a Package
jc tries to represent the many complex heat flow paths with a single thermal resistance Problem is most problematic with PBGAs Plastic Encapsulant exaggerates temperature gradient on surface Solder balls and vias increase parasitic losses to the board
Compact Models
Generates
Compact Models (Two-resistor and DELPHI)
SmartParts Available Today
21 Package Families 5 Ancillary Parts
Packaging Materials
Plastics/Resins Epoxy, FR-4, Polyimide, BT, die attach materials Metals/Alloys Copper, Solders (Pb/Sn alloys), Kovar, Alloy-42, Aluminum, Gold, Tungsten, etc. Ceramics Alumina (Al2O3), AlN, BeO Semiconductors Silicon, Gallium Arsenide (GaAs)
Packaging Materials
Relevant
properties of packaging materials:
Conductivity - Usually invariant with temperature Exceptions :
Silicon, AlN, BeO
Glass transition temperature for organic materials (Tg) - Temperature above which material loses its laminate
characteristics. Typical values: FR-4 = 125 C, BT = 200 C
Coefficient of Thermal Expansion (CTE) - Must match
for reliability. Particularly bad combinations: Si-FR4, Si-BT, Si-Cu. Good combinations: Cu-FR4, Si-Ceramics
Specific Heat Density
Silicon die BT substrate
Underfill
Interconnections
Recall the basic structure of a package:
Die enclosure Die
Level 1 interconnect Level 2 interconnect PCB Substrate
Die
level interconnections (Level 1)
Wire Bonding, Tape Adhesive Bonding, Flip Chip
Board level interconnections (Level Pins, Peripheral Leads, Solder Balls
2)
Interconnections: Level 1
Level
1 Interconnect is the coupling between the die and the substrate
Objective: to route signals and power to die while minimizing electrical degradation
Three
types of Level 1 Interconnect:
Wire Bonding Tape Adhesive Bonding (TAB) Flip-Chip (C4)
Interconnections: Level 1 Wire Bonding
Traditional
technology Bond wires typically
0.8 - 1.2 mil in diameter Gold or Aluminum
Advantages:
Substrate Bond Wire Pad on Substrate Die
Mature, low cost technology Reliable
Disadvantages:
Peripheral, not area array; low I/O density Pitch on die limited to usually of 3 mils Large signal lengths; high self-inductance
Interconnections: Level 1 Wire Bonding
Modeling Bond Wires
Can be ignored in ceramic packages May be significant in plastic packages with low metal content
Suggested modeling approach:
Represent as cuboid with equivalent (volume averaged) orthotropic conductivity
Interconnections: Level 1 Tape Adhesive Bonding (TAB)
Technology
introduced in the 1970s Popular in Japan, not much in the U.S. Leadframe is directly bonded to the I/O pads on die periphery, in a process known as Inner Lead Bonding Leadframe is normally attached to a (usually polyimide) tape, hence the name
Bumped die Die Polyimide Tape Cu leadframe
Interconnections: Level 1 Tape Adhesive Bonding (TAB)
Disadvantages:
More expensive today than wire-bonding Peripheral array, I/O density not high
Advantages:
Short interconnect length, excellent electrical performance Can handle up to 2 mil pitch on die periphery
Modeling:
This interconnection can usually be ignored in CFD modeling (insignificant thermal resistance)
Interconnections: Level 1 Flip-Chip Bonding
Has
its roots in an IBM technology of the 1960s ( called C4) Did not become popular till late 1980s Die connected with substrate through solder balls
Usually not in regular array Common solders: 37Pb/63Sn, 95Pb/5Sn Typical dia ~ 3 mils
C4 Die Substrate Underfill
Interconnections: Level 1 Flip-Chip Bonding (C4)
Disadvantages:
Can have major CTE mismatch problems Underfill makes rework practically impossible Higher cost (although this is dropping)
Advantages:
Collapsed Cuboid Die Substrate
Best electrical performance of all methods Area array leads to highest I/O density
Modeling:
Usually have a small, but significant thermal resistance, especially for ceramic packages. Negligible spreading in Flip-chip layer Best modeled as collapsed cuboid with volume averaged conductivity
Interconnections: Level 2
Level
2 interconnect: coupling between the package substrate and PCB Can generally be classified by mechanical attachment method and I/O arrangement:
Surface mount (SMT) : I/Os rest (usually soldered) on PCB surface.
Surface Mount/Peripheral leaded
Through-hole(TH): I/O physically penetrate the PCB through holes
Through Hole/Area Array
Interconnections: Level 2
Three
ways of coupling substrate and board:
Pins Peripheral leads Solder balls
Interconnect method Peripheral Leads Solder Balls Pins Mechanical Surface Mount, Through Hole Surface Mount Through Hole I/O Arrangement Peripheral Area Array Area Array
Peripheral Leads
These
are most commonly surface mounted (exception, Dual In-line Package) in PQFPs, SOPs etc. Pitches have shrunk to as low as 16 mils (0.4 mm) I/O counts up to ~ 400 Mature, low cost technology I/O limits due to peripheral array, co-planarity problems Leads typically of Copper (older packages, Alloy-42)
Modeling Peripheral Leads
Gull-wing leads
Advantages:
J-leads
Low cost, mature technology Easy to inspect for faults No CTE mismatch problems with FR-4 boards
Disadvantages
Long interconnect lengths, high self-inductance Lead co-planarity problem Peripheral array; low I/O density
Modeling Peripheral Leads
Modeling advice:
Form a critical heat transfer path for peripheral leaded packages Model as equivalent cuboid of volume averaged orthotropic conductivity. Modeling leads discretely does not improve model accuracy significantly for packages with a large number of leads.
Solder Balls
Package
using solder balls is knownPeripheral Balls Central/Thermal as Ball Grid Array (BGA) Balls Technology pioneered by IBM in the 1960s, Found wide acceptance in the 1990s BGA use is rising almost exponentially, especially in the U.S. Solder balls typically of 95Pb/5Sn or 37Pb/63Sn Array can be peripheral, with solder additional central balls Underfill rarely present
Solder Balls
Advantages
of solder ball interconnect:
High I/O density Excellent electrical performance (low self-inductance) Self-aligning during reflow, low manufacturing defect rate
Disadvantages:
Difficult to inspect for defects Possible CTE mismatch Not cheap (although cost is dropping)
Modeling Solder Balls
Modeling
choices:
Each solder ball discretely, as a cuboid:
Actual solder balls
FLOPACK discrete solder balls modeled as cuboids with
equivalent crosssectional area
Modeling Solder Balls
Modeling
choices:
As full cuboid (orthotropic)
Full Cuboid
Low conductivity in in-plane directions
High conductivity in through-plane direction
Pins
Package
using pins is called a Pin Grid Array (PGA). (More on PGAs later.....) Pins are typically made of Kovar (an alloy) They are often by means of a socket, connecting with the PCB through its own pins
Package pins Socket Socket pins
Modeling Pins
Most
pins have pitches of 50 mils or 100 mils and diameters of about 15 mils I/O counts of up to ~ 800 Modeling approach:
Ceramic packages: can model as equivalent volume averaged cuboid, as ceramic substrate is a good heat spreader Plastic packages: may need to model as discrete pins, especially if die size is small
Modeling ICs
Component Building Blocks Boards Heatsinks JEDEC standard test configurations
The Die
Term
for the piece of semiconductor on which all the active circuits lie Usually made of Silicon Gallium Arsenide is used in some special applications (microwave/high speed) Circuitry present within a thin layer on one side only, known as active surface
Circuitry Active surface
Die body (typically silicon)
The Die
Modeling advice:
Model as a cuboid with temperature dependent conductivity (for Silicon) Place collapsed source on active surface to represent heat dissipation Do not forget to set the source direction inwards, within the die!
Collapsed source
Cuboid
Die Flag
Die Flag:
The die is often placed (usually in plastic packages) on a thin metal plate known as the die flag or die pad. The die flag serves either a manufacturing or a thermal function, or both. The die flag is usually made of copper, and is typically larger than the die
Die Flag
Die
Die Flag
Die
Flag: the Die Flag:
Because the die flag is metallic, it can act as a very effective heat spreader
Modeling
It is recommended that the die flag be modeled discretely Spreading within the die flag can reduce the thermal resistance of a package by ~ 15 % This is small, but not insignificant!
Die Attach
Die
Attach:
The die is often attached to the substrate or the die pad by an adhesive known as the die attach It is often made of an epoxy based compound Typical values for die attach: Thickness = 1-2 mils, Conductivity = 1- 2 W/mK
Die Attach Die pad Die
Die Attach
Modeling the Die Attach:
Negligible spreading, but thermal resistance can be significant Model as collapsed cuboid
Die Protection
The die is fragile and needs protection (although packages with bare dies do exist) Two common means of protection:
Overmolding Capping
Overmolding
Overmolding:
Overmold is almost always an epoxy based compound Low conductivity (0.6 - 0.8 W/mK) A significant contributor to thermal resistance To reduce this resistance, a metallic slug is sometimes placed inside a plastic package
Metal Slug Adhesive Overmold
Die
Capping
Die
Capping:
In ceramic packages Capping seals off the die cavity Cap usually made of aluminum Model cap as cuboid May need to consider effects of radiation between cap and die
Cap Ceramic substrate
Die
Leadframes
Leadframes:
A characteristic of all peripheral leaded packages Most packages with leadframes are plastic (PQFP, SOP, PLCC), but ceramic ones do exist (CQFP) Leadframes normally made of Copper, although Alloy-42 (a Ferrous alloy) can be found in older designs
Die Flag
Internal Leadframe External Leadframe
Die
Leadframes
Leadframe
attachment:
Leadframe typically wire bonded to die TAB bonded in TAB packages When wire bonded, gap between die flag and leadframe is an important thermal bottleneck
Bond wire Die Die flag Leadframe Thermal bottleneck Die attach
Modeling Leadframes
Leadframe modeling:
Can be modeled as cuboid blocks with volume averaged, orthotropic conductivity Take average extent for internal leadframe
Substrates
A
substrate is an element on which the die is mounted to and which routes the I/Os from die to PCB Critical element from thermal standpoint Packages without a substrate: PQFP, SOP (e.g) Substrates:
Ceramic Organic
Ceramic Substrates
Ceramic
Substrates:
Most commonly made of Alumina (k = 20 W/mK) For better thermal performance, AlN or BeO also used (k ~ 200 W/mK) BeO is hazardous, requires special handling Ceramic layers placed together and fired in high temperature oven Metal traces usually made of Tungsten or Molybdenum
Ceramic Substrates
Ceramic substrate
Ceramic Substrates
Advantages:
Hermetic; highly reliable Fine line widths Excellent thermal performance Many (20 +) trace layers possible Good CTE match with silicon die
Disadvantages:
Require specialized, expensive manufacturing technique CTE mismatch with FR-4 PCB, large packages need underfill
Ceramic Substrates
Applications:
High power, heavy duty packages such as processors
Modeling Ceramic Substrates:
Relatively high conductivity Model simply as cuboid blocks Metal traces can be usually ignored Vias can be usually ignored
Organic Substrates
Organic
substrates:
Present only in plastic packages e.g. Plastic Ball Grid Array (PBGA), Plastic Pin Grid Array (PPGA) Challenging to model Dielectric made of a plastic based laminate resin; metal is usually copper
Die
Resin
Organic Substrate Metallization
Organic Substrates
Advantages:
Lower dielectric constant than ceramic substrates Manufacturing technology similar to that for PCBs Less expensive to manufacture Excellent CTE match with PCB
Disadvantages:
Limited number of layers Need thermal enhancements Poor CTE match with silicon die
Applications:
ASICs, low power processors etc.
Organic Substrates
Traces:
Cu traces can be signal layers or power/ground planes Typical organic substrates are either 2-layer or 4layer 2-layer substrate often (but not always) has signal layers only (no power and grounds)
Bond wire Two signal traces Die Die Flag
Organic Substrates
Traces:
4-layer substrates have two additional power and ground planes
Bond wire
Additional power and ground planes
Die Die Flag
Organic Substrates Modeling Traces
Modeling
traces:
Lumping traces and resin together as a single cuboid or block-and-plate is not recommended! Model traces as discrete layers Within each layer, volume average based on Cu coverage
Cuboids
Organic Substrates Vias
Vias
Originally created for increasing interconnection density in multiple layer PCBs Technology migrated to organic packages Today, also used for thermal enhancement (thermal vias)
Cu plating
Air Substrate
Organic Substrates Vias
Via classification:
Signal vias electrical function can be blind/buried Thermal vias serve purely thermal function usually thru-hole
Organic Substrates Modeling Thermal Vias
Modeling
vias:
Typically model only thermal vias Difficult to model signal vias! Signal vias may be thermally significant in some packages (e.g. flip-chip), need investigation.......
Modeling
approaches for thermal vias:
as discrete
most refined approach accounts for constriction resistance Takes up more grid; introduces large aspect ratio grid cells
Modeling Boards
Technology
for manufacturing organic substrates and PCBs is similar Compatibility - Detailed Model and Board Model Need to pay attention to:
Copper Planes Vias Connectors
Radiation
important in natural convection
Modeling Boards
FLOPACK
PCB macro can create a model with an arbitrary number of layers as well as compact or discrete via groups.
Copper Planes
Dielectric
Heatsinks
If
a heatsink is present on detailed package model, it must be modeled accurately for consistency Heatsinks:
Parallel Fin
Can use FLOTHERM SmartPart, or FLOPACK
Pin Fin
Can use FLOTHERM SmartPart, or FLOPACK
Disk-fin
FLOPACK generator
Heatsinks: Gridding Tips
Proper
gridding important for resolving boundary layers within heatsinks Focus on extruded heatsinks (most common) Transverse and streamwise directions are key Transverse direction:
Use 3 cells between fins No extra grid needed within fins 2 cells sufficient to resolve base
Heatsinks: Gridding Tips
3 Grid Cells between Fins
Keypoint Cells within Fins
2 Cells in Base
Heatsinks: Gridding Tips
Streamwise
direction:
Losses = Skin friction + Contraction/Expansion Transverse gridding resolves Skin Friction Losses Streamwise gridding critical to resolving Contraction/Expansion Losses Cluster cells at entrance and exit of extruded heatsink
Normal
direction:
Less critical 3-4 cells are usually sufficient
Heatsinks: Gridding Tips
Fins
Grid clustered at heatsink entrance and exit
Heatsinks: Miscellaneous
Model radiation on heatsink surfaces in natural convection Do not forget thermal grease (model as collapsed cuboid)
JEDEC Test Configurations
JEDEC
JC 15.1 subcommittee Standards to provide Figures of Merit for comparing package performance (http:///www.jedec.org) Examples of Standards available:
Still Air Test for Theta-JA (Rja) Forced Air Test for Theta-JMA (Rjma) Ring Cold Plate for Theta-JB (Rjb) Low Conductivity Test Board (1S Board) High Conductivity Test Board (2S2P Board)
JEDEC Test Configurations
Standards
being discussed:
Cold Plate for Theta-JC Various standards for new test boards
Other:
Validation beds for computational models Reporting format for detailed models Standards for compact modeling
JEDEC Standard Test Configurations
Ring Cold Plate
Example:
Standard for Theta-JB (Ring Cold Plate)
Compact Modeling
Introduction Compact Deriving Deriving
Model Topologies 2-Resistor Models
DELPHI Compact Models
Detailed Models
Recall
that .....
A Detailed Model attempts to capture thermal behavior of a package by reproducing the physical structure of the package as completely as possible
Why Compact Models?
Limitations
of Detailed Models
Reveal internal (proprietary) construction details of packages Are computationally demanding due to large grid required
A
Compact Model seeks to capture the thermal behavior of the package accurately ....
... at pre-determined (critical) points (junction, case etc.) .... by using a reduced set of parameters to represent the package
These
parameters need not be geometric The most popular approaches use some sort of thermal resistance network representation
The First Step: 2-Resistor Models
2-Resistor
Compact Models:
T Rjc J Rjb B
A significant improvement over single-resistor metrics Simple topology Can be used in System/Boardlevel/EDA tools (via IDF 3.0) Can be derived experimentally or computationally Typical accuracy for most cases is < 20%
Generating 2-Resistor Models Current (JEDEC) Experimental Approach:
by Top Cold Plate Test jb by Ring Cold Plate Test
jc
http://www.jedec.org
FLOPACK
Computational Approach:
Shadow experimental approach Advantages:
Consistent with JEDEC standards One-to-one correspondence with experiment Intuitive; easily understood by users
2-Resistor Models in FLOPACK
Ring Cold Plate Harness
Detailed Model Top Cold Plate Harness
Conduction Solver Engine
2-Resistor Network FLOTHERM Compact Model
The Traditional Approach ( ja and jc)
The
and jc approaches lump all heat paths together as one - use with caution.
ja
and
jc
are environmentally dependent.
Inaccuracies
in predicting junction temperatures can be as high as 100%!
Arbitrary Resistance Networks
Some components may need more complex networks, especially when heat spreading within the component is significant TI Often involve Shunt resistors
TO
Shunt Resistors
BI
BO
Boundary Condition Independent Resistance Networks
DELPHI
What
is (was) DELPHI? Project that proposed new methodologies for creating and validating computational component models Ultimate Goal: to enable component manufacturers to supply validated compact thermal models of their parts to end-users Results were:
Modeling methodology for Detailed Models 2 experimental systems (Double Cold Plate and Submerged Double Jet Impingement) Modeling methodology for Compact Models
The DELPHI Methodology
Package Parameters (Geometry, Material Properties)
Deliverable
Validate against Experiments
Create a Detailed Model
Detailed Model
Run Detailed Model N Times for N sets of representative Boundary Conditions
OptimiseResistance Network to Minimize Error for N Runs
Compare Compact Model Results with Detailed Model Results to Estimate Accuracy
Create CFD Equivalent of Resistance Network Model
Compact Model
N Sets of Boundary Conditions?
...A wide variety of boundary conditions within the spectrum of possible environments encountered in electronics cooling.
Example: 100-Lead PQFP
Detailed
Model
Internal Leads
Tie Bar
Die Die Paddle External Leads
Encapsulant
100-Lead PQFP
DELPHI
Compact Resistance Network
Top Inner
Top Outer
Sides 32.5
34.9 55.9 12.2
Junction
Leads
55.2 29.1
10.3
Bottom Inner
Bottom Outer
Compact Models in FLOPACK
Users
can either :
Generate their own compact models using FLOPACK Use compact models generated by component supplier
FLOPACK
generates a compact model as a PDML downloadable Compact Component SmartPart User simply imports the model and locates it correctly in their model User should not change entries except power
Package Styles
SmartPart
construction dependent on whether the package is:
Area Array (BGA, PGA, etc.) Peripheral Leaded (PQFP, TSOP, etc.)
Area
Array:
Heat transfer through top and bottom only Two solder ball regions possible
Leaded:
Heat transfer through top, bottom, and leads Leadframe could be 2-sided (Dual) or 4-sided (Quad)
The Compact Component SmartPart (Area Array)
Top Outer Bot Outer
Top Inner Junction Bot Inner
Top Outer Bot Outer
Cuboid blocks in three layers create isothermal nodes Cuboids representing solder balls (not included in SmartPart)
Top Outer Top Outer Top Outer
Top Outer Top Inner
Top Outer Top Outer Top Outer
Top Outer
The Compact Component SmartPart (Leaded)
Extra Cuboids representing peripheral lead resistance
Obtaining Junction Temperature
Place
monitor point in the middle of the junction region Can also use Tables Window
Example
As
an example, we will examine the implementation for an area array package, a Flip-Chip Plastic Ball Grid Array (FC-PBGA) Bare die protruding at top Inner and outer solder balls
FC-PBGA: Top Nodes
Top
surface partitioned to Top Inner and Top Top Inner Outer
Top Outer
FC-PBGA: Bottom Nodes
Bottom
surface partitioned to Bottom Inner and Bottom Outer
Bottom Inner
Bottom Outer
Network Menu
Node
Resistance (C/W)
Changing Power in SmartPart
Compact Models in FLOPACK
Two-Resistor Compact Models:
Currently available for all package styles
Complex (DELPHI) Compact Models:
Have already been introduced in FLOPACK for some package styles. New styles will be added periodically
What are Thermal Networks?
Thermal Network Models (TNM) are an extremely convenient method to represent heat transfer problems in terms of Thermal Resistances and Thermal Capacitance. It is useful to exploit the Electric Circuit analogy and make use of the existing well developed techniques to solve the network problem. Thermal Electrical
Heat Energy (Joules) Heat Flow Rate - Q (Watts) Temperature Difference - T (Kelvin) Thermal Resistance - Rth (K/W) Thermal Capacitance - Cth (J/K) Charge - Q (Coulomb) Current - I (Amperes) Potential Difference - V (Volts) Electrical Resistance R (Ohm- V/A) Electrical Capacitance - C (Farad C/V)
Typical Characteristics of TNM
Steady State
Only Resistance elements are necessary Conduction Very well suited for problems which result in predominantly one-dimensional heat flow pattern. Complicated networks may be needed to represent multidimensional problems. Convection and Radiation Not suitable for most of the engineering problems of interest. May be used as an simplified boundary condition for the conduction problems.
Transient
Both Resistance and Capacitance elements are necessary Otherwise quite similar to the Steady State Models
Compact Transient Thermal Model in FLOTHERM
Transient Thermal data
Transient Thermal data
From detailed model (or) datasheet (or) experiments
Network Identification
Number of RC Components and interconnections Needs good understanding of the thermal paths
Network Identification
Network Parameter Calculation
Lots of Mathematics! Laplace Transforms, Matrix Algebra, Inverse Transforms etc etc..
Network Parameters Calculation
Material Property Calculation
To represent R,C parameters in terms of k, and C with appropriate geometry
Material Property Calculation Implementation in FLOTHEM
Implementation in FLOTHERM
Model an equivalent network in FLOTHERM using existing options
Transient Thermal Data
The input data can be from
Detailed Model The package internal details are required Component level simulations for various conditions Device datasheet Supplier specified Transient Thermal Impedance curve Experimental data Only if both of the above are not available (or) reliable.
Transient Thermal data
Network Identification
Network Parameters Calculation
Material Property Calculation
Implementation in FLOTHEM
Network Identification
Networks can be of
One-Dimensional Only one major heat path Very short transients (semi-infinite assumption) Multidimensional More than one major heat path MCMs Interaction between various power cells within a die
Transient Thermal data
Network Identification
Network Parameters Calculation
Typical Types of Network
Foster No physical significance Simple circuit equations Cauer Physically meaningful Extremely complicated Transformation is possible from one from to another
Material Property Calculation
Implementation in FLOTHEM
Network Parameter Calculation
One-Dimensional Networks
Assumed RC Values
Transient Thermal data
Foster Network
Network Identification
Measured Temperature Step Response Tm(t)
Simulated Temperature Step Response Ts(t)
Changed Network Parameter
Network Parameters Calculation
Material Property Calculation
Compare Ts and Tm Good
Bad
Implementation in FLOTHEM
Foster to Cauer Transformation
Calculated Network Parameter
Network Parameter Calculation
Multi-Dimensional Networks
The most complicated steps
Assumed RC Values
Transient Thermal data
Network Identification
Transfer Function in Laplace Domain
Network Parameters Calculation
Measured Temperature Step Response Tm(t)
Simulated Temperature Step Response Ts(t)
Changed Network Parameter
Material Property Calculation
Compare Ts and Tm Good Calculated Network Parameter
Bad
Implementation in FLOTHEM
Material Property Calculation
This step is pretty straight-forward
Assume suitable dimensions for the network components Resistance Component Low Density and Specific heat (i.e Very low Capacitance) Thermal Conductivity (k) can be directly calculated Capacitance Component High Conductivity (i.e Low Resistance) Suitable Combination of Density and Specific Heat Need to consider numerical instability if this results in excessively high or low numbers Resistance and Capacitance may be lumped in a single block
Transient Thermal data
Network Identification
Network Parameters Calculation
Material Property Calculation
Implementation in FLOTHEM
Implementation in FLOTHERM
One-Dimensional Networks
Very simple Model blocks with appropriate dimensions and stack them to represent the network and Resistance
Transient Thermal data
Network Identification
Capacitance Resistance Capacitance Resistance Capacitance
Network Parameters Calculation
Material Property Calculation
Implementation in FLOTHEM
Multidimensional Networks
Complicated May not be possible to implement in FLOTHERM
Beyond FLOTHERM
In-house Network Analysis Tools
Reasonably simple algorithms Possible to combine Electrical-Thermal Networks Extension of the methods to Infra-Red Image processing Thermal diffusivity measurements Interaction between devices Excel based tools Expert interactions may still be necessary Resources in TCI People
Electrical Thermal Software ( Math-based, Tools etc..)
Tools
Matlab Mathcad MS Excel
Suggested Readings
Mathematics
Laplace Transforms Matrix Algebra Curve fitting methods Inverse Transforms Complex Numbers Numerical Methods
Network Synthesis
Passive Networks
Heat Transfer
Conduction Analytical methods Multidimensional Spreading Resistance Transients
