Edited by Chu Yu

Verilog HDL

Verilog Hardware Description Language

(Verilog HDL)

Edited by Chu Yu
http://ece.niu.edu.tw/~chu/

(2007/2/26)
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Verilog HDL

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Verilog HDL

Verilog HDL

Brief history of Verilog HDL

1985: Verilog language and related simulator Verilog-XL were
developed by Gateway Automation.
1989: Cadence Design System purchased Gateway Automation.
1990: Open Verilog International formed.
1995: IEEE standard 1364 adopted.

Features of Verilog HDL

Ability to mix different levels of abstract freely.
One language for all aspects of design, testing, and verification.

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Verilog HDL

Verilog HDL
z

HDL Hardware Description Language

A programming language that can describe the
functionality and timing of the hardware.

Why use an HDL?

It is becoming very difficult to design directly
on hardware.
It is easier and cheaper to different design
options.
Reduce time and cost.
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Verilog HDL

Programming
LanguageHDL
V.S. Verilog HDL
Verilog
Programming Language
if (a>b)
compiler
{

sub a, b
assembler

(C code)

(asm code)

Computer

(CPU)

Verilog HDL
if (a>b)
begin

end
(Verilog code)

I0
I1

synthesizer

In
a
b

out

a>b
(logic circuit)

(cell library)

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Verilog HDL

Verilog HDL
z

Verilog-XL is an event-driven simulator that can emulate

the hardware described by Verilog HDL.

Verilog-HDL allows you to describe the design at various

levels of abstractions within a design.
Behavioral Level
RTL Level
Gate Level
Switch Level

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Verilog HDL

Time Wheel in Event-Driven Simulation

Event queues at each time stamp

Et
An event Et at time t
Schedules another event
at time t + 2

t
t+1
t+2

z Time advances only when every event scheduled at that time

is executed.
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Verilog HDL

Different Levels of Abstraction

z

Architecture / Algorithmic (Behavior)

A model that implements a design algorithm in high-level
language construct.
A behavioral representation describes how a particular design
should responds to a given set of inputs.

Register Transfer Logic (RTL)

A model that describes the flow of data between registers and
how a design process these data.

Gate Level (Structure)

A model that describes the logic gates and the interconnections
between them.

Switch Level
A model that describes the transistors and the interconnections
between them.
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Verilog HDL

Three Levels of Verilog-HDL

Behavioral Level (RTL)

Switch Level
// AND gate of u2
pmos p0(VDD, nand, A),
p1(VDD, nand, B);
nmos n0(nand, wire1, A),
n1(wire1, GND, B);

assign {Co, Sum} = A + B + Ci

Gate Level
xor
xor
and
and
or

u0(.z(hs), .a1(A), .a2(B));

u1(.z(Sum), .a1(Ci), .a2(hs));
u2(.z(hc0), .a1(A), .a2(B));
u3(.z(hc1), .a1(Ci), .a2(hs));
u4(.z(Co), .a1(hc0), .a2(hc1));

pmos p2(VDD, hc0, nand);

nmos n2(hc0, GND, nand);
M

U0
U1

hs

A
B

Sum
U2
U3
1

U4
3

hc1

3
2

Co

hc0
Cin

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Verilog HDL

Top-Down Design Flow in ASIC

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Verilog HDL

Top Down ASIC Design Flow

Idea and Specification

Behavioral Modeling

sum = a + b;

Behavior Model
(Verilog HDL or C language)

Verification
(Verilog-XL)

Partitioning and Re-modeling

Logic Blocks with
Function Definition

always @( a or b or c)
{carry, sum} = a+b+c;

RTL Modeling
RTL Model
(Verilog HDL)

Verification
(Verilog-XL)

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Verilog HDL

Top Down ASIC Design Flow(Cont)

RTL Model
(Verilog HDL)

Logic Synthesis
(Synopsys)

xo03d1 u0(sum,a,b,c);
an02d1 u1(g2,a,b);

Gate Level Netlist

(Verilog HDL)

Verification
(Verilog-XL)

Physical Design
(CELL3 Ensemble)

ASIC Libraries
(Compass cell library)

GDS II
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Verilog HDL

Verilog-HDL Simulators
VCS (Synopsys)
Platform
Windows NT/XP, SUN Solaris (UNIX), Linux.
Modelsim (Mentor)
Platform
Windows NT/XP, SUN Solaris (UNIX), Linux.
NC-Verilog (Cadence)
Platform
Windows NT/XP, SUN Solaris (UNIX), Linux.
Verilog-XL (Cadence)
Platform
SUN Solaris (UNIX).

Other Simulators
MAX+PLUS II, Quartus II (Altera)
Active HDL (Aldec), Silos (Silvaco),
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Verilog HDL

Overview of Verilog Module

z A Verilog module includes the following parts:
module module_name (port_name);
port declaration
data type declaration
Task & function declaration
module functionality or declaration
timing specification
endmodule

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Verilog HDL

Example of Adder
z

A Full Adder
module name

module adder (carry, sum, a, b, cin);

output carry, sum;
I/O pins
input a, b, cin;
I/O pin declaration
wire
w0, w1, w2;

a
b
cin

sum

U0

a
b

U1

w0

xor u0(sum, a, b, cin);

and u1(w0, a, b);
and u2(w1, b, cin);
and u3(w2, cin, b);
or
u4(carry, w0, w1, w2)

cin

U2

w1

U4

carry

b
cin

U3

w2

endmodule
logic circuit description

build-in module invoked

instantiation

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Verilog HDL

Three Levels of Abstraction

z

A Full Adder
module adder (carry, sum, a, b, cin);
output carry, sum;
input a, b, cin;
reg
sum, carry;

module adder (carry, sum, a, b, cin);

output carry, sum;
input a, b, cin;
assign {carry, sum} = a + b + cin;
endmodule //RTL level

always @(a or b or cin)

{carry, sum} = a + b + cin;
endmodule //behavioral level
module adder (carry, sum, a, b, cin);
output carry, sum;
input a, b, cin;
wire w0, w1, w2;

a
b
cin
a
b

xor u0(sum, a, b, cin);

and u1(w0, a, b);
and u2(w1, b, cin);
and u3(w2, cin, b);
or
u4(carry, w0, w1, w2)
endmodule //gate level

sum

U0

U1

w0

a
cin

U2

w1

U4

carry

b
cin

U3

w2

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Verilog HDL

Identifiers of Verilog
z Identifiers are user-provided name for Verilog objects
within a description.
z Legal characters in identifiers:
a-z, A-Z, 0-9, _, $

z The first character of an identifier must be an

alphabetical character (a-z, A-Z) or an underscore (_).
z Identifiers can be up to 1024 characters long.
Example:
Mux_2_1
abc123
ABC123
Sel_
A$b$10
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Verilog HDL

Escaped Identifiers
z Escaped Identifiers start with a backslash (\) and end
with a white space.
z They can contain any printable ASCII characters.
z Backslash and white space are not part of the
identifiers.
Example:
module \2:1mux(out, a, b, sel);
not u0(\~out, in);

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Verilog HDL

Case Sensitivity
z Verilog is a case-sensitive language.
z You can run Verilog in case-insensitive mode by
specifying u command line option.
Example:
module inv(out, in);

endmodule

module Inv(out, in);

endmodule

// Both inv and Inv are viewed as two different modules.

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Verilog HDL

Verilog-HDL Structural Language

z

Verilog Module
Modules are basic building blocks in hierarchy.
Every module description starts with module
name(output_ports, input_ports), and ends with
endmodule.

Module Ports
Module ports are equivalent to the pins in hardware.
Declare ports to be input, output, or inout (bidirectional)
in the module description.

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Verilog HDL

Nets and Registers

z Nets: nets are continuously driven by the devices
that drive them.
wire, wor, wand, ...
- example : wire [7:0] w1,w2;
wire [0:7] w1;
- if wire is not vector type, then it doesnt need to
declaration.
z Registers: registers are used extensively in
behavioral modeling and in applying stimulus.
reg
- example: reg [3:0] variable;
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Verilog HDL

Registers
z More Examples
reg
mem1[127:0]; //128-bit memory with 1-bit wide
reg
mem2[63:0];
reg [7:0] mem3[127:0]; //128-bit memory with 8-bit wide
M
mem2=0; // illegal syntax
mem2[5] = mem1[125];
mem2[10:8] = mem1[120:118];
mem3[11]=0; //8-bit zero value

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Verilog HDL

Other Types of Nets

z Various net types are available for modeling designspecific and technology-specific functionality.
Net Types

Functionality

wire, tri
wand, triand
trireg
tri1
tri0
supply1
supply0

For multiple drivers that are Wired-OR

For multiple drivers that are Wired-AND
For nets with capacitive storeage
For nets with weak pull up device
For nets with weak pull down device
Power net
Ground net

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Verilog HDL

Example of Nets
z Example I

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Verilog HDL

Example of Nets
z Example II

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Verilog HDL

True Tables for tri, triand, and trior Nets

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Verilog HDL

Logic Level Modeling

z Built-in primitive functions
Gates

and
nand
nor
or
xor
xnor
not

buf
bufif0
bufif1
notif0
notif1
pullup
pulldown

MOS Switches
and Bidirectional
Transistors
nmos
pmos
cmos
rnmos
rpmos
rcmos

tran
tranif0
tranif1
rtran
rtranif0
rtranif1

Nets

wire
wand
wor
tri
triand
trior
trireg

supply0
supply1
trireg
tri1
tri0

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Verilog HDL

Switch Level Modeling

ctl
nMOS (unidirectional)

in

out

nmos(out, in, ctl);

out

pmos(out, in, ctl);

ctl
pMOS (unidirectional)

in
pctl

cMOS (unidirectional)

in

out

cmos(out, in, nctl, pctl);

nctl
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Verilog HDL

Operators Used in Verilog (Cont.)

z Verilog Language Operators

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Verilog HDL

Operators Used in Verilog (Cont.)

Precedence Rules for Operators

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Verilog HDL

Operators Used in Verilog (Cont.)

The Relational Operators Defined

The Equality Operators Defined

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Verilog HDL

Equality and Identity Operators

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Verilog HDL

Operators
Unary Operator
assign a = ~b;
Binary Operator
assign a = b&c;
Ternary Operator
assign out = sel ? a: b; //2-to-1 multiplexer

Comments
One Line Comment
// this is an example of one line comment
Multiple Line Comment
/* this is an example of
multiple line comment */
Error Comment Remarks
/* Error comment remark */ */
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Verilog HDL

Operators Used in Verilog

z Index:
example: a[11:6], b[2], ...

z Concatenation: {n{<exp> <, <exp>>*}}

adder4 a1(sum,carry,{a[2],a[2:0]},b[3:0]);
assign {carry, sum} = a+b+ci;
sign = {4{in[3]}, in};
temp = 2b01;
out = {2{2b10}, 2b11, temp}; //out=8b1010_1101

z Arithmetic operation: +,-,*

example: a=b+c;
x=y*z;

z Condition: = =, !=, >, <, >=, <=, ...

example: assign b = (a = = 0) ;
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Verilog HDL

Literal Numbers
z Literal integers are interpreted as decimal numbers in
the machine word size (32 bits) by default.
z Size and base my be explicitly specified
<size>'<base><value>
<size>: size in bits as a decimal number.
<base>: b(binary), o(octal), h(hex), d(decimal).
<value>: 0-9, a-f, x, z, ? (must be legal number in
<base>)
Four types of logic value
0 (logical 0), 1 (logical 1), x (unknown), z (high impedence)
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Verilog HDL

Literal Numbers (cont.)

z Examples

12
8'd45
10'hF1
1'B1
32'bz
6'b001_010

32-bit decimal
8-bit decimal
10-bit hex (left-extended with zero)
1-bit binary
32-bit Z
6-bit binary with underscore for readability.

Underscores are ignored.

X and Z values are automatically extended.
A question mark ? in <value> is interpreted as a Z.
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Verilog HDL

Block Statement
z Block statement are used to group two or more
statements together.
z Two Types of Blocks
Sequential Block
- Enclosed by keyword begin and end.
Parallel Block
- Enclosed by keyword fork and join.

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Verilog HDL

Procedural Timing Controls

z Three Types of Timing Controls

#<delay>
: Simple delay.
@(<signal>) : Event control with edge-trigger and level-sensitive controls.
wait(<expr>) : Level-sensitive control.

z Edge-Trigger Control
posedge: positive edge. EX: always @(posedge clk)
negedge: negative edge. EX: always @(negedge clk)

z Examples
always @(posedge clk)
begin
#5 q=d;
#1 qb=~d;
end

posedge clk?
y

#5 q=d
#1 qb=~d

q
qb

t=0

d
~d

t=5 t=6

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Verilog HDL

Procedural Timing Controls

z Examples
read=0
en1=1 or en2=1?

read

initial
begin
read=0;
wait(en1|en2) read=1;
#5 read=0;
end

t=0

read=1

t=n t=n+5

#5 read=0

set

negedge clk?

clk
q

set=1?

always wait(set)
begin
@(negedge clk);
#3 q=1;
#1 q=0;
wait(!set);
end

t=0
#3 q=1
#1 q=0
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t=n t=n+3 t=n+4

n
set=1?

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Verilog HDL

Syntax of Verilog
z C-like structural language

statement: begin ... end, if ... else, and so on.

free writing format: statement ended with ;.
remark: between /* */ or // until the line feed.
hierarchical modules.

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Verilog HDL

High-level Programming Language Constructs

z Looping Controls
while loop

forever loop

example

example

while(val[index]==1'b0)

forever #100 clk=~clk;

always #100 clk=~clk;

index=index-1;

repeat loop

for loop

example

example

repeat(mem_depth)
begin
mem[address]=0;
address=address+1;
end

for(index=0;index<size;
index=index+1)
if(val[index]==1'bx)
$display(''found an x'');

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Verilog HDL

High-Level Programming Language Constructs

z Decision-making controls
if statement
example
if (set = = 1) out = 1;
if (clear = = 0) q = 0;
else
q = d;
case statement
example
case(instruction)
2'b00: out = a + b;
2'b01: out = a - b;
default: out=0;
endcase
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Verilog HDL

Continuous Assignment
z Continuous assignment provide a means to abstractly
model combinational hardware driving values onto nets.
An alternate version of the 1-bit full adder is shown blow:
module FA(Cout, Sum, a, b, Cin);
output Cout, Sum;
input
a, b, Cin;
assign Sum = a ^ b ^ Cin,
Cout = (a & b) | (b & Cin) | (a & Cin);
endmodule

z Logic loop of Continuous Assignment

assign a = b+a;

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Verilog HDL

Procedural Assignments
z Assignments made within procedural blocks are known as
procedural assignments.
z The left-hand side of procedural assignment must be a
data type in the register class.
Example
initial
begin
out=0;
#10 en1=~net23;
#5 set=(r1|en1)&net4;
end
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Verilog HDL

Intra-Assignment Timing Control

z Previously described timing control.
#100 clk = ~ clk;
@(posedge clock) q = d;

z Intra-assignment timing control.

clk = #100 ~ clk;
q = @(posedge clock) d;

z Simulators perform two steps when encounter an intra

assignment timing control statement.
Evaluate the RHS immediately.
Execute the assignment after a proper delay.

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Verilog HDL

Intra-Assignment Timing Control

z Intra-assignment timing control can be accomplished by using the
following constructs
With intra-assignment construct

With intra-assignment construct

begin
temp = b;
#10 a = temp;
end

a = #10 b;

begin
temp = b;
@ (posedge clk) a = temp;
end

a = @(posedge clk) b;

begin
temp = b;
@ (posedge clk)
@ (posedge clk)
@ (posedge clk) a = temp;
end

a = repeat(3)@(posedge clk) b;

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Verilog HDL

Non-Blocking Procedural Assignment

z Blocking procedural assignment.
rega = #100 regb;
rega = @(posedge clk) regb;

z Non-Blocking procedural assignment.

rega <= #100 regb;
rega <= @(posedge clk) regb;

z Schedule the assignment without blocking the

procedural flow.
z Simulators perform two steps when encounter an nonblocking procedural assignment statement.
Evaluate the RHS immediately.
Schedule the assignment at a proper time.
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Verilog HDL

Blocking Procedural Assignment

initail begin
a = #10 1;
$display(current time = %t a = %b, $time, a);
end
Evaluate RHS (RHS = 1)

evaluate at time = 10, a = 1

t=0
t=1

event queues at each time stamp

Current
Simulation
Time

M
$display() assign logic 1 to a

t = 10
t = 11

t=0

t=10
$display a
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Verilog HDL

Non-Blocking Procedural Assignment

initail begin
a <= #10 1;
$display(current time = %t a = %b, $time, a);
end
$display() Evaluate RHS (RHS = 1)

evaluate at time = 0, a = x

t=0
t=1

event queues at each time stamp

Current
Simulation
Time

M
assign logic 1 to a
a

t=0
$display a

t = 10
t = 11

t=10
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Verilog HDL

Hierarchical Design
z Top-Down Design Methodology
module CPA4b(Cout, Sum, a,b,Cin);
output
Cout;
output [3:0] Sum;
input [3:0] a,b;
input
Cin;
wire [2:0] c;
adder
fa0(c[0], Sum[0], a[0], b[0], Cin); //by position mapping
adder
fa1(.a(a[1]), .b(b[1]), .cin(c[0]), .carry(c[1]), .sum(Sum[1])); //by name mapping
adder
fa2(c[2], Sum[2], a[2], b[2], c[1]);
adder
fa3(Cout, Sum[3], a[3], b[3], c[2]);
4-bit
endmodule
adder
module adder (carry, sum, a, b, cin);
output carry, sum;
input a, b, cin;
1-bit
1-bit
1-bit
1-bit
assign {carry, sum} = a + b + cin;
adder
adder
adder
adder
endmodule
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Verilog HDL

Delay Specification in Primitives

z Delay specification defines the propagation delay of that
primitive gate.

not #10 u0(out, in);

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Verilog HDL

Delay Specification in Primitives

z Support (rise, fall, turn-off) delay specification.

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Verilog HDL

Delay and Time Scales

z Delays
Gate Description
buf #<delay> buf0(X,A);
where <delay> is:
<delay time> or
(<minimum delay>:<typical delay>:<maximum delay>)
example: buf #(3:4:5) buf0(X,A);

or #1 u0(out, in0, in1);

Modeling Seperate Rise and Fall Delays

not #<delay> not0(X,A);
where <delay> is
(<rise dealy>,<fall delay>)
example: not #(2.23:2.33:2.66,3.33:3.47:3.9) not0(X,A);
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Verilog HDL

Delay and Time Scales (cont.)

Three-state drivers: include rise, fall, and turn off delays
example: bufif1 #(2.2:2.3:2.6, 3.3:3.4:3.9, 0.2:0.2:0.2) u0(out, in);
z Timescales
The `timescale compiler directive can be used to specify delays in
explicit time units.
Syntax of the `timescale compiler directive:
`timescale <unit>/<precision>
example: `timescale 1ns/10ps
then the design will be simulated in units of 10 ps.
example:

not #(2.337,3.472) not1(X, A); 2.337ns will be scaled

to 2.34 ten pico-second units for simulation purposes.
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Verilog HDL

Delay and Time Scales (cont.)

z The smallest precision of all the timescale determines the
time unit of simulation.
`timescale 1ns/10ps
module m1();

0 ps
1 ps

`timescale 100ns/1ns
module m2();

2 ps
3 ps

`timescale 1ps/1ps
module m3();

4 ps

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Verilog HDL

Compiler Directives
z All Verilog compiler directives are preceded by the
accent sign (`).
z Compiler directives remain active until they are
overridden or deactivated.
z The `resetall compiler directive resets all the compiler
directives to their default values (only if there is a
default value).
Example:
`define s0 2b00
`include lib.v
`timescale 10ns/100ps
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Verilog HDL

Compiler Directives
z The `define compiler directive provides a simple textsubstitution facility.
Syntax: define <macro_name> <text_string>
<text_string> will substitute <macro_name> at compile time.

z Typically use define to make the description more

readable.
Example:
`define false 0

assign a = false ; ==> assign a = 0;

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Verilog HDL

Compiler Directives
z Use `include compiler directive to insert the contents
of an entire file.
`include lib.v
`include dir/lib.v

z You can use include to

include global or common definitions.
include tasks without encapsulating repeated code within
module boundaries.

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Verilog HDL

Parameters
z Parameters are constants rather than variables.
z Typically parameters are used to specify delays and
width of variable.
Example:
module varmux(out, I0, I1, sel);
parameter width=2, delay=1;
output [width-1:0] out;
input [width-1:0] I0, I1;
input sel;
assign #delay out=sel? I1:I0;
endmodule
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Verilog HDL

Overriding the Value of Parameters

z Use defparam and hierarchical name of
parameter to change the value of parameter.

that

Example:
module top;

varmux u0(out0, a0, a1, sel);

varmux u1(out1, a2, a3, sel);
defparam u1.width=4, u1.delay=2;

endmodule

Top.u0.width=2
Top.u0.delay=1
Top.u1.width=4
Top.u1.delay=2

<##>
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Verilog HDL

System Tasks and Functions

z $<identifier>
Sign$ denotes Verilog system tasks and functions.
A number of system tasks and functions are available to
perform different operations such as
- Finding the current simulation time ($time).
- Displaying/monitoring the values of signals ($display,
$monitor).
- Stopping the simulation ($stop).
- Finishing the simulatioon ($finish).

z For more information on system tasks and functions,

see the module Support for Verification.
<##>
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Verilog HDL

Examples of Verilog-HDL
z 2-to-1 Multiplexer
module mux(out, I0, I1, sel);
output [3:0] out;
input [3:0] I0, I1;
input sel;
reg
[3:0] out;

I0
I1

always @(I0 or I1 or sel)

if (sel==1b1) out=I1;
else out=I0;
endmodule

0
4

Out

sel

//The output value will be changed when one of I0, I1, and sel input signals is
changing.
<##>
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Verilog HDL

Example of Verilog-HDL
z 2-to-1 Multiplexer
module mux(out, I0, I1, sel);
output [3:0] out;
input [3:0] I0, I1;
input sel;

I0
I1

assign out=sel?I1:I0;

0
4

Out

sel

endmodule

<##>
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Verilog HDL

Example of Verilog-HDL
z 4-to-1 Multiplexer
module mux(out, I3, I2, I1, I0, sel);
output [3:0] out;
input [3:0] I3, I2, I1, I0;
input [1:0] sel;
reg
[3:0] out;
always @(I3 or I2 or I1 or I0 or sel)
case (sel)
2b00: out=I0;
2b01: out=I1;
2b10: out=I2;
2b11: out=I3;
default: out=4bx;
endcase
endmodule

I0
I1
I2
I3
sel

0
4

1
4

Out

2
4

<##>
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Verilog HDL

Example of Verilog-HDL
z 4-to-1 Multiplexer
module mux(out, I3, I2, I1, I0, sel);
output [3:0] out;
input [3:0] I3, I2, I1, I0;
input [1:0] sel;
assign out = (sel==2b00)?I0:
(sel==2b01)?I1:
(sel==2b10)?I2:
(sel==2b11)?I3:
4bx;
endmodule

I0
I1
I2
I3
sel

0
4

1
4

Out

2
4

<##>
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Verilog HDL

Example of Verilog-HDL
z 3-to-1 Multiplexer
module mux(out, I3, I1, I0, sel);
output [3:0] out;
input [3:0] I3, I1, I0;
input [1:0] sel;
reg
[3:0] out;
always @(I3 or I1 or I0 or sel)
case (sel) //synopsys full_case -> If condition 2b10 is impossible
to appear.
2b00: out=I0;
2b01: out=I1;
2b11: out=I3;
endcase
endmodule // Require latches to synthesis the priority encoder circuit
if the remark synopsys full_case is not assigned.
<##>
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Verilog HDL

Example of Verilog-HDL
z Compound Logic
module complogic1(F, x, y, z);
output F;
input x, y, z;
assign F = (x&~y)|(y|z);
endmodule
module complogic2(F, x, y, z);
output F;
input x, y, z;

x
y
z

yp

xy

F
yz

not u1(yp, y);

and u2(xy, x, yp);
or u3(yz, y, z);
or u4(F, xy, yz);
endmodule

<##>
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Verilog HDL

Example of Verilog-HDL
z casex I
module top(R1, R2, R3, I2, I1, I0);
output R1, R2, R3;
input I2, I1, I0;
reg
R1, R2, R3;
always @(I2 or I1 or I0)
casex ({I2, I1, I0})
3b1??: {R1, R2, R3}=3b100;
3b?1?: {R1, R2, R3}=3b010;
3b??1: {R1, R2, R3}=3b001;
endcase
endmodule

// ? = {0, 1}
// ? != {x, z}

<##>
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Verilog HDL

Example of Verilog-HDL
z casex II
module top(R1, R2, R3, I2, I1, I0);
output R1, R2, R3;
input I2, I1, I0;
reg
R1, R2, R3;
always @(I2 or I1 or I0)
casex (1b1)
I0: {R1, R2, R3}=3b100;
I1: {R1, R2, R3}=3b010;
I2: {R1, R2, R3}=3b001;
endcase
endmodule

<##>
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Verilog HDL

Example of Verilog-HDL
z casez
module top(R1, R2, R3, I2, I1, I0);
output R1, R2, R3;
input I3, I1, I0;
reg
R1, R2, R3;
always @(I2 or I1 or I0)
casez ({I2, I1, I0})
3b1??: {R1, R2, R3}=3b100;
3b?1?: {R1, R2, R3}=3b010;
3b??1: {R1, R2, R3}=3b001;
endcase
endmodule

// ? = {0, 1, x, z}

<##>
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Verilog HDL

Example of Verilog-HDL
z Comparator
module comparator(large, equal, less, a, b);
output
large, equal, less;
input [3:0] a, b;
assign large = (a > b);
assign equal = (a == b);
assign less = (a < b);
endmodule

<##>
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Verilog HDL

Hierarchical Modules
z 4-bit carry-propagate adder
module CPA(Cout, Sum, a,b,Cin);
output
Cout;
output [3:0] Sum;
input [3:0] a,b;
input
Cin;
wire [2:0] c;
adder
fa0(c[0],Sum[0],a[0],b[0],Cin);
adder
fa1(c[1],Sum[1],a[1],b[1],c[0]);
adder
fa2(c[2],Sum[2],a[2],b[2],c[1]);
adder
fa3(Cout,Sum[3],a[3],b[3],c[2]);

module adder (carry, sum, a, b, cin);

output [3:0] carry, sum;
input [3:0] a, b;
input
cin;
assign {carry, sum} = a + b + cin;
endmodule

a[3] b[3] a[2] b[2] a[1] b[1] a[0] b[0]

endmodule

fa3

module adder (carry, sum, a, b, cin);

output carry, sum;
input a, b, cin;
assign {carry, sum} = a + b + cin;
endmodule

Cout

Full
Adder

fa2
Full
Adder

fa1
Full
Adder

fa0
Full
Adder

Cin

Sum[3] Sum[2] Sum[1] Sum[0]

<##>
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Verilog HDL

Example of Verilog-HDL
z Resource Sharing
module top1(out, a, b, c, sel);
output [4:0] out;
input [3:0] a, b, c;
input
sel;
reg
[4:0] out;

module top2(out, a, b, c, sel);

output [4:0] out;
input [3:0] a, b, c;
input
sel;
reg
[4:0] out;

always @ (a or b or c or sel)
if (sel) out=a+b;
else out=a-c;

always @ (a or b or c or sel)
if (sel) out=a+b;
else out=a+c;

endmodule //cant be shared

endmodule //can be shared

<##>
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Verilog HDL

Example of Verilog-HDL
z 1-bit latch
module Latch(q, d, rst, enable);
output q;
input d, enable, rst;

d
Latch

assign q=(rst==0)?0:
(enable==1)?d:q;

enable
rst

endmodule

<##>
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Verilog HDL

Example of Verilog-HDL
z 1-bit register with a synchronous reset
module D_FF(q, d, clk, load, rst);
output q;
input d, clk, load, rst;
reg
q;
always @(posedge clk)
if (rst==1b0) q=0;
else if (load==1b1) q=d;

d
clk

DFF

load
rst

endmodule

<##>
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Verilog HDL

Example of Verilog-HDL
z 1-bit register with a asynchronous reset
module D_FF(q, d, clk, load, rst);
output q;
input d, clk, load, rst;
reg
q;
always @(posedge clk or negedge rst)
if (rst==1b0) q=0;
else if (load==1b1) q=d;

d
clk

DFF

load
rst

endmodule

<##>
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Verilog HDL

Example of Verilog-HDL
z 4-bit up counter with load and enable signals
module counter(q, in, load, enable, rst, clk);
output [3:0] q;
input [3:0] in;
in
input
clk, load, rst, enable;
clk
reg [3:0] q;
enable
always @(posedge clk or negedge rst)
load
if (rst==1b0) q=0;
rst
else if (load==1b1) q=in;
else if (enable==1b1) q=q+1;

4-bit
counter

endmodule
<##>
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Verilog HDL

Example of Verilog-HDL
z Register with Combination Logic
module DFFE(Out, A, B, CLR, CLK);
output Out;
input A, B, CLR, CLK;
reg
Out;
always @(posedge CLK or negedge CLR)
if (CLR==1b0) Out=0;
else Out=(A&Out)|B;

A
B
CLK

Out

clr

CLR

endmodule

<##>
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Verilog HDL

z Mealy Machine (Finite State Machine)

module mealy(out, in, rst, clk);
output
out;
0/0
0/0
In/Out
input
in;
input
clk, rst;
s0
s1
s2
s3
1/0
reg
out;
0/0
0/0
1/0
reg
[1:0] state;
1/1
parameter s0=2d0, s1=2d1, s2=2d2, s3=2d3;
1/0
always @(posedge clk or negedge rst)
if (rst==0) begin state=s0; out=0; end
else begin
case (state)
s0: if (in==0) begin out=0; state=s1; end
else
begin out=0; state=s0; end
s1: if (in==0) begin out=0; state=s1; end
else
begin out=0; state=s2; end
s2: if (in==0) begin out=0; state=s3; end
else
begin out=0; state=s0; end
s3: if (in==0) begin out=0; state=s1; end
else
begin out=1; state=s2; end
default: state=s0;
endcase
end
endmodule

<##>
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Verilog HDL

z Moore Machine
0
0
module moore(out, in, rst, clk);
output
out;
s1/0
s2/0
s3/1
1 s0/0
input
in;
0
1
0
input
clk, rst;
reg
out;
1
1
reg
[1:0] state;
parameter s0=2d0, s1=2d1, s2=2d2, s3=2d3;
always @(posedge clk or negedge rst)
if (rst==0) begin state=s0; out=0; end
else begin
case (state)
s0: begin out=0; if (in==0) state=s1; else state=s0; end
s1: begin out=0; if (in==0) state=s1; else state=s2; end
s2: begin out=0; if (in==0) state=s3; else state=s0; end
s3: begin out=1; if (in==0) state=s1; else state=s2; end
default: state=s0;
endcase
end
endmodule
<##>
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Verilog HDL

z RAM
module RAM(out, in, addr, RW, CS);
output [7:0] out;
input [7:0] in;
input [3:0] addr;
input
RW,CS;
reg
[7:0] out;
reg
[7:0] DATA[15:0];

in
addr

out
RAM

RW
CS

always @(negedge CS)

begin
if (RW==1'b0) //READ
out=DATA[addr];
else
if (RW==1'b1) //WRITE
DATA[addr]=in;
else
out=8'bz;
end
endmodule
<##>

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Verilog HDL

z ROM
module ROM_Qe(out, addr, CS);
output [15:0] out;
input [3:0] addr;
input
CS;
reg
[15:0] out;
reg
[15:0] ROM[15:0];

addr

out
RAM

always @(negedge CS)

begin
ROM[0]=16'h5601; ROM[1]=16'h3401;
ROM[2]=16'h1801; ROM[3]=16'h0ac1;
ROM[4]=16'h0521; ROM[5]=16'h0221;
ROM[6]=16'h5601; ROM[7]=16'h5401;
ROM[8]=16'h4801; ROM[9]=16'h3801;
ROM[10]=16'h3001; ROM[11]=16'h2401;
ROM[12]=16'h1c01; ROM[13]=16'h1601;
ROM[14]=16'h5601; ROM[15]=16'h5401;
out=ROM[addr];
end
endmodule

CS

<##>
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Verilog HDL

z I/O read/write
reg clk, rst, start;
reg buffer[255:0];

reg
clk, rst;
integer f2;
parameter D=10;

M
initial
begin
clk=0; rst=0; start=0;
$readmemb("c:/temp/in.dat",buffer);
#10 rst=1;
#30 start=1;
M
end

initial
begin
clk=0;rst=0;
#D #D #D rst=1;
f2=$fopen(c:/lss.dat");
$fdisplay(f2,"%d", out);
$fclose(f2);
$stop; $finish;
end
endmodule

<##>
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Verilog HDL

User Defined Primitives

z UDPs permit the user to augment the set of predefined primitive elements.
z Use of UDPs may reduce the amount of memory
required for simulation.
z Both level-sensitive and edge-sensitive behavior is
supported.

<##>
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Verilog HDL

UDP Table Symbols

Comments

symbol

Interpretation

0
1
x
?
b
(vw)
*
r
f
p
n

Logic 0
Logic 1
Unknown
Iteration of 0, 1, and x
Iterayion of 0 and 1
No change
Change of value from v to w
Same as (??)
Same as (01)
Same as (10)
Iteration of (01), (0x), and (x1)
Iteration of (10), (1x), and (x0)

input field
input field
output field
Any value change on input
Rising edge on input
Falling edge on input
Positive edge including x
Negative edge including x

<##>
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Verilog HDL

UDP Definition
z Pure combinational Logic
primitive mux(o,a,b,s);
output o;
input a,b,s;
table
// a b s : o
0 ? 1 : 0;
1 ? 1 : 1;
? 0 0 : 0;
? 1 0 : 1;
0 0 x : 0;
1 1 x : 1;
endtable
endprimitive

The output port must be the first port.

UDP definitions occur outside of a module
All UDP ports must be declared as scalar
inputs or outputs. UDP ports cannot be
inout.
Table columns are inputs in order
declared in primitive statement-colon,
output, followed by a semicolon.
Any combination of inputs which is not
specified in the table will produce an 'x' at
the output.

<##>
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Verilog HDL

UDP Definition (cont.)

z Level-sensitive Sequential Behavior
primitive latch(q,clock,data);
output q;
reg q;
input clock,data;
table
// clock data : state_output : next_state
0
1 :
?
:
1;
0
0 :
?
:
0;
1
? :
?
:
-;
endtable
endprimitive

The '?' is used to represent don't

care condition in either inputs or
current state.
The '-' in the output field indicates
'no change'.

<##>
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Verilog HDL

UDP Definition (cont.)

z Edge-sensitive Sequential Behavior
primitive d_edge_ff(q,clock,data);
output q;
reg q;
input clock,data;
table
// obtain output on rising edge of clock
// clock data state next
(01)
0 : ? : 0;
(01)
1 : ? : 1;
(0x)
1 : 1 : 1;
(0x)
0 : 0 : 0;

// ignore negative edge of clock

(?0)
? : ? : -;
// ignore data changes on steady clock
? (??) : ? : -;
endtable
endprimitive
Note that the table now has
edgeterms representing transitions on
inputs.

<##>
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Verilog HDL

Logic Strength Modeling

z Verilog provides multiple levels of logic strengths for
accurate modeling of signal contention.
z Logic strength modeling resolves combinations of
signals into known or unknown values to represent the
behavior of the hardware with maximum accuracy.

<##>
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Verilog HDL

Logic Strength Modeling

z Adding logic strength properties to Verilog primitive.

<##>
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Verilog HDL

Logic Strength Modeling

z Signal Strength Value System.

<##>
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Verilog HDL

Logic Strength Modeling

z If two values of unequal strength combines in a wired
net configuration, the stronger signal is the result.
Example:
Pull
Strong0
Strong0
Supply1
Supply1
Large1

<##>
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Verilog HDL

Logic Strength Modeling

z Syntax
<GATETYPE><drive_strength>?<delay><gate_instance>;
where <drive_strength> may be (<strength0>, <strength1>) or
(<strength1>, <strength0>)

z Example
not (weak1, strong0) u0(Y, A);
not (strong0, strong1) u1(Y, A);

z You can use %v format specificity to display the

strength of a net.
$monitor(at time=%t, the strength of Y is %v, $time, Y);
<##>
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Verilog HDL

Specify Blocks
z What is a specify block?
Specify block let us add timing specifications to
paths across a module.
a
b
cin

Full Adder

sum
carry

Tlh_b_to_Sum = 1.5
Thl_b_to_Sum = 2.2

Tlh_a_to_Sum = 1.2
Thl_a_to_Sum = 2.0

<##>

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Verilog HDL

Example of Specify Blocks

module DFF (q, d, clk);
input d, clk;
output q;
reg
notifier;

q
DFF

clk
UDP_DFF

u0(q, d, clk notifier);

specify
specparam
InCap$d = 0.024, Tsetup$d_cp = 0.41, Thold$d_cp = 0.2;

(clk => q) = (0.390, 0.390);

$setup(d, posedge clk, Tsetup$d_cp, notifier);

perform timing check
$hold(posedge clk, d, Thold$d_cp, notifier);

endspecify
endmodule

<##>
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Verilog HDL

Starting the Verilog-XL Simulation

UNIX Environment
verolog <command_line_options> <design file>
Example 1:
unix> verilog adder.v
Example 2:
unix> verilog file1.v file2.v file3.v
or
unix> verilog f file4
file4 content in the text mode:
file1.v
file2.v
file3.v
<##>
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Verilog HDL

Testing and Verification of Full Adder

Test Fixture
Stimulus
and
Control

a
b
cin

Full Adder

sum
carry

Response
Generation
and
Verification

z Test the full adders Verilog model by applying test patterns and
observing its output responses.
Stimulus and control: Changes on device inputs, simulation finish
time, ... etc.
Device under test: Behavior, gate, or switch level modules.
Response generation and verification: Which signals to
save/display, verification of generated response.
<##>
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Verilog HDL
Circuit Description
module add4(sum, carry, A, B, Cin);
output [3:0] sum;

endmodule

Testfixture
module testfixture;
reg [3:0] A, B;

endmodule

Verilog Simulation
Verilog Parser
Simulation Engine

User Interface

0.00 ns in = 0 out = x
16.00 ns in = 0 out = 1
100.00 ns in = 1 out = 1

<##>
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Verilog HDL

Example with a Test Fixture

z

A Full Adder
module adder (carry, sum, a, b, cin);
output carry, sum;
input a, b, cin;
wire w0, w1, w2;

module testfixture;
reg a, b, cin;
wire sum, carry;
adder u0 (carry, sum, a, b, cin);

xor u0(sum, a, b, cin);

and u1(w0, a, b);
and u2(w1, b, cin);
and u3(w2, cin, b);
or
u4(carry, w0, w1, w2)
endmodule

initial begin
$monitor($time, a=%b b=%b
cin=%b sum=%b carry=%b,
a, b, cin, sum, carry);
a=0; b=0; cin=0;
#10 a=0; b=0; cin=1;
#10 a=0; b=1; cin=0;
#10 a=0; b=1; cin=1;
#10 a=1; b=0; cin=0;
#10 a=1; b=0; cin=1;
#10 a=1; b=1; cin=0;
#10 a=1; b=1; cin=1;
#10 $stop; #10 $finish;
end
endmodule

This will generate some text outputs as

0 a=0 b=0 c=0 sum=0 carry=0
10 a=0 b=0 c=1 sum=1 carry=0

<##>
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Verilog HDL

Useful System Tasks

z Always and Initial
always
initial
$stop: Stopping the simulation.
$finish: Finishing the simulation.

z Monitoring Commands
Text Format Output
$monitor($time,''a=%d, b=%b,...\n'',a,b);
Graphic Output
$gr_waves(''<signal_label>'',<signal>, ...);
$SimWave: $shm_open(<file_name>), $shm_probe( )
<##>
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Verilog HDL

Monitor System Task

z Any expression parameter that has no corresponding format
specification is displayed using the default decimal format.
%h or %H

display in hexadecimal format

%d or %D

display in decimal format

%o or %O

display in octal format

%b or %B

display in binary format

%c or %C

display in ASCII character format

%v or %V

display net signal strength

%n or %N

display net normalized voltage in Switch-RC

%m or %M

display hierarchical name

%s or %S

display as a string

%t or %T

display in current time format

<##>
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Verilog HDL

SimWave
z Using system tasks to save the circuit state into
waveform database.
z You can use SimWave to view the signal waveforms
after Verilog-XL simulation.
z Example
module testfixture;

initial begin
$shm_open(adder.shm);
$shm_probe(A);

#10 $finish; end

endmodule
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Verilog HDL

SimWave Window

<##>
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Verilog HDL

Trouble Shooting
z If a=b is triggered by some event, a must be declared as
reg.
z A bus signal must be declared as wire.
z The negative value should be sign-extended.
z The port size and number of a module should match
anywhere it is referred.

<##>
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