1) Count 1’s in given vector verilog code
module num_ones_for(
input [15:0] A,
output reg [4:0] ones
);
integer i;
always@(A)
begin
ones = 0; //initialize count variable.
for(i=0;i<16;i=i+1) //for all the bits.
ones = ones + A[i]; //Add the bit to the count.
end
endmodule
2) Verilog edge detection
Module posedge(inp,temp,outp)
Input inp;
Input clk;
Output outp;
reg temp;
always@(pos edge(clk))
temp <=input;
End
assign outp = input & (~temp);
Endmodule
3) Generic multiplexer
// Example 6d: Generic 2-to-1 MUX using a parameter
module mux2g
#(parameter N = 4)
(input wire [N-1:0] a,
input wire [N-1:0] b,
input wire s,
output reg [N-1:0] y
);
always @(*)
if(s == 0)
y = a;
else
y = b;
endmodule
4) Double flop sychronizer
Module double flop
Input d,clk;
Output q;
always@(posedge(clk))
begin
R1<= d;
R2<=R1;
Q<=R2;
End
Endmodule
5) Clock divider verilog code
For even number:
/**********Clock Divider************/
/*Implemented function:
out_clk(freq) = in_clk / 2n.
Width = N square root and carry in.*/
module clk_divider_n (
input in_clk,
input rst_n,
output out_clk
);
parameter WIDTH = 2;
parameter N = 3;
reg [WIDTH-1:0] cnt;
reg clk_p;
assign out_clk = clk_p;
always@(posedge in_clk or negedge rst_n) begin
if (!rst_n)begin
cnt <= 0;
clk_p <= 1'b0;
end
else if (cnt == N)
begin
clk_p <= ~clk_p;
cnt <= 0;
end
else
cnt <= cnt + 1'b1;
end
endmodule
For odd number:
module clk_div3(clk,reset, clk_out);
input clk;
input reset;
output clk_out;
reg [1:0] pos_count, neg_count;
wire [1:0] r_nxt;
always @(posedge clk)
if (reset)
pos_count <=0;
else if (pos_count ==2) pos_count <= 0;
else pos_count<= pos_count +1;
always @(negedge clk)
if (reset)
neg_count <=0;
else if (neg_count ==2) neg_count <= 0;
else neg_count<= neg_count +1;
assign clk_out = ((pos_count == 2) | (neg_count == 2));
endmodule
6) Verilog code for calculating the even parity
function parity;
input [31:0] data;
integer i;
begin parity = 0;
for (i= 0; i < 32; i = i + 1) begin
parity = parity ^ data[i];
end
end
endfunction
7) Gray counter
https://www.electronicsforu.com/technology-trends/latch-not-bad-latch-vs-flip-flop
8) SIPO & PISO verilog code
module Fast_comm_ser_des (
// inputs:
input clk45_i,
input uC_reset,
input [63:0] send_data,
input IN_FASTCOM1_RXD,
output reg OUT_FASTCOM1_TXD,
output [63:0] recv_data_1
);
// pll150 fastComPll
(
// .refclk(clk45_i),
// .rst(uC_reset),
// .outclk_0(clk_900Mhz),
// .outclk_1(clk_150en),
// .outclk_2(clk_150Mhz),
// .locked(pll_lock)
);
// parallel to serial conversion
always @ (posedge clk_150Mhz or negedge reset_n)
begin
OUT_FASTCOM1_TXD = shifter[63];
shifter <= send_data;
shifter <= {shifter[62:0],1'b0};
end
//serial to parallel conversion
reg [63:0] shift_reg;
always @(posedge clk_150Mhz or negedge reset_n)
begin
shift_reg <= {shift_reg[62 : 0], IN_FASTCOM1_RXD};
end
assign recv_data_1 = shift_reg;
Endmodule
9) Pulse streacher code
module Top(
input RESET,
input CLOCK,
input TRIGGER_P,
input TRIGGER_N,
output OUTPUT_PULSE_P,
output OUTPUT_PULSE_N
);
reg [2:0] counter;
reg async_reset;
reg output_pulse_se;
wire trigger_s;
// async edge latch
always @(posedge trigger_s or posedge async_reset)
begin
if(async_reset == 1) begin
output_pulse_se <= 0;
end else begin
output_pulse_se <= 1;
end
end
// One shot counter
always @(posedge CLOCK)
begin
if(RESET == 1) begin
counter <= 3'd0;
async_reset <= 0;
end else begin
if(output_pulse_se == 1) begin
if(counter < 3'd7) begin
counter <= counter + 1;
end else begin
counter <= 0;
async_reset <= 1;
end
end else begin
async_reset <= 0;
end
end
end
// Instantiate IBUFGDS
IBUFGDS IBUFGDS_clk(
.O(trigger_s),
.I(TRIGGER_P),
.IB(TRIGGER_N)
);
// Instantite OBUFDS
OBUFDS OBUFDS_i(
.I(output_pulse_se),
.O(OUTPUT_PULSE_P),
.OB(OUTPUT_PULSE_N)
);
endmodule
always@ ( b )
always @( posedge clk )begin begin
a <= b; a = b;
b <= a;end b = a;
/* end
Value of a and b will be /*
swapped.Commonly used in Value of b will be copied to
sequential logics both a and b. Commonly used in
*/ combinational logic
*/
