assertions
// to check the frequency is working at 10mhz
property check_clk;
realtime current_time;
realtime difference;
@(posedge clk)(1,current_time=$realtime)|=> (1, difference = $realtime-current_time)
difference == 10ns;
endproperty
//(1,current_time = $realtime) // store the time in current_time at 1st change
//(1, difference == $realtime-prev_time) // store the difference in difference
//difference value after one clk cycle has to be 10ns
check_period_10: assert property(@posedge (clk) p_check);
//A connectivity checker which can be used to increase toggle coverage)
`define CONNECTIVITY_CHECK (x) \
#100ns; \
force ``x = 1; \
#200ns; \
release ``x; \
#200ns; \
force ``x = 0; \
#200ns; \
release ``x; \
#400ns;
`CONNECTIVITY_CHECK(tb.dut.a);
//a is asserted high on each clock cycle and after 2 clk cycles b has to be asserted
high
property asserthigh
@(posedge clk) a ##2 b;
endproperty
asserthigh: assert property(asserthigh)
//a has to be asserted high in the same clk cycle b has to be asserted as well
property assertoverlap
@(posedge clk) a |-> b;
endproperty
assertoverlap: assert property assertoverlap
// a has to be asserted high on the next clk cycle b has to be asserted
property nonoverlap;
@(posedge clk) a |=> b;
endproperty
nonoverlap: assert property (nonoverlap);
a |-> $rose(b) // a is high in same cycle it detects positive edge on b
a |=> b[*6] ##1 c// consecutive repetition operator
a |-> b[|->6] ##1 c// goto repetition operator (not consecutive)
a |-> b[=3] ##1 c // non consecutive repitition operator
$onehot(a) //checks number of ones to be one in a
$onehot(~a) //checks number of zeros to be one in a
assert $rose(a) |=> (b throughout (!c[->1])); //b has to e=be high continuously until c
goes low
$rose(a) |=> (b until !c) //until
$rose(a) |=> (b until_with !c) //until_with
sequence1 within sequence2
-------------
axi assertions examples
- ARESETn and valid signals
- Valid has to be high next clock cycle when ARESETn is high
(@(posedge ACLK) ARESETn |=> VALID);
- Reset signal can be asserted asynchronously,
- but deassertion must be synchronous after rising edge of clk
property reset_sig(clk,ARESETn)
@(posedge clk)! ARESETn |=> ARESETn[*1:$] ##1! ARESETn;
end property
- During reset :
- A master interface must drive ARVALID, AWVALID, WVALID Low
- A slave interface must drive RVALID and BVALID Low
property Rst_rv(
@(posedge clk)! ARESETn |-> (
AWVALID == 0 && WVALID == 0 &&
ARVALID == 0 && BVALID ==0 ))
Rst_rv: assert property Rst_rv
- Valid control information
property valid_data(
@(posedge ACLK) AWVALID |-> (
$stable(AWID) &&
$stable(AWLEN) &&
$stable(AWPROT)
))
- assert property (disable iff(!ARESETn))
a == x && b == y && c == $past(c)
);
- Data bus(Read, Write) can be 8,16,32,64,128,256,512,1024
assert property (
@posedge clk($countones(DATABUS_WIDTH)==1 || $countones(DATABUS_WIDTH))==1))
- AWLENGTH min and max values
property xxx_range(int min, int max)(
@(posedge clk) AWVALID -> (AWLEN >= min && AWLEN <= max)
endproperty
xxx_range: assert property (xxx_range(0,15)
- for valid transaction
property valid_trans(valid,ready);
@(posedge aclk)
(valid && ready);
end property
- length encoding
property range_inside;
@(posedge ACLK) arlen inside{1,16}
end property
- Error assertion
Except (@(posedge ACLK) WID = AWID) $error("IDs are mismatch")
- ARADDR is stable when ARVALID is asserted high
property valid_check(
@(posedge ACLK)
ARVALID |-> $stable(ARADDR)
endproperty
valid_check: assert property(valid_check)
- property valid_check(
@(posedge ACLK) (ARVALID==1 && ARREADY ==1) |->$stable(ARADDR)
endproperty
Assert_valid_check: assert()
- WRITE BURST
sequence s;
(AWVALID && AWREADY);
endsequence
property wr_burst(
@(posedge ACLK) AWVALID |=> [*1:$] (WVALID ==1 &&
WREADY==1 &&$stable(WDATA))[->1:4]
endproperty
-- write burst
property xyz
@(posedge ACLK)
(AWVALID && AWREADY) |=> [*1:$($stable(WDATA))[->1:4];
endproperty
- out of transaction
sequence s;
(ARVALID ##1 ARREADY)[*2];
endsequence
property out_tr(@(posedge ACLK)
ARVALID |-> s; end property
