How many clock cycles should the reset signal in an AMBA system be

asserted for?
Applies to: AHB, APB
Answer
It is recommended that master and slave components should clearly state if
they have a reset requirement greater than 1 or 2 cycles. It is also
recommended that the system design should hold reset asserted for at least
16 cycles, unless it is known that a master or slave component has a longer
reset requirement.

How should AHB to APB bridges handle accesses that are not 32-
bits?
Applies to: AHB, APB
Answer
The bridge should simply pass the entire 32-bit data bus through the bridge.
Please note that when transfers less than 32-bits are performed to an APB
slave it is important to ensure that the peripheral is located on the
appropriate bits of the APB data bus.

3. What is the difference between SPLIT and RETRY responses in AHB?

Ans:Both the Split and Retry responses are used by slaves which require a
large number of cycles tocomplete a transfer. These responses allow a data
phase transfer to appear completed to avoidstalling the bus, but at the same
time indicate that the transfer should be re-attempted when themaster is
next granted the bus.The difference between them is that a SPLIT response
tells the Arbiter to give priority to all othermasters until the SPLIT transfer
can be completed (effectively ignoring all further requests from thismaster
until the SPLIT slave indicates it can complete the SPLIT transfer), whereas
the RETRYresponse only tells the Arbiter to give priority to higher priority
masters.A SPLIT response is more complicated to implement than a RETRY,
but has the advantage that itallows the maximum efficiency to be made of
the bus bandwidth.The master behaviors is identical to both SPLIT and
RETRY responses, the master has to cancel thenext access and re-attempt
the current failed access.

4. What value should be used for HTRANS when an AHB master gets a RETRY
response from aslave in the middle of burst?
Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it
may also be necessary toadjust the HBURST information (usually just to
indicate INCR).

5. What address should be on the bus during the IDLE cycle after a SPLIT or
RETRY?
 It does not matter what address is driven onto the bus during this cycle.
The slave selected by the

AHB protocol
1. When Should A Master Assert And Deassert The Block Signal For A
Locked Transfer?
The GLOCK signal must be asserted at least one cycle before the start of
the address phase of a locked transfer. This is required so that the arbiter
can sample the HLOCK signal as high at the start of the address phase.
The master should deassert the HLOCK signal when the address phase of
the last transfer in the locked sequence has started.

2. Can An Arbiter Be Designed To Always Allow Bursts To Complete?

A SPLIT, RETRY or ERROR response from a slave can always cause a burst
to be early terminated. This is outwith the control of the Arbiter and so
must be supported.
Undefined length INCR bursts cannot have their end point predicted, so
there is no efficient way that an Arbiter design can allow the burst to
complete before granting another master. INCR bursts must be arbitrated
on a cycle by cycle basis.
Defined length INCRx and WRAPx bursts can have their beats counted,
and so allowed to complete by the Arbiter. However because of the AHB
arbitration synchronous timing, there is no way to avoid possibly
terminating a burst immediately after the first transfer of the burst has
been indicated.
The Arbiter only knows that a defined length burst is in progress by
sampling the HBURST bus. However the first point at which HBURST can
be sampled is after the first clock cycle of the first burst beat, by which
time the Arbiter may already have decided to grant another master and
will have changed the HGRANT outputs accordingly. Only a combinatorial
path from HBURST to HGRANT would allow the burst to be detected in
time to avoid early termination in this scenario, but combinatorial paths in
the AHB bus are not allowed.

3. Why Is Haddr Sometimes Shown As An Input To The Arbiter?

The address bus, HADDR, is not required as an input to the arbiter but in
some system designs it may be useful to use the address bus to
determine a good point to change over between bus masters. For
example, the arbiter could be designed to change bus ownership when a
burst of transfers reaches a quad word boundary.
4. When Can The Hgrant Signal Change?
The GRANT signal can change in any cycle and the following cases
are possible:
o It is possible that the HGRANT signal may be asserted and then
removed before the current transfer completes. This is acceptable
because the HGRANT signal is only sampled by masters when
HREADY is high.
o A master can be granted the bus without requesting it.
o The above point also means that it is possible to be granted the
bus in the same cycle that it is requested. This can occur if the
master is coincidentally granted the bus in the same cycle that it
requests it.

5. What Is The Relationship Between The Hlock Signal And The

Hmastlock Signal?
At the start of the address phase of every transfer the arbiter will sample
the HLOCK signal of the master that is about to start driving the address
bus and if HLOCK is asserted at this point then HMASTLOCK will be
asserted by the arbiter for the duration of the address phase of the
transfer.

6. When Should A Master Deassert Its Hbusreq Signal?

For an undefined length burst (INCR) a master must keep its HBUSREQ
signal asserted until it has started the address phase of the last transfer in
the burst. This will mean that if the penultimate transfer in the burst is
zero wait state then the master may be granted the bus for an additional
transfer at the end of an undefined length burst.
For a defined length burst the master can deassert the HBUSREQ signal
once the master has been granted the bus for the first transfer. This can
be done because the arbiter is able to count the transfers in the burst and
keep the master granted until the burst completes.
However it is not a mandatory requirement for an Arbiter to allow a burst
to complete, so the master will have to re-assert HBUSREQ if the Arbiter
removes HGRANT before the burst has been completed.

7. When Will The Arbiter Grant Another Master After A Locked

Transfer?
The arbiter will always grant the master an extra transfer at the end of a
locked sequence, so the master is guaranteed to perform one transfer
with the HMASTLOCK signal low at the end of the locked sequence. This
coincides with the data phase of the last transfer in the locked sequence.
During this time the arbiter can change the HGRANT signals to a new bus
master, but if the data phase of the last locked transfer receives either a
SPLIT or RETRY response then the arbiter will drive the HGRANT signals to
 ensure that either the master performing the locked sequence remains
granted on the bus for a RETRY response, or the Dummy master is
granted the bus for the SPLIT response.

8. Can A Master Deassert Hlock During A Burst?

The AHB specification requires that all address phase timed control signals
(other than HADDR and HTRANS) remain constant for the duration of a
burst.
Although HLOCK is not an address phase timed signal, it does directly
control the HMASTLOCK signal which is address phase timed.
Therefore HLOCK must remain high for the duration of a burst, and can
only be deasserted such that the following HMASTLOCK signal changes
after the final address phase of the burst.

9. If A Master Is Currently Granted The Bus By Default, How Many

Cycles Before Starting An Non-idle Transfer Does It Have To
Assert Hbusreq?
None. It can start a non IDLE transfer immediately.

10. Can A Master Perform Transfers Other Than Idle When The
Bus Was Granted To It, But Not Requested By The Master?
Yes. A master can perform transfers other than IDLE when it had not
requested the bus. Please note that in this case it is still recommended
that the master asserts its request signal so that the arbiter does not
change ownership of the bus to a lower priority master while the transfers
are in progress.

11. The Specification Recommends That Only 16 Wait States Are

Used. What Should You Do If More Than 16 Cycles Are Needed?
For some slaves it is acceptable to insert more than 16 wait states. For
example, a serial boot ROM which is only ever accessed at initial power up
could insert a larger number of wait states and it would not affect the
calculation of the system performance and latency once system power up
has been completed.
For other slaves a number of options exist. A SPLIT or RETRY response
could be used to indicate that the slave is not yet able to perform the
requested data transfer, or the slave could be accessed either in response
to interrupts or after polling a status register, in either case indicating that
the slave is now able to respond in an acceptable number of cycles.

12. Why Is A Burst Not Allowed To Cross A 1 Kilobyte Boundary?

If an AHB slave samples HSELx at the start of a burst transaction, it
knows it will be selected for the duration of the burst. Also, a slave which
 is not selected at the start of a burst will know that it will not become
selected until a new burst is started.
1 kilobyte is the smallest area an AHB slave may occupy in the memory
map.
Therefore, if a burst did cross a 1 kilobyte boundary, the access could
start accessing one slave at the beginning of the burst and then switch to
another on the boundary, which must not happen for the above reason.
The 1 kilobyte boundary has been chosen as it is large enough to allow
reasonable length bursts, but small enough that peripherals can be
aligned to the 1 kilobyte boundary without using up too much of the
available memory map.

13. Can An Ahb Master Be Connected Directly To An Ahb Slave?

Any slave which does not use SPLIT responses can be connected directly
to an AHB master. If the slave does use SPLIT responses then a simplified
version of the arbiter is also required.
If an AHB master is connected directly to an AHB slave it is important to
ensure that the slave drives HREADY high during reset and that the select
signal HSEL for the slave is tied permanently high.

14. What Is The State Of The Ahb Signals During Reset?

The specification states that during reset the bus signals should be at
valid levels. This simply means that the signals should be logic '0' or '1',
but not Hi-Z. The actual logic levels driven are left up to the designer.
HTRANS is the only signal specified during reset, with a mandatory value
of IDLE.
It is important that ALREADY is high during reset. If all slaves in the
system drive HARDY high during reset then this will ensure that this is the
case. However, if slaves are used which do not drive HREADY high during
reset it should be ensured that a slave which does drive HREADY high is
selected at reset.

15. Can A Busy Transfer Occur At The End Of A Burst?

A BUSY transfer can only occur at the end of an undefined length burst
(INCR). A BUSY transfer cannot occur at the end of a fixed length burst
(SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).

16. What Is A Default Slave?

If the memory map of a system does not define the full 4 gigabyte
address space then a default slave is required, which is selected when an
access is attempted to the empty areas of the memory map. The default
slave should use an OKAY response for IDLE/BUSY transfers and an
ERROR response sequence for NONSEQ/SEQ transfers.
17. Is A Default Slave Really Necessary?
If the entire 4 gigabyte address space is defined then a default slave is
not required. If, however, there are undefined areas in the memory map
then it is important to ensure that a spurious access to a non-existent
address location will not lock up the system. The functionality of the
default slave is extremely simple and it will often make sense to
implement this within the decoder.

18. Is A Dummy Master Really Necessary?

A dummy master is necessary in any system which has a slave that can
give SPLIT transfer responses. The dummy master is required so that
something can be granted the bus if all the other masters have received a
SPLIT response.
No logic is required for the dummy master and it can be implemented by
simply tying off the inputs to the master address/control multiplexer for
the dummy master position. The requirements for a dummy master are
that HTRANS is driven to IDLE, GLOCK is driven low, and all other master
outputs are driven to legal values.

19. Is It Specified That Hprot, Hsize And Hwrite Remain Constant

Throughout A Burst?
Yes, the control signals must remain constant throughout the duration of
a burst.

20. What Default State Should Be Used For The Hready And Hresp
Outputs From A Slave?
It is recommended that the default value for HREADY is high and the
default value for HRESP is OKAY. This combination ensures that the slave
will respond correctly to IDLE transfers to the slave, even if the slave is in
some form of power saving mode.

21. Is Hready An Input Or An Output From Slaves?

An AHB slave must have the HREADY signal as both an input and an
output.
HREADY is required as an output from a slave so that the slave can
extend the data phase of a transfer.
HREADY is also required as an input so that the slave can determine when
the previously selected slave has completed its final transfer and the first
data phase transfer for this slave is about to commence.
Each AHB Slave should have an HREADY output signal (conventionally
named HREADYOUT) which is connected to the Slave-to-Master
Multiplexer. The output of this multiplexer is the global HREADY signal
which is routed to all masters on the AHB and is also fed back to all slaves
as the HREADY input.
22. How Many Masters Can There Be In An Ahb System?
The AHB specification caters for up to 16 masters. However, allowing for a
dummy bus master means the maximum number of real bus masters is
actually 15. By convention bus master number 0 is allocated to the
dummy bus master.

23. Can A Master Change The Address/control Signals During A

Waited Transfer?
Yes. If the address/control signals are indicating an IDLE transfer then the
master can change to a real transfer (NONSEQ) when HREADY is low.
However, if a master is indicating a real transfer (NONSEQ or SEQ) then it
cannot cancel this during a waited transfer unless it receives a SPLIT,
RETRY or ERROR response.

24. When A Master Rebuilds A Burst Which Has Been Terminated

Early Are There Any Limitations On How It Rebuilds The Burst?
The only limitation is that the master uses legal burst combinations to
rebuild the burst. For example, if a master was performing an 8 beat
burst, but had only completed 3 transfers before losing control of the bus,
then the remaining 5 transfers could be performed either by using a 1
beat SINGLE burst followed by a 4 beat INCR burst, or it could be
performed using a 5 beat undefined length INCR burst.
For simplicity it is recommended that masters use INCR bursts to rebuild
the remaining transfers.

25. What Is The Recommended Default Value For Hprot?

Many bus masters will not be able to generate accurate protection
information and for these bus masters it is recommended that the HPROT
encoding shows, Non-cacheable, Non-bufferable, Privileged, Data
Accesses which corresponds to HPROT[3:0] = 4'b0011.

26. Do All Slaves Have To Support The Busy Transfer Type?

Yes. All slaves must support the BUSY transfer type to ensure they are
compatible with any bus master.

27. What System Support Is Required If A Slave Can Be Powered

Down Or Have Its Clock Stopped?
If a slave access is attempted while that slave is in a power down state or
has had its clock stopped, you must ensure that an access will cause the
power/clock to be restored, or else configure the AHB decoder up to
redirect any such accesses to the dummy slave so that the system does
not hang forever when an access to the device is made when it is
disabled.
 Redirecting the access in this way will ensure that random "IDLE"
addresses are treated with the HREADY high and HRESP=OKAY default
response, but real accesses (NONSEQ or SEQ) will be detected with an
ERROR response.

28. When Can Early Burst Termination Occur?

Bursts can be early terminated either as a result of the Arbiter removing
the HGRANT to a master part way through a burst, or after a slave returns
a non-OKAY response to any beat of a burst. Note however that a master
cannot decide to terminate a defined length burst unless prompted to do
so by the Arbiter or Slave responses.
All AHB Masters, Slaves and Arbiters must be designed to support Early
Burst Termination.

29. Does The Address Have To Be Aligned, Even For Idle

Transfers?
Yes. The address should be aligned according to the transfer size (HSIZE)
even for IDLE transfers. This will prevent spurious warnings from bus
monitors used during simulation.

30. What Is The Difference Between A Dummy Bus Master And A

Default Bus Master?
The term default bus master is used to describe the master that is
granted when none of the masters in the system are requesting access to
the bus. Usually the bus master which is most likely to request the bus is
made the default master.
The dummy bus master is a master which only performs IDLE transfers. It
is required in a system so the arbiter can grant a master which is
guaranteed not to perform any real transfers. The two cases when the
arbiter would need to do this are when a SPLIT response is given to a
locked transfer and when a SPLIT response is given and all other masters
have already been SPLIT.

31. Is It Legal For A Master To Change Haddr When A Transfer Is

Extended?
If a master is indicating that it wants to do a NONSEQ, SEQ or BUSY
transfer then it cannot change the address during an extended
transfer(when HREADY is low) unless it receives an ERROR, RETRY or
SPLIT response.
If the master is indicating that it wants to do an IDLE transfer then it may
change the address.

32. Can Htrans Change Whilst Hready Is Low?

 In general, an AHB master should not change control signals whilst
HREADY is low.

However it is allowable to change HTRANS in the following

conditions:
HTRANS = IDLE
The AHB master is performing internal operations and has not yet
committed to a bus transfer. However during the AHB wait states
(HREADY low) the master may determine that a bus transfer is required
and change
HTRANS on the next cycle to NONSEQ.
HTRANS = BUSY
HTRANS is being used to give the master time to complete internal
operations, which may be entirely independent of HREADY (i.e. wait states
on the AHB). Therefore HTRANS can change on the next cycle to any legal
value, i.e. SEQ if the burst is to continue, IDLE if the burst has completed,
NONSEQ if a separate burst is to begin.
HRESP = SPLIT/RETRY
As stated in the AHB specification, a master must assert IDLE on HTRANS
during the second cycle of the two-cycle SPLIT or RETRY slave response
so HTRANS will change value from the first cycle to the second cycle of
the response.
HRESP = ERROR
The master is permitted to change HTRANS in reaction to an ERROR
response in the same way as in reaction to a SPLIT/RETRY response and
cancel any further beats in the current burst (even if HBURST is indicating
a defined-length burst). In this case HTRANS changes to IDLE on the
second cycle of the response. Alternatively, the master is permitted to
continue with the current transfers

33. What Are The Different Bursts Used For?

Typically a master would use wrapping bursts for cache line fills where the
master wants to access the data it requires first and then it completes the
burst to fetch the remaining data it requires for the cache line fill.
Incrementing bursts are used by masters, such as DMA controllers, that
are filling a buffer in memory which may not be aligned to a particular
address boundary.

34. How Should Ahb To Apb Bridges Handle Accesses That Are Not
32-bits?
The bridge should simply pass the entire 32-bit data bus through the
bridge. Please note that when transfers less than 32-bits are performed to
an APB slave it is important to ensure that the peripheral is located on the
appropriate bits of the APB data bus.
35. What Value Should Be Used For Htrans When An Ahb Master
Gets A Retry Response From A Slave In The Middle Of Burst?
Whenever a transfer is restarted it must use HTRANS set to NONSEQ and
it may also be necessary to adjust the HBURST information (usually just
to indicate INCR)
.
36. What Address Should Be On The Bus During The Idle Cycle
After A Split Or Retry?
It does not matter what address is driven onto the bus during this cycle.
The slave selected by the driven address should not take any action and
must respond with a zero wait state OKAY response.
In many cases it will be simpler for the master to leave the address
unaltered during this cycle, so that it remains at the address of the next
transfer that the master wishes to perform and only in the following cycle
does the master return the address to that of the transfer that must be
repeated because of the SPLIT or RETRY response.
In some designs it may be possible for the master to return the address to
that required to repeat the previous transfer during the IDLE cycle and
this behaviour is also perfectly acceptable.

37. Do All Masters Have To Support Split And Retry?

Yes. All masters must support SPLIT and RETRY responses to ensure they
are compatible with any bus slave. A master will handle both SPLIT and
RETRY responses in an identical manner.

38. Can A Split Or Retry Response Be Given At Any Point During A

Burst?
Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any
transfer during a burst. The slave is not restricted to only giving these
responses to the first transfer.

39. Will A Master Always Lose The Bus After A Split Response?
Yes. A slave must not assert the relevant bit of the SPLIT bus in the same
cycle that it gives the SPLIT response and therefore the master will always
lose the bus.

40. Can A Slave Assert Hsplitx In The Same Cycle That It Gives A
Split Response?
No. The specification requires that HSPLITx can only be asserted after the
slave has given a SPLIT response.

41. Do All Slaves Have To Support The Split And Retry Responses?
 No. A slave is only required to support the response types that it needs to
use. For example, a simple on-chip memory block which can respond to
all transfers in just a few wait states does not need to use either the
SPLIT or RETRY responses.

42. Can A Slave Use Both Split And Retry Responses?

Normally a slave will not use both the SPLIT and RETRY responses. The
SPLIT response should be used by any slave that may be accessed by
many different masters at the same time. The RETRY response is intended
to be used by peripherals that are only accessed by one bus master.

43. What Is The Difference Between Split And Retry Responses?

Both the Split and Retry responses are used by slaves which require a
large number of cycles to complete a transfer. These responses allow a
data phase transfer to appear completed to avoid stalling the bus, but at
the same time indicate that the transfer should be re-attempted when the
master is next granted the bus.
The difference between them is that a SPLIT response tells the Arbiter to
give priority to all other masters until the SPLIT transfer can be completed
(effectively ignoring all further requests from this master until the SPLIT
slave indicates it can complete the SPLIT transfer), whereas the RETRY
response only tells the Arbiter to give priority to higher priority masters.
A SPLIT response is more complicated to implement than a RETRY, but
has the advantage that it allows the maximum efficiency to be made of
the bus bandwidth.
The master behaviour is identical to both SPLIT and RETRY responses, the
master has to cancel the next access and re-attempt the current failed
access.

Does HWDATA have to remain stable during an extended transfer?

HWDATA is guaranteed to remain at the same value when sampled at
different clock edges in an extended transfer. However, it is possible that
HWDATA can glitch after clock edges, returning to the same value as
previously driven. It is possible to observe this behaviour when using a
typical synthesis design flow, where the control signals for the HWDATA
output multiplexor can change during the extended transfer, but they result
in the same output value being used.

AHB Protocol: Must a read after a write to the same address return
the newly written data?
Scenario
When there is an AHB write followed by a read from the same address,
should the read return the old or the new data when the read address phase
is in same cycle of the write data phase?
Answer
The answer to this question is dependent on the design of the slave.
A simple slave will not be buffering any data, so the returned read data will
be the latest. A more complex slave could implement buffering for write data
(if allowed by HPROT[2]) and so it could "snoop" the write buffer contents
before returning read data, or it might just return the previously stored data
regardless of what might be buffered.
In conclusion, all the AHB specification requires is that data is returned.

AHB-lite - Can HWDATA change in the 2nd cycle of an ERROR

response ?
Answer
The AHB-lite protocol (ARM IHI 0033A) shows in figure 5-1
"ERROR response" that when an ERROR response is being returned, and the
master decides to end the current burst, the HWDATA bus can change at the
start of the final cycle of the data phase transfer.
However it is recommended, but not required, that a master keeps HWDATA
stable for all cycles of a write transfer that receives an ERROR response.
Note that a slave returning an ERROR response must not require that
HWDATA is stable after the first cycle of the error response.

Arbitration: Can a master deassert HLOCK during a burst?

The AHB specification requires that all address phase timed control signals
(other than HADDR and HTRANS) remain constant for the duration of a
burst.
Although HLOCK is not an address phase timed signal, it does directly
control the HMASTLOCK signal which is address phase timed.
Therefore HLOCK must remain high for the duration of a burst, and can only
be deasserted such that the following HMASTLOCK signal changes after the
final address phase of the burst.

Arbitration: Can a master perform transfers other than IDLE when

the bus was granted to it, but not requested by the master?
Yes. A master can perform transfers other than IDLE when it had not
requested the bus. Please note that in this case it is still recommended that
the master asserts its request signal so that the arbiter does not change
ownership of the bus to a lower priority master while the transfers are in
progress.
Arbitration: If a master is currently granted the bus by default, how
many cycles before starting an non-IDLE transfer does it have to
assert HBUSREQ?
None. It can start a non IDLE transfer immediately.
Arbitration: What is the relationship between the HLOCK signal and
the HMASTLOCK signal?
At the start of the address phase of every transfer the arbiter will sample the
HLOCK signal of the master that is about to start driving the address bus
and if HLOCK is asserted at this point then HMASTLOCK will be asserted by
the arbiter for the duration of the address phase of the transfer.

Arbitration: When can the HGRANT signal change?

The HGRANT signal can change in any cycle and the following cases are
possible:
• It is possible that the HGRANT signal may be asserted and then
removed before the current transfer completes. This is acceptable
because the HGRANT signal is only sampled by masters when HREADY
is high.
• A master can be granted the bus without requesting it.
• The above point also means that it is possible to be granted the bus in
the same cycle that it is requested. This can occur if the master is
coincidentally granted the bus in the same cycle that it requests it.

Arbitration: Why is HADDR sometimes shown as an input to the

arbiter?
Answer
The address bus, HADDR, is not required as an input to the arbiter but in
some system designs it may be useful to use the address bus to determine a
good point to change over between bus masters. For example, the arbiter
could be designed to change bus ownership when a burst of transfers
reaches a quad word boundary.

Can an arbiter be designed to always allow bursts to complete?

Applies to: AHB
Answer
Applies to: AMBA AHB
A SPLIT, RETRY or ERROR response from a slave can always cause a burst to
be early terminated. This is outwith the control of the Arbiter and so must be
supported.
Undefined length INCR bursts cannot have their end point predicted, so
there is no efficient way that an Arbiter design can allow the burst to
complete before granting another master. INCR bursts must be arbitrated on
a cycle by cycle basis.
Defined length INCRx and WRAPx bursts can have their beats counted, and
so allowed to complete by the Arbiter. However because of the AHB
arbitration synchronous timing, there is no way to avoid possibly terminating
a burst immediately after the first transfer of the burst has been indicated.
The Arbiter only knows that a defined length burst is in progress by sampling
the HBURST bus. However the first point at which HBURST can be sampled
is after the first clock cycle of the first burst beat, by which time the Arbiter
may already have decided to grant another master and will have changed
the HGRANT outputs accordingly. Only a combinatorial path from HBURST to
HGRANT would allow the burst to be detected in time to avoid early
termination in this scenario, but combinatorial paths in the AHB bus are not
allowed.
Does a master need to issue non-LOCKed accesses when accessing a
sequence of AHB slaves ?
If a master performs lots of back-to-back LOCKed access sequences, the
selected slave has no idea when one sequence ends and a new one starts.
In a multi-layer AHB system, if one master is performing LOCKed accesses
to a slave, no other master can access that slave until the LOCKed sequence
has ended.
If in that multi-layer system the master attempts LOCKed accesses to a
number of slaves, each NOT ending with unLOCKed accesses, that master
will progressively LOCK up more and more of the system slaves, stopping
other masters accessing them.
There is then a risk of system deadlock if 2 masters attempt LOCKed
sequences crossing between 2 different slaves, one to slave A then slave B,
and the other to slave B then slave A. Each master will complete its LOCKed
transfers to the first slave, but will then be deadlocked because the other
master has not released the first slave. Reset (or a SPLIT/RETRY response
from one slave) would be the only way out of this.
The ADK BusMatrix insists that LOCKed sequences do not cross between
different slaves, so deadlock is not possible.

Does the AHB Arbiter require address lines as input?

Scenario
In AMBA specification v2.0, fig 3-31 of the AHB arbiter shows address lines
as input to the arbiter. Why does the arbiter require address lines? Should
these address lines be from all masters or the from the master which has
been granted bus access?
Answer
The address lines are just from the master which has been granted bus
access. However, there is no compulsion for the arbiter to use these address
signals; they are provided for your convenience. If you can think of an
arbitration scheme that can make use of the address signals then you may
implement them.
General : What system support is required if a slave can be powered
down or have its clock stopped?
If a slave access is attempted while that slave is in a power down state or
has had its clock stopped, you must ensure that an access will cause the
power/clock to be restored, or else configure the AHB decoder up to redirect
any such accesses to the dummy slave so that the system does not hang
forever when an access to the device is made when it is disabled.
Redirecting the access in this way will ensure that random "IDLE" addresses
are treated with the HREADY high and HRESP=OKAY default response, but
real accesses (NONSEQ or SEQ) will be detected with an ERROR response.

General : When can Early Burst Termination occur

Answer
Bursts can be early terminated either as a result of the Arbiter removing the
HGRANT to a master part way through a burst, or after a slave returns a
non-OKAY response to any beat of a burst. Note however that a master
cannot decide to terminate a defined length burst unless prompted to do so
by the Arbiter or Slave responses.
All AHB Masters, Slaves and Arbiters must be designed to support Early
Burst Termination.
General: Can HTRANS change whilst HREADY is low?
Answer
In general, an AHB master should not change control signals whilst HREADY
is low. However it is allowable to change HTRANS in the following conditions:
• HTRANS = IDLE
The AHB master is performing internal operations and has not yet
committed to a bus transfer. However during the AHB wait states
(HREADY low) the master may determine that a bus transfer is
required and change HTRANS on the next cycle to NONSEQ.
• HTRANS = BUSY
HTRANS is being used to give the master time to complete internal
operations, which may be entirely independent of HREADY (i.e. wait
states on the AHB). Therefore HTRANS can change on the next cycle
to any legal value, i.e. SEQ if the burst is to continue, IDLE if the burst
has completed, NONSEQ if a separate burst is to begin.
• HRESP = SPLIT/RETRY
As stated in the AHB specification, a master must assert IDLE on
HTRANS during the second cycle of the two-cycle SPLIT or RETRY slave
 response so HTRANS will change value from the first cycle to the
second cycle of the response.
• HRESP = ERROR
The master is permitted to change HTRANS in reaction to an ERROR
response in the same way as in reaction to a SPLIT/RETRY response
and cancel any further beats in the current burst (even if HBURST is
indicating a defined-length burst). In this case HTRANS changes to
IDLE on the second cycle of the response. Alternatively, the master is
permitted to continue with the current transfers.

Can a BUSY transfer occur at the end of a burst?

Answer
A BUSY transfer can only occur at the end of an undefined length burst
(INCR). A BUSY transfer cannot occur at the end of a fixed length burst
(SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).
Can a master change the address/control signals during a waited
transfer?
Answer
Yes. If the address/control signals are indicating an IDLE transfer then the
master can change to a real transfer (NONSEQ) when HREADY is low.
However, if a master is indicating a real transfer (NONSEQ or SEQ) then it
cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY
or ERROR response.

Can an AHB master be connected directly to an AHB slave?

Answer
Any slave which does not use SPLIT responses can be connected directly to
an AHB master. If the slave does use SPLIT responses then a simplified
version of the arbiter is also required.
If an AHB master is connected directly to an AHB slave it is important to
ensure that the slave drives HREADY high during reset and that the select
signal HSEL for the slave is tied permanently high.

Do all slaves have to support the BUSY transfer type?

Answer
Yes. All slaves must support the BUSY transfer type to ensure they are
compatible with any bus master.

Does the address have to be aligned, even for IDLE transfers?

Applies to: AHB
Answer
Yes. The address should be aligned according to the transfer size (HSIZE)
even for IDLE transfers. This will prevent spurious warnings from bus
monitors used during simulation.
How many masters can there be in an AHB system?
Answer
The AHB specification caters for up to 16 masters. However, allowing for a
dummy bus master means the maximum number of real bus masters is
actually 15. By convention bus master number 0 is allocated to the dummy
bus master.

How should AHB to APB bridges handle accesses that are not 32-
bits?
Answer
The bridge should simply pass the entire 32-bit data bus through the bridge.
Please note that when transfers less than 32-bits are performed to an APB
slave it is important to ensure that the peripheral is located on the
appropriate bits of the APB data bus.

Is HREADY an input or an output from slaves?

Answer
An AHB slave must have the HREADY signal as both an input and an output.
HREADY is required as an output from a slave so that the slave can extend
the data phase of a transfer.
HREADY is also required as an input so that the slave can determine when
the previously selected slave has completed its final transfer and the first
data phase transfer for this slave is about to commence.
Each AHB Slave should have an HREADY output signal (conventionally
named HREADYOUT) which is connected to the Slave-to-Master Multiplexer.
The output of this multiplexer is the global HREADY signal which is routed to
all masters on the AHB and is also fed back to all slaves as the HREADY
input.

Is a default slave really necessary?

Answer
If the entire 4 gigabyte address space is defined then a default slave is not
required. If, however, there are undefined areas in the memory map then it
is important to ensure that a spurious access to a non-existent address
location will not lock up the system. The functionality of the default slave is
extremely simple and it will often make sense to implement this within the
decoder.

Is a dummy master really necessary?

Answer
A dummy master is necessary in any system which has a slave that can give
SPLIT transfer responses. The dummy master is required so that something
can be granted the bus if all the other masters have received a SPLIT
response.
No logic is required for the dummy master and it can be implemented by
simply tying off the inputs to the master address/control multiplexer for the
dummy master position. The requirements for a dummy master are that
HTRANS is driven to IDLE, HLOCK is driven low, and all other master outputs
are driven to legal values.

Is it legal for a master to change HADDR when a transfer is

extended?
Answer
If a master is indicating that it wants to do a NONSEQ or SEQ transfer then
it cannot change the address during an extended transfer (when HREADY is
low) unless it receives an ERROR, RETRY or SPLIT response.
If the master is indicating that it wants to do an IDLE transfer then it may
change the address, but if it is indicating a BUSY transfer it can only change
the address if the current undefined length burst is being terminated
(with HTRANS also changing to IDLE or NONSEQ).

Is it specified that HPROT, HSIZE and HWRITE remain constant

throughout a burst?
Yes, the control signals must remain constant throughout the duration of a
burst.

The specification recommends that only 16 wait states are used.

What should you do if more than 16 cycles are needed?
Answer
For some slaves it is acceptable to insert more than 16 wait states. For
example, a serial boot ROM which is only ever accessed at initial power up
could insert a larger number of wait states and it would not affect the
calculation of the system performance and latency once system power up
has been completed.
For other slaves a number of options exist. A SPLIT or RETRY response could
be used to indicate that the slave is not yet able to perform the requested
data transfer, or the slave could be accessed either in response to interrupts
or after polling a status register, in either case indicating that the slave is
now able to respond in an acceptable number of cycles.

What are the different bursts used for?

Applies to: AHB
Answer
Typically a master would use wrapping bursts for cache line fills where the
master wants to access the data it requires first and then it completes the
burst to fetch the remaining data it requires for the cache line fill.
Incrementing bursts are used by masters, such as DMA controllers, that are
filling a buffer in memory which may not be aligned to a particular address
boundary.

What default state should be used for the HREADY and HRESP
outputs from a slave?
Applies to: AHB
Answer
It is recommended that the default value for HREADY is high and the default
value for HRESP is OKAY. This combination ensures that the slave will
respond correctly to IDLE transfers to the slave, even if the slave is in some
form of power saving mode.

What is a default slave?

Applies to: AHB
Answer
If the memory map of a system does not define the full 4 gigabyte address
space then a default slave is required, which is selected when an access is
attempted to the empty areas of the memory map. The default slave should
use an OKAY response for IDLE/BUSY transfers and an ERROR response
sequence for NONSEQ/SEQ transfers.
What is the difference between a dummy bus master and a default
bus master?
Applies to: AHB
Answer
The term default bus master is used to describe the master that is granted
when none of the masters in the system are requesting access to the bus.
Usually the bus master which is most likely to request the bus is made the
default master.
The dummy bus master is a master which only performs IDLE transfers. It is
required in a system so the arbiter can grant a master which is guaranteed
not to perform any real transfers. The two cases when the arbiter would
need to do this are when a SPLIT response is given to a locked transfer and
when a SPLIT response is given and all other masters have already been
SPLIT.

What is the recommended default value for HPROT?

Applies to: AHB
Answer
Many bus masters will not be able to generate accurate protection
information and for these bus masters it is recommended that the HPROT
encoding shows, Non-cacheable, Non-bufferable, Privileged, Data Accesses
which corresponds to HPROT[3:0] = 4'b0011.
What is the state of the AHB signals during reset?
Applies to: AHB
Answer
The specification states that during reset the bus signals should be at valid
levels. This simply means that the signals should be logic '0' or '1', but not
Hi-Z. The actual logic levels driven are left up to the designer. HTRANS is the
only signal specified during reset, with a mandatory value of IDLE.
It is important that HREADY is high during reset. If all slaves in the system
drive HREADY high during reset then this will ensure that this is the case.
However, if slaves are used which do not drive HREADY high during reset it
should be ensured that a slave which does drive HREADY high is selected at
reset.
What sequences of transfers types (HTRANS) can occur on the bus?
Applies to: AHB
Answer
The following examples show some of the sequences of HTRANS that can
occur on the bus:
A normal burst of four transfers followed by an IDLE.
N-S-S-S-I
A normal burst of four transfers which includes BUSY transfers.
N-S-B-S-B-S-I
A burst of four transfers followed by another burst.
N-S-S-S-N-S-S-S-I
A single transfer followed by a burst of four transfers.
N-N-S-S-S-I
A single transfer followed by an IDLE
N-I
An undefined length burst which concludes with a BUSY transfer.
N-B-S-B-S-B-I
An undefined length burst which concludes with a BUSY transfer and is
followed immediately by another burst.
N-B-S-B-S-B-N-S

When a master rebuilds a burst which has been terminated early are
there any limitations on how it rebuilds the burst?
Applies to: AHB
Answer
The only limitation is that the master uses legal burst combinations to
rebuild the burst. For example, if a master was performing an 8 beat burst,
but had only completed 3 transfers before losing control of the bus, then the
remaining 5 transfers could be performed either by using a 1 beat SINGLE
burst followed by a 4 beat INCR4 burst, or it could be performed using a 5
beat undefined length INCR burst.
For simplicity it is recommended that masters use INCR bursts to rebuild the
remaining transfers.

Why is a burst not allowed to cross a 1 kilobyte boundary?

Applies to: AHB
Answer
If an AHB slave samples HSELx at the start of a burst transaction, it knows it
will be selected for the duration of the burst. Also, a slave which is not
selected at the start of a burst will know that it will not become selected
until a new burst is started.
1 kilobyte is the smallest area an AHB slave may occupy in the memory
map. Therefore, if a burst did cross a 1 kilobyte boundary, the access could
start accessing one slave at the beginning of the burst and then switch to
another on the boundary, which must not happen for the above reason.
The 1 kilobyte boundary has been chosen as it is large enough to allow
reasonable length bursts, but small enough that peripherals can be aligned
to the 1 kilobyte boundary without using up too much of the available
memory map.

How do I use the ARMv6 AHB-Lite extension signals in my AMBA 2.0

system?
Applies to: AHB
Scenario
My AHB system contains an ARM1136 which uses ARMv6 AHB-Lite extension
signals. How do I use these signals?
The signals in question are:
HRESP[2], HPROT[4:2], HPROT[5], HUNALIGN,
HBSTRB[7:0],HSIDEBAND[0] and HSIDEBAND[3:1]
Answer
The purpose of the signals and how to use them is shown below:
HRESP[2]
========
This indicates an exclusive access has failed and is an input to the
core. Since there is no provision for Exclusive Access in an AMBA 2.0
system (AHB), this signal is not used and can therefore be tied HIGH.

HPROT[4:2]
==========
Indicates memory type. These are outputs and, if your memory system
doesn't require this information, you may ignore these signals.
HPROT[5]
========
Indicates an exclusive access and is an output. Leave unconnected.

HUNALIGN
========
Quote from the TRM: "This signal is only provided to assist with
backwards compatibility and indicates when a single unaligned transfer
occurs that requires more than one AHB v2.0 transfer without byte
strobes. The HUNALIGN signal has address phase timing and must be
asserted HIGH for unaligned transfers and LOW for AHB v2.0 compatible
aligned transfers.". You can therefore leave it unconnected, provided
you will not be making any unaligned transfers.

HBSTRB[7:0]
===========
Again, these are for use with unaligned transfers and indicate which
byte lanes are active during a transfer. An AMBA v2.0 system should not
make use of them so you can leave them unconnected.

HSIDEBAND[0] and HSIDEBAND[3:1]

============ ==============
These indicate the type of memory being accessed and are not applicable
in an AMBA v2.0 memory system. Leave unconnected.

Basically, all the signals can be left unconnected with the exception of
HRESP[2] which is an input and should be tied HIGH, PROVIDING the core
is in backwards-compatible mode (the default at reset) and no attempt is
made to change into BE-8 bigendianness.

How do you connect an AHB Master to an AHB-lite system?

Applies to: AHB
Answer
An AHB-lite system does not have any arbitration logic, so the full AHB
master will be permanently granted. The full AHB master HBUSREQ output
will be left unconnected, and the HGRANT input tied to logic '1' (1'b1).
As AHB-lite does not support SPLIT or RETRY responses, the AHB-lite HRESP
signal is a single bit, so the full AHB master HRESP[1:0] input should have
HRESP[1] tied to logic '0' (1'b0).
The full AHB master drives HLOCK in advance of the LOCKed transfer
address phase, and this would normally be retimed in full AHB by an Arbiter
module to produce HMASTLOCK, which is address phase aligned.
The following Verilog code would implement the required AHB HLOCK ->
AHB-lite HMASTLOCK retiming function.
 always @( negedge (HRESETn) or posedge (HCLK) )
begin
if ((!HRESETn))
HMASTLOCK <= 1'b0;
else
begin
if (HREADY)
HMASTLOCK <= HLOCK;
end
end

How do you connect an AHB slave to an AHB-lite system?

Applies to: AHB
Answer
AHB slaves are fully AHB-lite compatible, so can be connected directly,
unless they generate SPLIT or RETRY responses.
If the AHB slave generates RETRY responses, you will need an Ahb2Ahb
bridge (there are several examples in ARM's AMBA Design Kit (ADK))
between the AHB slave and the AHB-lite system. This Ahb2Ahb bridge will
locally service the RETRY response, while holding HREADY low (1'b0) to the
AHB-lite system.
If the AHB slave generates SPLIT responses then in addition to the Ahb2Ahb
bridge required for RETRY responses, you would also need a local Dummy
master and an Arbiter. SPLIT responses require the arbiter to grant a
different master, so we need the dummy master on this local full-AHB bus to
drive IDLE cycles until the slave is able to complete the SPLIT transfer.
How do you connect an AHB-lite Master to a full AHB system?
Applies to: AHB
Answer
You will need logic to add the HBUSREQ and HGRANT signals, to advance the
timing of the HLOCK output to be ahead of the LOCKed transfer address
phase, and to support SPLIT or RETRY responses on HRESP.
None of this logic is trivial, so you would need an AHB-lite master wrapper,
such as the Lite2Ahb component found in ARM's AMBA Design Kit (ADK).

How do you connect an AHB-lite Slave to a full AHB system?

Applies to: AHB
Answer
An AHB-lite slave is already AHB compliant, with only the HRESP output
(indicating OKAY or ERROR) needing to be extended to 2 bits to be
compatible with the full AHB HRESP[1:0] bus. HRESP[1] would be driven to
logic '0' (1'b0).

How does AHB differ from AHB-lite?

Applies to: AHB
Answer
AHB-lite is a simplified version of the full AMBA 2 AHB specification,
supporting only a single Master.
This removes the need for arbitration signals, HBUSREQ and HGRANT, and
HRESP only needs to be 1 bit as SPLIT and RETRY slave responses are only
used for multi-master support.
The removal of any arbitration logic also means the AHB Master HLOCK
output (driven ahead of the LOCKed transfer address phase) needs to be
retimed to be the address phase aligned HMASTLOCK signal (a function
usually performed by the AHB arbiter).

How does the AHB handle LOCKed SPLITs?

Applies to: AHB
Answer
When a transfer is SPLIT the arbiter degrants and removes the SPLIT master
out of the arbitration until the slave indicates that the transfer can complete.
When an access is LOCKed the access cannot be interrupted by an access
from another master.
The only possible way that an AHB system can handle these two
requirements simultaneously is to grant a "dummy master" when the
LOCKed access is SPLIT. The dummy master will only perform IDLE
transactions, which are allowable during a locked transfer. To grant any
other master would violate the LOCK protocol, for the arbiter to ignore the
SPLIT would violate the SPLIT protocol - the dummy master is the only
option.
The dummy master is also used when all masters are have received a SPLIT
response (the dummy master cannot receive a SPLIT response).
It is recommended that the designer of the split-capable slave(s) makes
sure that the slave monitors its HMASTLOCK input so that it doesn't return a
SPLIT on a LOCKed transfer, as this serves no purpose.

How many clock cycles should the reset signal in an AMBA system be
asserted for?
Applies to: AHB, APB
Answer
It is recommended that master and slave components should clearly state if
they have a reset requirement greater than 1 or 2 cycles. It is also
recommended that the system design should hold reset asserted for at least
16 cycles, unless it is known that a master or slave component has a longer
reset requirement.

Is it legal for an AHB wrapping burst to be aligned with respect to

the total number bytes in the burst, such that it does not wrap?
Applies to: AHB, AMBA Design Kit (ADK)
Answer
Yes, this behavior is compliant with the AHB protocol.
Consider a four-beat wrapping burst of word (4-byte) transfers (which will
wrap at 16-byte boundaries).
If the start address of the transfer is 0x30, then the burst consists of four
transfers to addresses 0x30, 0x34, 0x38, and 0x3C.
Again, although HBURST is set to WRAP4, the burst will not actually wrap,
which is allowed.
Split/Retry: Can a SPLIT or RETRY response be given at any point
during a burst?
Applies to: AHB
Answer
Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any
transfer during a burst. The slave is not restricted to only giving these
responses to the first transfer.

Split/Retry: Can a slave assert HSPLITx in the same cycle that it

gives a SPLIT response?
Applies to: AHB
Answer
No. The specification requires that HSPLITx can only be asserted after the
slave has given a SPLIT response.

Split/Retry: Can a slave use both SPLIT and RETRY responses?

Applies to: AHB
Answer
Normally a slave will not use both the SPLIT and RETRY responses. The
SPLIT response should be used by any slave that may be accessed by many
different masters at the same time. The RETRY response is intended to be
used by peripherals that are only accessed by one bus master.

Split/Retry: Do all masters have to support SPLIT and RETRY?

Applies to: AHB
Answer
Yes. All masters must support SPLIT and RETRY responses to ensure they
are compatible with any bus slave. A master will handle both SPLIT and
RETRY responses in an identical manner.
Note that if the system is based on AHB-Lite, SPLIT and RETRY responses
are not supported. AHB-lite is a single master solution, so SPLIT and RETRY
responses would have no meaning.

Split/Retry: Do all slaves have to support the SPLIT and RETRY

responses?
Applies to: AHB
Answer
No. A slave is only required to support the response types that it needs to
use. For example, a simple on-chip memory block which can respond to all
transfers in just a few wait states does not need to use either the SPLIT or
RETRY responses.

Split/Retry: What address should be on the bus during the IDLE

cycle after a SPLIT or RETRY?
Applies to: AHB
Answer
It does not matter what address is driven onto the bus during this cycle. The
slave selected by the driven address should not take any action and must
respond with a zero wait state OKAY response.
In many cases it will be simpler for the master to leave the address
unaltered during this cycle, so that it remains at the address of the next
transfer that the master wishes to perform and only in the following cycle
does the master return the address to that of the transfer that must be
repeated because of the SPLIT or RETRY response.
In some designs it may be possible for the master to return the address to
that required to repeat the previous transfer during the IDLE cycle and this
behaviour is also perfectly acceptable.

Split/Retry: What is the difference between SPLIT and RETRY

responses?
Applies to: AHB
Answer
Both the Split and Retry responses are used by slaves which require a large
number of cycles to complete a transfer. These responses allow a data phase
transfer to appear completed to avoid stalling the bus, but at the same time
indicate that the transfer should be re-attempted when the master is next
granted the bus.
The difference between them is that a SPLIT response tells the Arbiter to
give priority to all other masters until the SPLIT transfer can be completed
(effectively ignoring all further requests from this master until the SPLIT
slave indicates it can complete the SPLIT transfer), whereas the RETRY
response only tells the Arbiter to give priority to higher priority masters.
A SPLIT response is more complicated to implement than a RETRY, but has
the advantage that it allows the maximum efficiency to be made of the bus
bandwidth.
The master behaviour is identical to both SPLIT and RETRY responses, the
master has to cancel the next access and re-attempt the current failed
access.
Split/Retry: What value should be used for HTRANS when an AHB
master gets a RETRY response from a slave in the middle of burst?
Applies to: AHB
Answer
Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it
may also be necessary to adjust the HBURST information (usually just to
indicate INCR).

Split/Retry: Will a master always lose the bus after a SPLIT

response?
Applies to: AHB
Answer
Yes. A slave must not assert the relevant bit of the HSPLIT bus in the same
cycle that it gives the SPLIT response and therefore the master will always
lose the bus.
When should a master assert and deassert the HLOCK signal for a
locked transfer?
Applies to: AHB
Answer
The HLOCK signal must be asserted at least one cycle before the start of the
address phase of a locked transfer. This is required so that the arbiter can
sample the HLOCK signal as high at the start of the address phase.
The master should deassert the HLOCK signal when the address phase of the
last transfer in the locked sequence has started.

When should a master deassert its HBUSREQ signal?

Applies to: AHB
Answer
For an undefined length burst (INCR) a master must keep its HBUSREQ
signal asserted until it has started the address phase of the last transfer in
the burst. This will mean that if the penultimate transfer in the burst is zero
wait state then the master may be granted the bus for an additional transfer
at the end of an undefined length burst.
For a defined length burst the master can deassert the HBUSREQ signal once
the master has been granted the bus for the first transfer. This can be done
because the arbiter is able to count the transfers in the burst and keep the
master granted until the burst completes.
However it is not a mandatory requirement for an Arbiter to allow a burst to
complete, so the master will have to re-assert HBUSREQ if the Arbiter
removes HGRANT before the burst has been completed.

When will the arbiter grant another master after a locked transfer?
Applies to: AHB
Answer
The arbiter will always grant the master an extra transfer at the end of a
locked sequence, so the master is guaranteed to perform one transfer with
the HMASTLOCK signal low at the end of the locked sequence. This coincides
with the data phase of the last transfer in the locked sequence.
During this time the arbiter can change the HGRANT signals to a new bus
master, but if the data phase of the last locked transfer receives either a
SPLIT or RETRY response then the arbiter will drive the HGRANT signals to
ensure that either the master performing the locked sequence remains
granted on the bus for a RETRY response, or the Dummy master is granted
the bus for the SPLIT response.
See also:
Why is there a 1KB restriction in AHB?
Applies to: AHB
Scenario
1. What is the calculation behind this 1KB boundary.
2. Can we have more than 1KB space allocated to each slave.
Answer
The 1KB restriction you refer to is not a restriction on maximum slave size
but a constraint within AHB that says that a burst must not cross a 1KB
boundary. The limit is designed to prevent bursts crossing from one device
to another and to give a reasonable trade-off between burst size and
efficiency. In practise, this means that a master must ALWAYS break a burst
that would otherwise cross the 1KB boundary and restart it with a non-
sequential transfer, thus:
Address: 0x3F0 0x3F4 0x3F8 0x3FC 0x400 0x404 0x408
Transfer: NSEQ SEQ SEQ SEQ NSEQ SEQ SEQ
There is no upper limit to the slave footprint - ARM PrimeCells, for instance,
are 4KB