ASSERTIONS.
sv Page 1
Question 1: Write a SystemVerilog property that checks if a signal data rises to a h
igh value within 5 clock cycles after the reset signal is deasserted
// Property to check rising edge of 'data' within 5 clock cycles after reset deas
sertion
property check_data_rise_after_reset;
@(posedge clk) disable iff (reset)
(reset == 0) |-> ##[1:5] (data == 1);
endproperty
// Assertion to check if property holds
assert property (check_data_rise_after_reset)
else $fatal ("Data did not rise within 5 cycles after reset deassertion")
;
Question 2:Write a SystemVerilog assertion to verify that the signal data remains st
able (unchanged) for at least 4 clock cycles after the signal start is high.
// Property to check if 'data' remains unchanged for 4 cycles after 'start' is
high
property check_data_stability;
@(posedge clk) disable iff (reset)
(start == 1) |-> ##[1:4] (data==$past (data));
endproperty
// Assertion to ensure that the data stays stable
assert property (check_data_stability)
else $fatal ("Data changed within 4 cycles after 'start' signal went h
igh");
Question 3:Write an assertion that ensures the signal valid transitions from 0 to 1
only after the signal ready has been 1 for at least 3 clock cycles.
// Property to check that 'valid' can only go high after 'ready' has been hig
h for 3 cycles
property valid_transition_check;
@(posedge clk) disable iff (reset)
(ready==1) ##[2:4] (valid==1);
endproperty
// Assertion to ensure the correct transition
assert property (valid_transition_check)
else $fatal ("Invalid transition of 'valid' without proper 'ready' si
gnal");
Question 4:Write an assertion to ensure that at least one of the signals a, b, or c is
high, but never more than one of them is high at the same time.
// Property to check that at least one of 'a', 'b', or 'c' is high, but not mo
re than one
property one_high_at_a_time;
@(posedge clk) disable iff (reset)
(a || b || c) && ! (a && b) && ! (b && c) && ! (a && c);
endproperty
// Assertion to check that property holds
assert property (one_high_at_a_time)
else $fatal ("More than one of 'a', 'b', or 'c' was high simultaneo
usly");
Question 5:Write an assertion that checks that a signal data follows a certain patte
ASSERTIONS.sv Page 2
rn: 1 cycle low, 2 cycles high, 1 cycle low, repeating for 10 cycles.
// Property to check a specific data pattern with delays
property data_pattern_check;
@(posedge clk) disable iff (reset)
(data==0) ##1 (data==1) ##2 (data == 0) ##1 (data==1) ##2 (data==0) ##1
(data==1)##2 (data==0) ##1 (data==1) ##2 (data==0) ##1 (data==1);
endproperty
// Assertion to check if the pattern holds
assert property (data_pattern_check)
else $fatal ("Data pattern did not match the expected pattern over 10 c
ycles");
Question 6:Write an assertion that checks whether the signal data_out gets reset to
zero when the signal reset is asserted.
// Property to check that 'data_out' is zero during reset
property data_out_reset_check;
@(posedge clk) disable iff (!reset)
reset==1 |-> (data_out == 0);
endproperty
// Assertion to ensure 'data_out' is zero when reset is asserted
assert property (data_out_reset_check)
else $fatal ("Data output was not reset to zero when reset was ass
erted");
Question 7:Write an assertion to check if the signal data_valid is synchronized corr
ectly between two clock domains clk_a and clk_b. Assume the signal data_valid_a is i
n clk_a, and data_valid_b is in clk_b. The synchronization between these signals shoul
d be ensured using a 2-stage synchronizer.
// Property to check cross-domain synchronization
property sync_check;
@(posedge clk_b) disable iff (reset)
(data_valid_a == 1) |-> ##1 [data_valid_b == 1);
endproperty
// Assertion to ensure the synchronization
assert property (sync_check)
else $fatal ("Cross-domain synchronization failed: data_valid_a and
data_valid_b are not synchronized correctly");
Question 8:In a FIFO design, write an assertion to ensure that the FIFO's empty sign
al is high when the FIFO is empty and the full signal is high when t he FIFO is full.
Assume that the FIFO is 16 entries deep.
// Property to check FIFO empty and full conditions
property fifo_empty_full_check;
@(posedge clk) disable iff (reset)
(fifo_depth==0) |-> fifo_empty = 1;
(fifo_depth == 16) |-> fifo_full = 1;
endproperty
// Assertion to ensure the FIFO empty/full conditions
assert property (fifo_empty_full_check)
else $fatal ("FIFO empty/full condition failed");
Question 9:Write an assertion that checks if a parallel bus data_bus [7:0] is stable
ASSERTIONS.sv Page 3
for 3 cycles when the signal data_valid is high. The bus should not change during thi
s time, and any change should be flagged as an error.
// Property to check data stability on the bus for 3 cycles
property data_bus_stability;
@(posedge clk) disable iff (reset)
data_valid == 1 |-> ##[2] (data_bus==$past (data_bus, 2));
endproperty
// Assertion to check data bus stability
assert property (data_bus_stability)
else $fatal ("Data bus changed during stable period when data_v
alid was high");
Question 10:In a design, an asynchronous reset signal reset should clear all flip-fl
ops (ff_reset). However, there is a requirement that the reset signal should be deasse
rted for at least 3 cycles before the registers are allowed to change their state. Wri
te an assertion to ensure this condition.
// Property to ensure reset is deasserted for 3 cycles before registers ch
ange
property reset_deassertion_check;
@(posedge clk) disable iff (reset)
reset==0 |-> ## [3] (ff_reset == 0);
endproperty
// Assertion to ensure the reset deassertion timing
assert property (reset_deassertion_check)
else $fatal ("Reset was deasserted too soon, not enough cycle
s for registers to settle.");
