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HW 2

This document provides the homework assignment for CS M151B/EE M116C, due on January 21, 2015. It includes reading assignments from the textbook and appendix covering finite state machines. It lists 8 problems involving analyzing the consequences of faults in a MIPS processor's ALU, designing logic circuits for an adder and 4-bit down counter, multiplying without a multiply instruction, and converting instructions to machine code.

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197 views1 page

HW 2

This document provides the homework assignment for CS M151B/EE M116C, due on January 21, 2015. It includes reading assignments from the textbook and appendix covering finite state machines. It lists 8 problems involving analyzing the consequences of faults in a MIPS processor's ALU, designing logic circuits for an adder and 4-bit down counter, multiplying without a multiply instruction, and converting instructions to machine code.

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tinhtrilac
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CS M151B/EE M116C - H omework #2, Due 01/21/2015

Reading Assignment:
Readings from hw #1 Appendix B: pp. B-26 B-37, Chapter 4: pp. 300-330
Appendix B: pp. B67-B71 (reviews some basics of finite state machines)
(ignore the paragraph on Verilog)
Appendix D: pp. D3-D27

Problems:
(1)-(2)
(3)

(4)

B.24, B.25 (on page B-83).


The single cycle implementation of the MIPS processor uses for the main ALU the
implementation shown in Figures B.5.10-B.5.12 (pp. B-33 B-36) in the book. Due to a circuit
malfunction, the CarryIn signal to the least significant bit (see Fig.B.5.11) is always zero. The
rest of the circuitry of the ALU and the rest of the processor operates normally.
Explain in full detail what will be the consequences of this fault when the processor executes
programs how will it change the behavior of the processor as observed
by a user/programmer who does not know a nd does not care how t he processor is
implemented internally? Be sure to clearly identify each and every consequence of this fault.
Consider the ALU shown in Figure B.5.12 (page B-36). What function will this ALU perform if the ALU
control lines are set to 0101. Explain your answer.

(5)

(6)
(7)

(8)

LH

Consider the MIPS ALU implementation shown in Figures B.5.10-B.5.12 (pp. B-33 B-36). A change in the
implementation is made to Figure B.5.11: the Less input to the ALU3 cell is set to 1 instead of 0. Explain
in detail what will be the consequences of making this change when the processor executes programs (i.e.,
how will it change the behavior of the processor as observed by a u ser/programmer who does not
know a nd does not care how t he processor is implemented internally?).
Draw a l ogic circuit of an adder of two 4 -bit numbers. Your design should be simple and modular.
Using the circuit from problem 6 as a building block, show the design of a 4-bit counter that counts down.
The only external input to this circuit is the clock. The output four bits continuously follow
the sequence: . . . , 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, . . .
Your goal is to minimize the circuitry needed in addition to the module from problem 6.

(for practice)
Instead of using the multiply instruction, it is possible to multiply using shift and add instructions. This may
actually be faster when multiplying by a small constant. Suppose we want to store five times the value of
register $16 into register $17, ignoring any overflow that may occur. Show a minimal sequence of MIPS
instructions for doing this without using a multiply instruction.
Convert your program to machine code. Assume that your program is to be placed in memory starting
address 128. Write the machine code in the format shown in class, with the address of each instruction to
the left of the instruction. Note that all values should be presented in binary.

Winter 2015

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