UNIVERSITY OF EDINBURGH

COLLEGE OF SCIENCE AND ENGINEERING

SCHOOL OF INFORMATICS

INFR08018 INFORMATICS 2C - INTRODUCTION TO

COMPUTER SYSTEMS

Tuesday 10 th December 2013

14:30 to 15:30

INSTRUCTIONS TO CANDIDATES

1. Answer Parts A and B. The multiple choice questions in Part A are

worth 50% in total and are each worth the same amount. Mark one
answer only for each question — multiple answers will score 0. Marks
will not be deducted for incorrect answers. Part B is worth 50% and
contains TWO questions. Answer ONE of them.

2. Use the special mark sheet for Part A. Use a script book for the ques-
tion from Part B that you answer.

3. Calculators may not be used in this examination.

Convener: J. Bradfield
External Examiner: C. Johnson

THIS EXAMINATION WILL BE MARKED ANONYMOUSLY

 Part A
ANSWER ALL QUESTIONS IN PART A. Use the special mark sheet.

1. Take the 8-bit word with hex value 9b, logically shift it right 2 bits and ‘and’ the
result with hex value f5. What is the decimal value of the final result, interpreting
it as a 2’s complement number?

(a) −21
(b) −20
(c) 36
(d) 100
(e) 220

2. What C code does the following piece of MIPS assembly code correspond to?

l2: bne $s0, $s2, l1

and $s3, $s1, $s2
or $s2, $s1, $s3
j l2
l1:

(a) while (s0 == s2) { s2 = s3 & s1; s3 = s2 | s1; }

(b) while (s0 == s2) { s3 = s1 & s2; s2 = s1 | s3; }
(c) while (s0 <= s2) { s2 = s3 & s1; s3 = s2 | s1; }
(d) while (s0 != s2) { s2 = s3 & s1; s3 = s2 | s1; }
(e) while (s0 != s2) { s3 = s1 & s2; s2 = s1 | s3; }

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3. Consider running the C program fragment:

int x[] = {1,3,5,7,9};

int* y;
y = &x[0] + *(x + 1);

What is the value of *y afterwards?

(a) 1
(b) 2
(c) 3
(d) 4
(e) 7

4. A Half Adder circuit has two inputs a and b and two outputs – a sum output
s and a carry output c. The two-bit binary number c s is the sum of the 1-bit
binary numbers a and b. What are correct Boolean formulas for s and c?

(a) s = a + b and c = a.b

(b) s = a.b + a.b and c = a + b
(c) s = a.b and c = a + b
(d) s = (a + b).(a + b) and c = a.b
(e) s = (a + b).(a + b) and c = a.b

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5. A synchronous register file component can be designed to have various different
read and write behaviours, as follows.

• Data from the register indicated by the read address 1 input appears on the
read data 1 output port
A: shortly after the positive edge of the clock input to the register file, or
B: a short delay after the read address 1 input has been set up.
• Data on the write data input is written to the register indicated by the write
address input either
C: on the positive edge of the clock input, when at that time the regWrite
input is a logic 1, or
D: whenever the regWrite input is a logic 1.

Which pairs of these behaviours are expected of the register file component used
in the single-cycle and multi-cycle CPU architectures discussed in the course?

(a) A and C.
(b) A and D.
(c) B and C.
(d) B and D.
(e) None of the above.

6. Which hazards are present in the following piece of code, on the 5-stage pipelined
MIPS processor discussed in the course? Assume that no steps have been taken
to reduce bubble sizes, such as introducing data forwarding.

add $s1, $s2, $s3

beq $s2, $zero, label
sub $s4, $s2, $s3
and $s5, $s1, $s2
label:

(a) Structural hazard only

(b) Control hazard only
(c) Data hazard and control hazard
(d) Data hazard only
(e) Data hazard and structural hazard

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7. Which of the following does not occur when a MIPS CPU executes a syscall
instruction?

(a) Interrupts are disabled.

(b) The processor is switched into Kernel mode.
(c) The current Program Counter value is saved to a special register.
(d) The values in registers $s0 to $s7 are saved on the program stack.
(e) Control flow is transferred to a specific address in the operating system code.

8. Consider a fully-associative cache with 1024 blocks/lines where each block con-
tains 16 64-bit words. How many bits are needed for the tag field, assuming
addresses are 48-bit and memory is byte addressable?

(a) 7
(b) 31
(c) 34
(d) 41
(e) 44

9. In which of the following situations do we say that a page fault occurs?

(a) A memory transfer instruction tries to access an address which is not in the
cache.
(b) A memory transfer instruction tries to access an address which is not in
physical memory.
(c) An address is accessed which is missing from the TLB address cache.
(d) A process requires disk I/O.
(e) A process is suspended due to receiving a kernel timeout.

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10. Which of the following does not happen when DMA (Direct Memory Access) is
used for data transfers?

(a) The processor is interrupted by a peripheral controller that wants a data

transfer.
(b) The processor sets up DMA registers (e.g. address, length) which describe
the transfer.
(c) The DMA controller transfers data between memory and a peripheral con-
troller.
(d) An arbiter circuit controls access by the processor and DMA controller to
the memory bus.
(e) During a transfer, the processor repeatedly polls the DMA controller until
the transfer is complete.

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 Part B
ANSWER ONE QUESTION FROM PART B.

1. (a) Convert the following C code into equivalent MIPS assembly code.
int a[10];
int b[10];
int i;
int sum;
...
i = 0;
sum = 0;
while (i < 10) {
sum = sum + a[i] * b[10-i];
i++;
}
When your code starts, assume that the base address of array a is held in
register $s0, the base address of array b is held in register $s1, integer i is
held in register $s2 and integer sum is held in register $s3. Integers are 32-
bit and memory is byte addressable. You are free to use any other registers
as you wish. For multiplication, use the instruction
mul d s1 s2
which places into register d the lower 32 bits of the product of registers s1
and s2 .
Please comment your code well to ease understanding. [18 marks]
(b) Express as an 8-digit hex number the 32-bit floating-point encoding of the
decimal number 85.0 following the IEEE 754 floating-point standard. Re-
member, for 32-bit floats, the exponent takes up 8 bits and the exponent
bias is 127. [8 marks]
(c) Explain how MIPS handles exceptions/interrupts. Describe which tasks are
handled by hardware and which by software. [10 marks]

QUESTION CONTINUES ON NEXT PAGE

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 QUESTION CONTINUED FROM PREVIOUS PAGE

(d) Consider the familiar multi-cycle implementation of MIPS used in the course.
The datapath is shown in the figure below.

We need to add the instruction lui r, imm (load upper immediate) which
loads a constant (imm) into the upper 16 bits of register r and sets the
lower 16 bits to 0s. Describe the changes needed in the datapath (includ-
ing changes inside the sub-blocks shown in the figure) and give a detailed
description of what task is performed in each cycle of execution for this
instruction. [14 marks]

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2. (a) Write C code for a function
int countchar(char c, char* s)
which counts and returns the number of occurrences of character c in string
s. Assume that the string s is null terminated.
Please add comments to your code explaining the main components. [14 marks]
(b) How does a pipelined processor differ from a multi-cycle processor such as
discussed in class? Why can pipelining improve processor performance? [8 marks]
(c) A J-K flip-flop is a 1-bit clocked memory element with data inputs J and
K, a clock input Ck, and an output Q. It has the following behaviour on
the positive edge of Ck :
• If J = 1 and K = 0, the Q output is set to 1.
• If J = 0 and K = 1, the Q output is set to 0.
• If J = 0 and K = 0, the Q output retains its previous value.
• If J = 1 and K = 1, the Q output is set to the inverse of its previous
value.
Draw a circuit diagram giving an implementation of a J-K flip-flop that uses
a D flip-flop and combinational logic gates. [12 marks]

QUESTION CONTINUES ON NEXT PAGE

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 QUESTION CONTINUED FROM PREVIOUS PAGE

(d) Consider a simple direct-mapped cache with 4 lines, each containing 4 bytes
of data and a tag field of appropriate size for 6-bit addresses. Assume that
the cache is initially empty and that memory is byte-addressable.
For the following pattern of cache accesses:
Access Number Address
1 11 0011
2 10 1010
3 01 1101
4 10 1011
5 10 0011
6 01 1100
draw up a table of form

Access Number Tag Index Line 0 Line 1 Line 2 Line 3 Hit/Miss

1
2
3
4
5
6
that summarises the contents of the cache after each access. In the Tag and
Index columns, write the decimal values of the tag and index components
of each access address. Then, in each row, if Line i is occupied with the
memory block with tag t, write the decimal value of t in the column for Line
i, and record in the Hit/Miss column an H or an M to indicate whether the
access is a hit or a miss. If a line is empty after some access, leave the entry
for that line and access number blank. [16 marks]

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