2012 EEsof

2012/10/23

Volume 1

Time

Title

Speaker

Title

Speaker

Title

Speaker

Registration and Welcome

0830-0900

Juergen Hartung
0900-0940

Comprehensive RF Microwave Solutions for Wireless Applications

Agilent

Move to
Tracks(10)

Track A(RF and Mixed Signal IC Design)

Track B(Wireless and Digital system design)

0950-1040

A1: Integrated ElectroRick Poore

Thermal Solution Delivers
Thermally Aware Circuit
Agilent
Simulation

B1: Validating of
Ming-Chih Lin
Communication System
Design in C, Matlab, HDL
Agilent
Codes with SystemVue

1040-1130

A2: A complete Designer- Shuang Cai

Oriented Device Model
Verification Solution for
Agilent
Advanced Technology

B2: FPGA Simulator Work

with SystemVue
Aldec

Break & Product Fair

1130-1150

1150-1230

A3: Comprehensive
Hsieh-Hung Hsieh
Milimeter Wave Solutions
for TSMCs 60GHz CMOS
PhD,TSMC
Reference Design Kit

B3: The Agilent EEsof

Integrated EDA Design
Flow for High Speed
Digital Designers: PreLayout, Post-Layout,
Measurement

JS Wu
A4: WIN PDK in ADS
Environment Introduction
WINSEMI

1400-1440

A5: Addressing the RF

Needs in Nano-Scale
Wireless Platforms

Jason Chen

Agilent

Juergen Hartung
1500-1530
A6: Complete mm-Wave
Front-to-Back RFIC
Design Flow

Agilent

1530-1600

1650-1700

Agilent

B4: The Signal Integrity

and Power Integrity
Analysis by ADS

Craig Wang

B5: Power Integrity

Analysis for High Speed
PCB Design Using ADS

Eric Kuo

Silicon Motion

Gemtek

C4: System-Level Design Keven Chang

& Verification for Flexible
OFDM with SystemVue
Agilent
C5: Automating On-Wafer Abby Shih
Measurements with the
New Agilent IC-CAP
Agilent
WaferPro

Break & Product Fair

1440-1500

1600-1650

Heidi Barnes

Lunch

1230-1330

1330-1400

Track C(Test measurement implementation with

Simulation technology)

A8: Real World CMOS PA

Jason Chen
Design for Mobile
Applications with
Advanced Simulation
Agilent
Technologies

B6: Using ADS Momentum

Jack Hu
to Differentiate Signal
Integrity Issue Happening
on Board Level or Chip
TomTom
Level
B7: Consideration of High- Nick Chin
Speed Connector's Signal
Integrity with EMPro and
JETCONN
ADS
B8: SI, PI and EMI in High Ming-Chih Lin
Speed Digital Design with
ADS
Agilent

Survey & Lucky Draw

Yoshiyuki Yanagimoto

C6: GaN Doherty Amplifier

Design Using XParameters

Agilent

Comprehensive RF
Microwave Solutions for
Wireless Applications

Dr. Juergen Hartung

RFIC Product Marketing &
Foundry Program Manager
Agilent EEsof

October 2012

Agenda
Introduction RF/MW Design Challenges
Agilent EEsof RF/MW Solution

Device Modeling
MMIC
Silicon RFIC
3D RF Components
RF Modules

Whats New in ADS 2012

Summary & Outlook

1-1

RF/MW Design Challenges The Tablet Example

Data
Wi-Fi 802.11a/b/g/n

Communications
4G LTE

possible: 802.11ac

Also: LTE-Advanced, MIMO

Location
A-GPS
possible: Galileo, Beidou, GLONASS

HSPA, HSPA+
DC-HSDPA

Personal Connectivity
Bluetooth v4.0

Also: GSM/EDGE, WCDMA,

Multi-Standard Radio (MSR)

possible: 802.11ad/WiGIG

o Increasing Integration Multiple different complex systems placed in close proximity

o Increasing design complexity and compaction
o Concurrent design teams across companies
o Verification across design domains (IC/package/board)
3

Increasing RF content in a Tablet

Pictures are courtesy of chipworks

Murata/Peregrine SP6T
Rx diversity switch module

Tablet includes 7 PA modules:

TriQuint Quad-Band GSM
Avago Band 4 LTE

Triquint
GSM PA module

Avago Band 17 LTE

Skyworks Band 5 UMTS/HSPA
Skyworks Band 8 UMTS/HSPA

Skyworks 77468-16
W-CDMA/HSDPA/HSPA+
PA and duplexer module

Avago Band 2 UMTS/HSPA

Murata/Panasonic Dual-Band

Avago
Band 4 PA module

RF Modules require
further integration!

1-2

Integration-dependent design challenges

Smaller, cheaper, more integration, lower power consumption
Small-Scale Chips + Module

Single Large-Scale Silicon Chip (SoC)

if it can
be done in
silicon, it
WILL be
done in
silicon

SMT
components
or integrated
on IPD chip
Embedded
passives

Picture is courtesy of chipworks

More functionality
on chip
Additional chips
III-V technologies
or Silicon RFIC

New packaging
techniques
explored (TSV,
3DIC, PoP, etc.)

Higher levels of integration, lower cost

Low breakdown voltage, Low device
gain, High loss on-chip inductors,
linearity issues, poor RF models

SMD Component Designer

L, C, Filter, Active Devices

RF/MMIC
Designer
PA, LNA

RF SiP / Module
Designer
PAM, TxRx

Antenna Designer
SMD Ant, A/D Ant

Connector Designer
SMA, USB, HDMI

GaAs

Silicon

RF/MW Design Segments Application

perspective

Package
Designer
QFN, BGA

RF Board Designer *
Radio module

Modeling Engineer
GaAs, Si, SiGe,
GaN, LDMOS

RF SoC Designer *
Transceiver IC

System Integrator
Tablet, Handset, Radar, Base
station,
*) Pictures are courtesy of chipworks

1-3

RF/MW Design Segments Flow perspective

MMIC

RFIC

RF Module
RF SiP

RF Board

Design/Implementation Challenges per Segment

Complete characterization of
component level designs
3

IC design enablement beyond

broad and qualified PDK support
2

1
Accurate device models
for emerging technologies

1-4

Integration challenges with

multi-technology designs

1 Accurate Device Models for Emerging

Technologies

NeuroFET Model
(Extract in IC-CAP, Simulate in ADS)

Artificial Neural Network Measurement-based FET Model

Complete Solution: data acquisition, extraction and simulation in ADS)
Equations and derivatives are infinitely continuous
Accurate 2nd, 3rd, Nth order effects
Robust RF & DC convergence
Symmetric: switch, mixer & amplifier applications (Vds<=0)
Measured vs. Simulated
Better than current data-based models

Improved convergence
Improved small-signal distortion
More accurate S-parameters vs. bias
More accurate PAE
More accurate than Compact Models
Applications: GaN, InP, GaAs

10

1-5

Fund

2nd
3rd
4th5th

Design/Implementation Challenges per Segment

Complete characterization of
component level designs
3

IC design enablement beyond

broad and qualified PDK support
2

1
Accurate device models
for emerging technologies

Integration challenges with

multi-technology designs

11

2 MMIC/RFIC Design Enablement

12

1-6

Complete ADS Desktop Design Flow

Agilent EEsof Chip/Module/Board Design

MMIC

Most widely used MMIC Design Platform!

13

ADS 2011 PDK Support GaAs / GaN

G28V3

G28V4

G40V4

G50V3

under dev.

InGaP HBT - P2

InGaP HBT D1

ED02AH

D01PH

FD30

FD25

TQTRx

HP07

TQHiP

D01MH

TQHBT3

PH25

InP SHBT1 InP DHBT2

TQPED

PPH25X

H01U-xx H02U-xx MP15-01 PL15-xx

D007IH

TQP13

HB20M

THz Schottky
Diode

GaN HEMT
0.25um

GaN HEMT
0.50um

DH15IB

TQP15

TQP25

HB20P

TQRLC

TQBihemt

BES100

PP10-xx PP15-xx PP25-xx PP50-xx PS50-xx PH50-xx PD50-xx

Paper: WIN PDK for ADS, by JS Wu (WINSEMI)

1-7

>40

Getting started with MMIC Design

MMIC Design Seminar Material

Seminar Videos
Presentations & Demos
ADS projects
Hands-on Workshops
X-Parameters

http://www.agilent.com/find/eesof-mmic-seminar

ADS2011 Complete MMIC-Module-MultiTech

Design - JS
Page 15

ADS 2012 Electro-Thermal Simulator

Applications: high power RFIC / MMIC

design

Deliver thermally aware circuit

simulation results by including effects
of on-chip temperature rise

Include effects of package and PCB

Easy to set up and use from within the

ADS environment

Works with all simulation types:

DC, AC, SP, HB, Transient, Envelope

ADS Schematic

ADS Layout

Integrated Thermal Solver

Paper: Integrated Electro-Thermal Solution Delivers

Thermally Aware Circuit Simulation, by Rick Poore

16

1-8

2 MMIC/RFIC Design Enablement

17

ADS for Silicon RFIC Applications

Small-scale RFIC

Si RF Components
Front-end modules (PA, Mixer, LNA-Mixer) or Antenna switches in
CMOS-SOI starting to displace discrete GaAs power components

Si-MMICs
Silicon components and transceivers for millimeter wave products,
like Optical Networks ( 10 to 40Gb/s), Automotive Collision
Avoidance, 60GHz WLAN

IPD
Integrated Passive Device (IPD) silicon process technology for
the production of passive devices such as baluns, filters, couplers,
and diplexers that are used in portable, wireless and RF
applications

LDMOS
RF power transistors used for basestation, broadcast /
ISM and aerospace & defense applications

18

1-9

ADS 2011 Extending towards Silicon RFIC

Design
Schematic Entry
Simulators
System
Circuit
EM

Data Display
Layout
DRC/LVS
DFM support

Major (& continued) improvements with ADS 2011

19

Agilent Technologies Advanced Design System Selected by

Sivers IMA for Front-to-Back Silicon RFIC Implementation

We are expanding our peak-performance millimeter wave product

portfolio toward silicon-based, proprietary MMIC designs to leverage the
advantages of higher integration and reduced cost,
said Christer Stoij, chief technology officer at Sivers IMA.
We selected ADS for the complete front-to-back implementation of
corresponding devices because it delivers proven RF circuit
simulation, integrated EM solvers and RF-relevant backend support.
ADS is designed for our type of application, allowing us to introduce new
unique products for E-band and V-band radio links, with full control of the
millimeter wave architecture.
20

1-10

ADS 2011 RFIC Design Flow Status

Inputs from System-level

Proven ADS front-end solution for RFIC

Schematic Entry

Major advantages through integrated EM

ADS layout provides all relevant capabilities

Circuit Design &

Simulation

Automatic Metal Fill to be added

Assura & Calibre DRC support for sign-off

Layout

ADS DRC covers most recurring checks

ADS LVS natively supported without need

for dedicated rule files

DRC/LVS

Calibre LVS supports complements offering

EM Extraction

EM-based extraction through Momentum

Parasitic Extraction support to be added

GDSII or SOC integration

Paper: Complete mm-Wave front-to-back

RFIC Flow, by Juergen Hartung

21

ADS 2011 PDK Support SiGe / BiCMOS / IPD

Full Front-to-Back PDKs
BiCMOS8HP

Front-end PDKs
CMRF7SF

CSOI7RF

CSOI7RF

BiCMOS8HP

BiCMOS5PAe

under dev.

SG25H3

SG13S

SG25H1

SG13G2

BiCMOS9MW

SGB25V

under dev.

under dev.

TSL018

CA18HB

CA18QC

SBC18H3

CMOS065 RF

H9SOI RF

BiCMOS7RF

BiCMOS9MW

BiCMOS6G

H9SiGe

SBC18HA SBC18H2 SBC18HXL

CS13Q1

under dev.

CM013RF
IPD 0.18um
CM090rf

New
High-Q IPD

22

1-11

018CMOS

SIGE018

CM055

ADS 2011 RFIC Design Flow Licensing & Bundles

Inputs from System-level

ADS Platform
Schematic Entry
Circuit Design &
Simulation

ADS Core
(incl. Schematic Entry, Linear
Simulation, Optimization, Monte
Carlo, Data Display, )
HB, Tran, Envelope Elements

HB

Circuit
Sim

ADS Layout Element

Layout

Layout

Momentum

Momentum

Layout

DRC/LVS

EM Extraction

W2205
W2214
Bundle
Bundle
ADS Core ADS Core

incl. DRC & LVS,

Connectivity-driven layout, )

Momentum Element

New
GDSII or SOC integration

23

ADS 2012 New Via Simplification for faster EM

Layers are generated for EM only
Can be viewed in 3D Viewer
Can be used in combination with standard layers for EM simulation

24

1-12

2 MMIC/RFIC Design Enablement

25

Agilent EEsof RFIC solutions within Virtuoso

SystemVue Verification

Inputs from System-level

Component Options

GoldenGate FCE

Schematic Entry

Broadband
SPICE
Model
Generator

S-parameter

Momentum Simulator

RF-ESL Analysis &

Design support

GoldenGate RFIC Design and Verification

Circuit Simulation
GoldenGate

Inductor & Passive

Component Design

Layout

Package & Bond

wire modeling
QFN Designer

DRC/LVS

Parasitic Extraction

GDSII or SOC integration

26

1-13

New GoldenGate 2012.10 release

27

TSMC 60 GHz RDK Example

Covers complete RF Design Flow

Top-down ESL architecture verification

Verify at every level vs. consistent 802.11ad

TX/RX references

RFIC circuit simulation & verification

Full characterization of complete RF transceiver

prior to tape-out

EM analysis & verification

Enable EM analysis early and often through

integrated solvers

Add off-chip effects & components in overall

verification

Addressing integration issues early in the

design cycle

Paper: Addressing the RF needs in nanoscale Wireless Platforms, by Jason Chen

28

1-14

Paper: TSMC 60 GHz

reference design kit, by
Hsieh-Hung Hsieh (TSMC)

Design/Implementation Challenges per Segment

Complete characterization of
component level designs
3

IC design enablement beyond

broad and qualified PDK support
2

Accurate device models

for emerging technologies

Integration challenges with

multi-technology designs

29

3 EMPro 3D EM Modeling Environment

Interactive, Intuitive, Efficient, 3DEM design
Environment
Full Wave 3D EM FEM and FDTD Simulation
Technologies
Parameterize 3D EM components for cosimulation & optimization in ADS
Transfer ADS Layouts to EMPro for additional
3D-EM simulation
Full scripting (Python) and parameterization
capability
Windows & Linux
Paper: The best 3DEM Tool for ADS,
by Agilent

30

1-15

New Release: EMPro 2012

Electromagnetic Professional Software
Key New Features:
New level of integration with Advanced
Design System
Common database allows 3D
components built in EMPro to be
placed on ADS schematics and
layout directly.
New low-frequency analysis algorithm
Improves accuracy <100 MHz to DC
Accurate, stable results at DC & lowfrequencies required for higherfrequency circuit simulations.
50% faster FEM meshing technology

31

NEW: Enhanced EMPro-ADS Integration

Common Database
ADS Layout (3D View)

EMPro 3D Design

ADS Schematic

32

1-16

NEW: FEM DC/Low Frequency w/iterative solver

Legacy solver (wo LF enhancement)
cannot converge below 0.1 GHz.
5 hours @ 1MHz and aborted.

Rollback to 1st order,

direct solver.
1.5 hour per freq

Iterative solver converges beyond 1 kHz, 3550 iterations, 10 min per freq
33

Design/Implementation Challenges per Segment

Complete characterization of
component level designs
3

IC design enablement beyond

broad and qualified PDK support
2

1
Accurate device models
for emerging technologies

34

1-17

Integration challenges with

multi-technology designs

4 Interoperable RF Module / SiP Co-Design Flow

35

Integration Challenges with Multi-Technologies

Enable
end-to-end
simulation

Behavioral
model for PA IC
(X-parameters)

Multiple ICs on
different fabrication
technologies
Passive EM
Simulation of
Entire Laminate

Model Package,
solder bumps,
bond wires

Thermal
Considerations
Model
connector
Amalfi AM7802
PA Front End Module

36

Chip, module,
board
interactions

Paper: Real world CMOS PA design form mobile applications

with advanced simulation technologies, by Cheng-Cheng Xie

1-18

Integration Challenges with Multi-Technologies

Behavioral
model for PA IC
(X-parameters)

Enable
end-to-end
simulation

Multiple ICs on
different fabrication
technologies
Passive EM
Simulation of
Entire Laminate

Model Package,
solder bumps,
bond wires

Thermal
Considerations
Model
connector
Amalfi AM7802
PA Front End Module

Chip, module,
board
interactions

37

Continues changes requires Interoperable Flows

Typical PA Module

Possible next steps

and new constraints like board-driven chip (re-)design.

38

1-19

ADS 2012: Side-by-Side EM Simulation Setup &

FEM Analysis
analyze electromagnetic
interactions between ICs of
differing technologies and
interconnects, wire bond and
flip-chip solder bumps in
typical in multi-chip RF PA
modules.

39

IC Interoperability through OpenAccess

Agilent is a member of Si2, OA Coalition and IPL Alliance
ADS 2011 moved to OpenAccess as industry-standard database

40

1-20

Virtuoso Export To EMPro

Transfers shapes, materials, ports from
Virtuoso into EMPro 3D modeler
Allows using both FEM and FDTD solvers

41

Board/PKG Interoperability through ODB++

Board/Packag
e Enterprise
Tools

ODB++

High
Capacity
Layout PreProcessor

42

1-21

ADFI

ADS

Amkor Package Design Kit for ADS

Predict Packaged Performance in Minutes
Configure QFN package

43

Vendor Component Library

GSM/DCS band filters
use many SMT parts
from Murata and TDK
All SMT parts are 0201
type
Download and use ADS
component library from
the vendors website

44

1-22

Whats New in ADS 2012 Main focus areas

New Technologies
Side-by-Side FEM & DC/LF Solution
Electro-Thermal Simulation
NeuroFET Model

Usability
Easily Share workspaces (Archive/Unarchive)
Docking Windows
Search & Navigator
3D EM Components Almost unbelievable Integration
Layout Flight-lines replace wires in layout

45

ADS 2012 User Interface Improvements

Component Search

Layer Visibility
Net Navigator

Comp Information

Comp Information

46

1-23

New Docking Windows

Can
Can stack
stack windows
windows
Can
Can tab
tab the
the windows
windows
Or
Or easily
easily drag
drag window
window
into
place
into place

Can
Can float
float the
the window
window
Or
Or easily
easily drag
drag window
window
into
into place
place

47

New Navigator Tool

Displays all the objects in a design
Traces, paths, rectangles, polygons, circles, pins,
components, cell instances, etc.
Shows all the nets in a design
Shows all the objects through the entire design
hierarchy
Cross selection/highlighting between design and
Navigator
Auto Zoom feature automatically windows in to the
target objects
Works in both Layout and Schematic
Easily locate objects, even in complex designs

48

1-24

New Navigator Tool

Cross
Cross selection
selection between
between
Navigator
Navigator and
and design
design

Easily
Easily filter
filter what
what
is
visible
is visible in
in
Navigator
Navigator

Expand
Expand to
to see
see full
full design
design hierarchy
hierarchy

49

Powerful New Search Utility

Great for
Finding specific objects in large, complex designs
Quickly make edits to objects fitting a specific criteria

Features

Easily locate specific design objects

Searches through the entire design hierarchy
Type search strings in directly, or use search wizard
Intuitive search language supports Boolean search strings
Auto zoom opens required cell, zooms then selects object
Use the search results to easily visit and edit specific objects

50

1-25

Whats New in ADS 2012 New Capabilities

User Interface & Design Management

Simulation Improvements

Docking & Tabbed Windows & Dialog Boxes

Faster Linear Speed

Component Search: Find objects in the design hierarchy

Net Navigator to confirm nodal connectivity

Improved Convergence/Sweep behavior

Flexible Archive & Unarchive: share parts of your workspace

Dozens of additional Schematic & Layout UI refinements

Parallel Computing

Support for 3rd party Design Management/Version Control Tools

(Cliosoft)

Automation of Linear Network Collapser in Linear Controller

Ignore and Continue if encounters a convergence issue

Faster Transient GPU

Simulation Manager to setup and control parallel sims

With Transient/Convolution 8-pack license

Layout

Flight-wires replaces wires in layout

Power Amplifier Design Applications

Improved and Flexible Connectivity modes

Enhancements to the Load Pull DesignGuide: Added mismatch

simulation to indicate device or amplifier sensitivity to load VSWR
or phase angle.

Enhancements to the Amplifier DesignGuide: Extensive update

makes it easy to see amplifier performance at a specific output
power or a specific amount of gain compression.

Multi-layer Interconnect creation

Lock components to fixed position

Dimension-Line Improvements

Direct mouse entry of array spacing

ADS Desktop LVS Improvements

Connection Manager Instrument Support

Layout Command Line Editor

copy and oversize simple & complex structures

Cookie Cutter

Remove all wires in layout

ADS Support for PNA-X N524x series and the new PNA N522X

51

Improvements to Layout Connectivity

Overview
Connectivity better reflects users intent
User selectable connectivity modes
Better display of missing or incorrect connections
More user control over connectivity
Easier editing of connectivity information
New
New Flight
Flight Wires
Wires

New
New Copy
Copy and
and Oversize
Oversize Utility
Utility

Retain
Retain individual
individual shapes
shapes
or
or merge
merge objects
objects

52

1-26

New
New Navigator
Navigator docking
docking
window
provides
window provides easy
easy
browsing
browsing of
of nets
nets
Highlight
Highlight complete
complete nets
nets
Highlight
Highlight individual
individual objects
objects
attached
attached to
to net
net
Show
Show complete
complete physical
physical
interconnect
interconnect associated
associated
with
with aa net
net

ADS 2012 Support for Version Control Software

Cliosoft SOS via ADS

53

ADS 2012 High Speed Digital

Mid-channel repeater and opto link channel
simulation based on IBIS AMI
New on Sept CPL!
W2312 Transient Convolution Distributed
Computing Eight-packs September CPL
W2324 High Capacity Layout Pre-processor
IBIS 5.1 and IBIS 5.2 support
Via drawing utility
Enhanced Net Explorer
S-parameter port names and differential pairings,
enhanced symbol generation
Built-in DesignGuides, DesignKit, and Examples
(SI and PI)
HSPICE Compatibility s_element support

54

Paper: The Agilent EEsof Integrated Design Flow

for High Speed Digital Designer, by Heidi Barnes

1-27

Key RF/MW Technology Investments

Wireless Verification
LTE-A Library
802.11ac/ad/n Library
Radar Library

Circuit Simulation
Complete Flow

Physical Modeling Modeling

Multi-Technology

Layout

Integration

Device (III-IV, Si)

Performance

Manufacturing Flow

3D Multi-layer Planar

NeuroFET/GaN

Convergence

Desktop DRC & LVS

Full 3D EM

Packaging

Multi-Technology

Behavioral Modeling Nonlinear Stability

Parallel Computing
X-Parameters

Thermal

Model Verification

Interoperability

Packaging

OpenAccess

Interconnect

Interoperable PDKs

3D passives

Integration with
IC/PCB frameworks

Usability Innovations
Circuit Simulation
EM-Circuit Co-Simulation
Interconnect Design
Design Management
Optimization Cockpit

55

Comprehensive RF Microwave Solutions

for Wireless Applications

Summary
Advanced RF design and simulation support
with industry-leading RF simulation speed
and capacity

Best-in-class modeling solutions for

passives, interconnects, packaging and
active devices

Unique RF & mm-Wave design support

Access to scalable system-level solutions
from algorithm development through RF
architecture exploration

Interoperable solutions for RFIC / SiP /

Module / Board co-design

Leverage the most complete RF EDA

portfolio for your next-generation products!

1-28

Key benefits
Best-in-class RF fidelity among todays baseband/PHY environments,
which allows baseband designers to virtualize the RF and eliminate excess
margin
Superior integration with test accelerates real-world maturity and
streamlines your model-based design flow, from architecture to verification
World-class reference IP puts Agilent instrument-grade interoperability and
Layer
1 compliance inside your block diagram, before you have hardware
Unified, open, polymorphic modeling simplifies tool flow, reduces
department costs and supports a customizable, vendor-neutral
environment
Priced for networked workgroups to maximize design re-use and capitalize
on baseband and RF synergies

Integrated Electrothermal Solution

Delivers Thermally-Aware
Circuit Simulation
Rick Poore
Principal Engineer, R&D
Agilent Technologies

Marc Petersen
Product Manager
Agilent Technologies

Agenda
Introduction
Thermal Problems in RFIC/MMIC Design
Solutions: Traditional Approaches
Solutions: A New Approach
Case Study
MMIC PA Design Example
Electro-Thermal Simulation
Thermal and Electrical Results
Conclusion and Q&A

Copyright Agilent Technologies 2012

2

2-1_1

The Problem:
Thermal Effects Impact RFIC/MMIC Design
High Power Devices
+ High Level of Integration
= On-Chip Temperature Rise

IC performance depends on device

temperature

Device temperature depends on:

Power dissipation
Layout position
IC / packaging material thermal properties

This is a nonlinear problem

Thermal conductivities vary with temperature!

????

Copyright Agilent Technologies 2012

3

Traditional Approach:
Self-Heating Models
Many transistor models now include
self-heating effects
Requires accurate extraction of thermal
parameters RTH, CTH
Does not include thermal coupling
between transistors
Does not include impact on nearby
passive components
Does not include impact of packaging

Copyright Agilent Technologies 2012

4

2-1_2

Traditional Approach:
Stand-alone Thermal Solvers
Requires user to manually transfer
layout and expand to 3-D
heat sources locations
power dissipation values
computed device temperatures
and perform any required iteration

Copyright Agilent Technologies 2012

5

Traditional Approach:
Equivalent RC Thermal Network
Extract thermal RC network from
FEM data, add to schematic
Must be re-extracted for any layout
change
Requires device models to have
thermal nodes
Large device count make cause slow
extraction of RC network
Large thermal networks may cause
significant slowdown
Does not account for nonlinear thermal
properties

Copyright Agilent Technologies 2012

6

2-1_3

Thermal Equation
The thermal problem

c and N are both functions of temperature and spatial location

(material)
g is a function of temperature, time and spatial location
(electrical devices)

Copyright Agilent Technologies 2012

7

A New Approach Full Electro-Thermal Simulation

Thermal
technology
files

Circuit Simulator
Read temperatures
Solve electrical equations
Write power dissipation

TDEVICES

PDISS

Thermal Simulator
Read power dissipation
Solve thermal equation
Write temperatures

Iteration loop is
done automatically
until powers and
temperatures are
self-consistent

Copyright Agilent Technologies 2012

8

2-1_4

Electro-Thermal Simulation Results

More accurate circuit simulation results,
showing performance degradation due
to temperature rise
3D temperature maps, providing design
insight, leading to more robust layout
designs
Device temperature data, to uncover
potential reliability issues and failures

Copyright Agilent Technologies 2012

9

Thermal Solver Technology

Provided by Gradient Design Automation
Focused on IC thermal simulation
Full-chip (high capacity) 3-D FEM temperature
simulation with device- and wire-level resolution
Linux-based
Proven for large digital and mixedsignal applications
Used by major IC companies
On Semi, TI, AMD,
Works with any IC process
GaAs, Si, SiGe, GaN,

Mixed-Signal IC

45nm Digital Block with 800k Transistors

http://www.gradient-da.com/resources/technical-papers.php

Copyright Agilent Technologies 2012

10

2-1_5

Agenda
Introduction
Thermal Problems in RFIC/MMIC Design
Solutions: Traditional Approaches
Solutions: A New Approach
Case Study
MMIC PA Design Example
Electro-Thermal Simulation
Thermal and Electrical Results
Conclusion and Q&A

Copyright Agilent Technologies 2012

11

Case Study: Two Stage LTE PA

Two-Stage LTE PA
GaAsFET; uses EEsof DemoKit
Gain >25 dB
Pout > 25 dbm with Pin >1 dbm

Copyright Agilent Technologies 2012

12

2-1_6

Case Study: Two Stage LTE PA

Gain >25 dB; Pout > 25 dBm @ Pin >1 dBm

Copyright Agilent Technologies 2012

13

Two Stage LTE PA

6- InitialDesign_lay out3aa.gif

Stage 1 FET
4 fingers
100 um wide
PDC=900 mW

6- InitialDesign_lay out3bb.gif

Stage 2 FET
6 fingers
200 um wide
PDC=2100 mW

Copyright Agilent Technologies 2012

14

2-1_7

Two Stage LTE PA Layout

Thermal analysis using Rth calculations
Simple calculation of thermal resistance
RTH for each transistor
Assume power is dissipated uniformly
throughout the transistors channel
FET1 channel: 100 x 46.6 um: RTH = 168 K/W
Power dissipation = 900 mW
'T=RTH PDISS=168 K/W x 0.9W = 151qC T1=25+151=176qC
FET2 channel: 200 x 79.9 um: RTH = 98 K/W
Power dissipation = 2100 mW
'T=RTH PDISS=98 K/W x 2.1W = 206qC
T2=25+206=231qC
Copyright Agilent Technologies 2012
15

Two Stage LTE PA Layout

Electro-thermal simulation

Copyright Agilent Technologies 2012

16

2-1_8

Electrothermal Simulation Setup

Step 1 Add an Electrothermal Controller to the schematic page

Copyright Agilent Technologies 2012

17

Electrothermal Simulation Setup

Step 2 Open the Electrothermal Controller
and specify a few parameters as shown below

Thermal
technology
Thermal
boundary
conditions

Copyright Agilent Technologies 2012

18

2-1_9

Electrothermal Simulation Setup

Step 3 Click the Simulate button

and electro-thermal simulation starts

Simulate

Thermal profiles,
plots and data output
results are
automatically
displayed at the end
of simulation

Copyright Agilent Technologies 2012

19

Thermal Profile @ Pin=0dBm

Simulation time = 6 minutes
8 point input
power sweep:
from -10 dBm
to
+4 dBm

Copyright Agilent Technologies 2012

20

2-1_10

Thermal Profile Max @ DC

Simulation time = 56 seconds

Copyright Agilent Technologies 2012

21

Thermal Profile Max @ DC

Copyright Agilent Technologies 2012

22

2-1_11

Electro-thermal Device Temperatures

Initial hand calculation with RTH predicted TFET1=176C and TFET2=231C
Electrothermal results TFET1=135C and TFET2=158-181C

Copyright Agilent Technologies 2012

23

Electro-thermal On vs Off
3 dB loss in gain

Electro-thermal OFF
Electro-thermal ON

Copyright Agilent Technologies 2012

24

2-1_12

Electro-thermal On vs Off
HB Pin/Pout

Pin Vs Pout
Electro-thermal OFF
Electro-thermal ON

Copyright Agilent Technologies 2012

25

Electro-thermal On vs Off
HB Power Dissipation Vs Pin

Electro-thermal OFF

Electro-thermal ON

Copyright Agilent Technologies 2012

26

2-1_13

Electro-thermal On vs Off
Harmonics

Electro-thermal ON
Electro-thermal OFF

Copyright Agilent Technologies 2012

27

Modify the Layout of FET2

Spread the fingers and place ground/thermal vias

FET2 temperatures were too high for reliability

RF performance no longer met specs
Modify the layout of FET2 to spread the heat out and cool the devices
Initial Design

Modified Design

Tmax
TFET1 =135qC

TFET2 =158-181qC

TFET1 =135qC

TFET2 =107-115qC
Copyright Agilent Technologies 2012

28

2-1_14

Modified Stage 2 FET Layout

Spread out fingers and place ground/thermal vias

Copyright Agilent Technologies 2012

29

Thermal Profile of Modified Layout @ Pin=0dBm

Initial Design
TFET2 = 158-181qC
Modified Design
TFET2 = 107-115qC
FET1 Temp now
dominates at
135qC

Copyright Agilent Technologies 2012

30

2-1_15

Thermal Profile Max @ DC of Modified Layout

Copyright Agilent Technologies 2012

31

Thermal Profile of Modified Layout

Copyright Agilent Technologies 2012

32

2-1_16

Electro-thermal Device Temperatures

Original layout
Modified layout

TFET1=135C and TFET2=158-181C

TFET1=135C and TFET2=107-115C

Copyright Agilent Technologies 2012

33

Modified Design - Dashed Traces

Copyright Agilent Technologies 2012

34

2-1_17

Modified Design - Dashed Traces

Initial Design Electro-thermal OFF

Initial Design Electro-thermal ON
Modified Design Electro-thermal ON

Copyright Agilent Technologies 2012

35

Modified Design
HB power dissipation
Initial Design Electro-thermal OFF
Initial Design Electro-thermal ON
Modified Design Electro-thermal ON

Copyright Agilent Technologies 2012

36

2-1_18

Modified Design

Initial Design Electro-thermal OFF

Initial Design Electro-thermal ON
Modified Design Electro-thermal ON

Copyright Agilent Technologies 2012

37

Case Study: Two Stage LTE PA

Mounted on a QFN Package

Copyright Agilent Technologies 2012

38

2-1_19

Mounting the IC onto a Package

Layer summary:
725 m
5 m
100 m
150 m

plastic package k=1.0

metal stack on chip
GaAs substrate k(25)=46
copper lead frame k=401

Copyright Agilent Technologies 2012

39

Thermal Profile of Modified Design and Package

Copyright Agilent Technologies 2012

40

2-1_20

Thermal Profile of Modified Design and Package

Thermal profiles of all layers IC and package

Copyright Agilent Technologies 2012

41

Electro-thermal Device Temperatures

Original layout
Modified layout
Modified, packaged

TFET1=135C and TFET2=158-181C

TFET1=135C and TFET2=107-115C
TFET1=141C and TFET2=116-120C

Copyright Agilent Technologies 2012

42

2-1_21

Thermal Profile of Modified Design and Package

Simulation results S-parameters

Copyright Agilent Technologies 2012

43

Thermal Profile of Modified Design and Package

Simulation results S21

Copyright Agilent Technologies 2012

44

2-1_22

Thermal Profile of Modified Design and Package

Simulation results Pin / Pout

Copyright Agilent Technologies 2012

45

Thermal Profile of Modified Design and Package

Simulation results HB power dissipation

Copyright Agilent Technologies 2012

46

2-1_23

Thermal Profile of Modified Design and Package

Simulation results fundamental and harmonics

Copyright Agilent Technologies 2012

47

Agenda
Introduction
Thermal Problems in RFIC/MMIC Design
Solutions: Traditional Approaches
Solutions: A New Approach
Case Study
MMIC PA Design Example
Electro-Thermal Simulation
Thermal and Electrical Results
Conclusion and Q&A

Copyright Agilent Technologies 2012

48

2-1_24

Summary: ADS Electro-thermal Solution

Applications: high power RFIC / MMIC

design
Deliver thermally aware circuit
simulation results by including effects
of on-chip temperature rise
Include effects of package and PCB
Easy to set up and use from within
the ADS environment
Works with all simulation types:
DC, AC, SP, HB, Transient, Envelope
Available in ADS 2012

ADS Schematic

ADS Layout

Integrated Thermal Solver

QUESTIONS?

Copyright Agilent Technologies 2012

49

2-1_25

A complete designer-oriented device

model verification solution for
advanced technology
Cai Shuang
Senior Application Engineer
Agilent EEsof

October 2012

Agenda
Increasing process complexity a challenge to models
Complete solutions for model verification
MQA (Model Quality Assurance)
de-facto industry standard SPICE model validation platform

AMA (Advanced Model Analysis)

layout dependent effects model validation platform

Whats New in MQA2012.07 and AMA 2012.07

Summary & Outlook

Copyright 2012 Agilent Technologies

2

2-2_1

Design Requirement for PDK

Industry standard model required
Physical model and scalable model required
Process variation awareness required for ensuring the yield
Mismatch model for AMS design required

Copyright 2012 Agilent Technologies

3

Model Challenge with Advanced Technology

Stress, Lithography and Well Proximity Effect

have made models more complex

Comprehensive QA and verification on the

Models are required in order to ensure design
success

Foundry often encrypts the model principle

for proximity models and make it more difficult for verifying the models

Copyright 2012 Agilent Technologies

4

2-2_2

Model QA Challenges And Requirements

When a model/library has been obtained from the foundry,
it should be checked against
- consistency (simulation convergence, model explosion etc.)
- physical behavior
- performance in different simulators
- etc.

This means:
Creating a lot of netlists
Handling of huge amount of data
Intelligent flagging of issues
Detailed reporting & documentation
and this requires a
comprehensive, flexible and customizable tool
5

Complete QA Solutions
MQA/AMA helps designers to remove uncertainties for sub45nm technologies
MQA/AMA is flexible enough to be adjusted to any design
flow and compatible to all popular EDA tools
MQA/AMA integrates the entire flow and all the related tools
for PDK verification purposes
MQA/AMA can be easily adjusted for future challenges

Agilent has developed an automated yet flexible

platform to access foundry proximity models with a
click of button
Copyright 2012 Agilent Technologies
6

2-2_3

Agenda

- Modeling Challenges
- Introduction to MQA (Model Quality Assurance)
- Introduction to AMA (Advanced Model Analysis)

Accelerating Analog Silicon

7

End-to-end Silicon Device Modeling Flow

Copyright 2012 Agilent Technologies

8

2-2_4

Agilents Validation Tools

Model
Validation

Physical
Validation

MQA

AMA

Design Variability

What is MQA?

MQA

the industry standard assurance tool that assists

modeling experts and model users to perform comprehensive
model QA with an knowledge-based, rule-driven approach.

It qualifies device models/libraries of ever growing complexity.

It is an automated device model verification and documentation
tool that
modeling engineers at IDMs/Foundries use to perform comprehensive
model QA and to release verified model files/libraries.
Fabless Design Houses use to evaluate and accept the model libraries
from Foundries.

10

2-2_5

What is MQA?

11

OS, Simulators, Input Format

Supported operating systems
Windows XP, Windows Vista, Windows 7
Linux

Supported simulators
All major EDA simulators: HSPICE, SPECTRE, Eldo, SPICE3, ADS,
Golden Gate (2012H2), AFS, Titan..

Input format
Data

Native MBP/MQA data format

IC-CAP mdm format (2012H2)

Model

Of all supported simulators

Copyright 2012 Agilent Technologies

12

2-2_6

MQA Rule-Based, Knowledge-Driven Model QA

A rule-based, knowledge-driven
automatic platform for SPICE
model quality assurance through
device- and circuit-level figures of
merit

Knowledge

Rules

Device physics, technology impact on

circuit design, model-simulator
interaction, key FOMs
Text files to describe FOMs, PVT
coverage, expectations, graphing
options, flagging criteria

Automation

Plotting, analysis, flagging, reporting,

documentation

13

MQA de-facto Industry Standard Acceptance

Tool
Minimizes costly late-stage
design surprises
Comprehensive acceptance QA
Design-specific checks

Increased efficiency for all design

teams
Consolidated QA efforts
Model library version control
Bridge between foundry and design
house

14

2-2_7

MQA Ideal Solution for Library Benchmarking

Exploding varieties of libraries

CAD-centric benchmarking

Cross-simulator equivalence
check
Cross-model (ex., BSIM4 vs.
PSP) equivalence check

Addresses key technology

benchmarking challenges

What has changed from previous

library release?
What has improved or worsened
from 32nm to 28nm?
How identical is the 2nd source
foundry to the primary foundry?

15

MQA Lib Explorer

Powerful Lib Parser

Parse large model libraries

Corner View / Model View

Model Analysis / Benchmark

2-2_8

Apply MQA as
Qualification tool
Knowledge based and rule driven
Validate model file/library and measurement data
Documentation tool
Overlay with measurement data
Easy to customize report
Design interface (foundry interface) tool
Comparison
Sharing the new technology characterization
Model QA result sharing tool
Bridge between foundry and design house
Communication between different groups

17

MQA Default Rule Sample:

18

2-2_9

Time Cost (2807 plots, 21 tables)

Slow & Error-prone

89.8%

66.7%

56.7%

Accelerating Analog Silicon

20

2-2_10

Inside the .rule File

ts
tes

A Rule file in MQA is a ASCII text file

which defines how MQA performs
certain checks on certain objects
under certain conditions

Example: Rule Check Idsat vs. L

[common]
appliedmodel = binning, global, macro
[Group: 4:Title=Model Scalability]

A rule (ASCII, customizable) is typically organized like this:

1. ID and title for selection in the GUI.
2. Conditions, which determine when it is valid,
i.e. when it will be executed.
3.
Loops, which defines the variations like bias, W/L/T sweeping,
etc.
4. Target, which defines target, normally it will be Y-axis on plot.
5. Check functions, to define which MQA checks to be applied,
also to define the warning message if check failed.

[Label: 4001:title= Check Idsat vs. L] *for NMOS

[Condition:(devtype=1)and(application=1 or application=2 or application=3)]
[Loops
: X=L(start=g_lmin,stop=g_lmax,perdec=10)
: P=W (start=g_wmin,stop=g_wmax, num=3)
: P1=Vgs(vgg)
: P2=Vds(vdd)
: P3=Vbs(0)
: P4=T(tmin, tnom, tmax)]
[Target: y=Idsat]
[Check: 01:Check Trend: CheckTrend2D (p,x,y,"times=1","incAtFirst=-1"): error: Trend is not right]
[Check: 02:Check Kink: CheckKink2D (p,x,y): error: Kink occurs]

21

Example of MQA Check functions, called by a Rules file:

CheckTrend

CrossCheck

Accelerating Analog Silicon

22

2-2_11

After all is
set up,
execute the
MQA test

the problem is
automatically indicated !

and obtain
a detailed
report

Accelerating Analog Silicon

23

MQA Demos
Multi-library comparison using Lib Explorer
Multi-targets Table
RF Applications:
9 S parameter
9 Harmonic Balance

Statistical Applications:
9 NP correlation + Monte Carlo
9 Mismatch

24

2-2_12

MQA Summary
As the first commercial SPICE model validation solution, MQA is
the de-facto industry standard tool for SPICE model validation,
comparison and documentation.
Broad customer acceptance: MQA has been widely adopted by
100+ customers around the world. Dominate in the validation
market.
Comprehensive checking routines built-in.
e.g. BSIM4: default 110 rules from 17 rule-groups
Support all mainstream models and simulators.
Compare differences between model versions, SPICE simulators,
and foundry technologies.
Powerful and Flexible Reporting Function. Easy to share QA
results.

25

Agenda

- Overview
- Introduction to MQA (Model Quality Assurance)
- Introduction to AMA (Advance Model Analysis)

Accelerating Analog Silicon

26

2-2_13

Why AMA?
A MOS transistors drive capability is no longer primarily determined by its
width and length. Rather, it is heavily influenced by the layout of its
surrounding structures, which has become known collectively as layout
dependent effects (LDEs).
Stress, Lithography and Well Proximity Effects have made models more complex.
Need solution to:
Verify foundry Models
Access Variability using foundry input
Remove Uncertainty before tape out.

27

Why AMA?

Schematic

Schematic

Layout

Layout

LVS

Modified
Netlist
SPICE

Customized
instance

Layout instance correlate

model parameters through equations

BSIM

Macro Model

28

2-2_14

LVS

Extracted
Netlist
SPICE

Macro Heavy

LVS Heavy

Modeling approach: LVS + Macro SPICE model

45nm/32nm Special Effects

Layout Dependent Variations

29

Foundry Solutions for Addressing Variability

Proximity Models
Stress
Lithography
Well Proximity

Proximity Model Means

LVS heavy

Need Solution to

Macro SPICE model heavy

LVS+Macro SPICE model

1. Verify foundry Models

2. Access Variability
using foundry input

30

2-2_15

What AMA does

Model QA with layout dependent parameter consideration.
Sweep layout parameters and generate Test Structure automatically.
Extract layout parameters
Check SPICE model electrical performance vs. layout parameters.
Pin-point issues or abnormal behaviors due to LDEs before Tape-Out

Built-in Modules and Flow

AMAs architecture

SPICE
Model

Generic
Rule File

Corner model
Statistical model
Mismatch

Assura
Calibre
Hercules

AMA

Netlist

SPICE

PCELL or
Generator

Layout
DB

LVS Decks
Characterization
Comparison
Documentation

User layout or
from stand cell

32

2-2_16

Built-in Modules and Flow

Layout Generation

Layout
Generation

PCell mode
SKILL Template mode
Layout mode

Layout
Extraction

Layout Extraction
Mentor Graphic Calibre
Synopsys Hercules & StarRCXT
Cadence Assura & QRC

SPICE simulation

SPICE Simulation
HSPICE or Spectre
Data Analysis

Data Analysis

33

AMA Sample Result

2-2_17

AMA directory structure

bin: contains key executable of AMA.

lib: contains library files for program, such as ".so"
and ".jar" files.
skill: contains SKILL files to initiate AMA program from Virtuoso.

etc: contains default settings files.

icf: contains Instance Connection Files.
checker: contains testing cases to check connectivity to 3rd
party tools.
checkfunctions: contains built-in check functions.
skill: contains built-in SKILL template files to create layout.

lic: contains license related configuration files.

help: contains user manual and built-in contextsensitive help files.

35

Rule File Generator

This rule file is more complicated than MQAs and since

it involves layout generation, we provide a separate
module to generate rule files.

36

2-2_18

Rule File Generator-Layout Source

Test Bench can have the following three sources:

From Foundry PCELL

From SKILL based layout generator

From existing or user layout

37

Sample Rule Syntax

[Group: 1:Title=MOS Devices]

[Condition:1]

[Path: $AMAHOME/etc/tb/mos/nmos/xxxx65ng_nch.il] * user has the option to link to foundry PCELL.

[SPICE: HSPICE$AMAHOME/examples/hb3v3.lib:tt:nmos]

* for circuit, model is defined within circuit definition.

[Loops

: A1(values for A1)

: A2(values for A2)

: A3(values for A3)

[Target: Idsat, Vth, Ioff]

[Check: 01:Check Trend: CheckTrend2D (a1,a2,a3,"times=1","incAtFirst=-1"): error: Trend issue]

[Compare: CompPlot(a1,a2,a3): error: TBD]

38

2-2_19

Example: Lithography rounding effects for 32nm

A predictive 32nm Model is used

A Litho-aware extraction deck of a 45nm technology is
used (we expect more rounding effect at 32nm).

Example: Lithography rounding effects for 32nm

An AMA run is executed and is finished in less than 30 seconds. One
can clearly see that the variability due to layout parameter B (OD
rounding height) is almost 20% at certain A value, and if A exceeds
certain value say 0.1um, OD rounding effects becomes negligible
(the number may not make sense, but you get the idea).

W=60nm
L=32nm

2-2_20

Example: Lithography rounding effects for 32nm

And we have observed using the input from foundry, the following
plot is observed, and it obviously doesnt make sense, so user can
define a criteria and let the tool pick up the issue automatically and
feedback to foundry.

Example: WPE effect

42

2-2_21

Example: WPE effect (cont.)

43

AMA Summary
AMA is the extension of MQA to qualify the layout dependent
effects model for cutting-edge technologies.
Built-in complete workflow for model-LVS co-validation.
Technology based and rule driven.
Open interface to support popular physical verification tools
and SPICE simulators.
Accurately predict design margin due to process/design
variability before tape-out.
Flexible to be adjusted (extended) to other applications.

44

2-2_22

Whats New
MQA 2012.07
Java Version Update
Support of Project-level Parallelism
Seamless Data Flow for ICCap .mdm data format
Enhanced Support of ADS (HPEESOFSIM)
Support for III-V Technologies

AMA 2012.07

Expanded CDF Support

StarRCXT, Assura Support

Support of Layout Mode in Rule Generator

For more: http://edocs.soco.agilent.com/display/mqa201207/MQA+Release+Notes

MQA/AMA in a nut shell:

A tool to test simulation or measurement results under all kinds of conditions

Drawn by: Franz Sischka

Accelerating Analog Silicon
46

2-2_23

Roadmap
Database preparation to deal with huge amount of data.
More flexible parallelization to further speed-up.
Continue to contribute to the seamless integration of
simulation modules with focus on the interplay and
interfacing of EDA tools in order to:
Enhance design effectiveness
Reduce development cycle times
Reduce costs

Build unified platform for modeling verification to combine

MQA and AMA functionalities and more.

Thank you for your attention !

Accelerating Analog Silicon

48

2-2_24

www.agilent.com.tw

Agilent Email Updates

www.agilent.com.tw/find/emailupdates

http://210.244.49.188/library

0800-047866

www.agilent.com.tw/find/open

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(02) 8772-5888

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(03) 492-9666

www.agilent.com/find/removealldoubt

8026251
(07) 535-5035

2012
Issued date : 2012 / 10

Printed in Taiwan

2012/10