K.T.
Tim Cheng,
02_fault_model, v1.0
Outline Fault Modeling
Why Model Faults
Single Stuck-at Faults
Fault Collapsing
Fault Detection and Redundancy
Other Common Fault Models
Transistor faults
Bridging faults
Delay faults
Memory faults
K.T. Tim Cheng,
02_fault_model, v1.0
Why Model Faults?
I/O function tests inadequate for
manufacturing (functionality vs.
component & interconnection testing)
Fault model identifies target faults
Fault model makes analysis possible
Effectiveness measurable by
experiments
K.T. Tim Cheng,
02_fault_model, v1.0
Some Real Faults In Chips
Processing faults
Missing contact windows
Parasitic transistors
Oxide breakdown
Material defects
Bulk defects (Cracks, Crystal imperfections)
Surface impurities (Ion migration)
Time-dependent failures
Dielectric breakdown
Electromigration
Packaging failures
Contact degradation
Seal leaks
K.T. Tim Cheng,
02_fault_model, v1.0
Some Fault Models
Single stuck-at faults
Transistor open/short faults
Bridging faults
Delay faults
Memory faults
Analog faults
K.T. Tim Cheng,
02_fault_model, v1.0
Single Stuck-At Faults
TEST VECTOR
1
1
FAULTY RESPONSE
TRUE RESPONSE
0
0
0 (1)
0 (1)
STUCK - AT - 1
Assumptions: 1. Only one line is faulty
2. Faulty line permanently set to 0 or 1
3. Fault can be at an input or output of a gate
K.T. Tim Cheng,
02_fault_model, v1.0
Single Stuck-At Fault
Most widely studied and used
It represents many different physical faults
It is independent of technology
Experience has shown that tests that detect
SSFs detect many nonclassical faults as well
The number of SSFs in a circuit is small.
Moreover, the number of faults to be explicitly
analyzed can be reduced by fault collapsing
techniques.
K.T. Tim Cheng,
02_fault_model, v1.0
Role of Fault Collapsing
DUT
Fault Model
Generate fault list
Collapse fault list
Required
fault coverage
Generate test vectors
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
K.T. Tim Cheng,
02_fault_model, v1.0
Definitions
Given
T1 is set of all tests for fault F1
T2 is set of all tests for fault F2
F2 dominates F1
T2
F1 and F2 are equivalent
K.T. Tim Cheng,
T1
T1=T2
9
02_fault_model, v1.0
Fault Equivalence
Two equivalent faults are detected by exactly
the same tests
s-a-0
s-a-1
s-a-1
Example : Three faults shown are equivalent
K.T. Tim Cheng,
02_fault_model, v1.0
10
Equivalence Fault Collapsing
s-a-0
s-a-1
s-a-1
s-a-0
s-a-1
s-a-1
s-a-0
s-a-0
N+2 faults in N-input gate
K.T. Tim Cheng,
11
02_fault_model, v1.0
Equivalent Fault Collapsing
0
0
0
0
0
0
0
0
(a)
0
0
0
0
(b)
K.T. Tim Cheng,
02_fault_model, v1.0
12
Functional Equivalence
s - a. 0
x
s. a. 0
b s.a.0 & f s.a.0 are equivalent while they
cannot be identified by simple structure
analysis.
K.T. Tim Cheng,
13
02_fault_model, v1.0
Dominance Fault Collapsing
F1: s - a - 1
F2: s - a - 1
T2
T1
If any test for F1 detects F2 but converse
is not true, then F2 dominates F1
Only N+1 faults in an N-input gate
s -a-1
s -a-0
s -a-1
K.T. Tim Cheng,
02_fault_model, v1.0
14
Checkpoint Faults
Checkpoints
Primary inputs
Gate-inputs fed by fanout lines
Checkpoint faults
Sufficient to model stuck-at faults at checkpoints
Model only input faults in fanout-free circuit
K.T. Tim Cheng,
02_fault_model, v1.0
15
Theory on Checkpoint Faults
Theorem: In a fanout-free combinational
circuit C, any test set that detects all
single stuck-at faults on the primary inputs
of C detects all SSFs in C.
Theorem: In a combinational circuit, any
test which detects all single (multiple)
stuck faults on all checkpoints detects all
single (multiple) faults in the circuit.
K.T. Tim Cheng,
02_fault_model, v1.0
16
Fault Detection
For combinational circuits: A test vector t
detects a fault f iff Zf(t) Z(t)
s. a. 0
X
Example :
C
B
Z (A, B, C) = AC + BC
Zf (A, B, C) = BC
>t = (1, 0, 0) is a test for A s.a.0. fault
K.T. Tim Cheng,
17
02_fault_model, v1.0
Fault Detection An Example
X2
X3
X1
Z
X4
Z = (X2 + X3) X1 + X1 X4
Fault: X4 s-a-0
Zf = (X2 + X3) X1
Z(x) Zf(x) = X1 X4 = 1
Any of the four tests: 0 0 0 1, 0 0 1 1, 0 1 0 1, 0 1 1 1 detects f
18
Sensitization
X2
X3
0
0
X1
G1
0
G3
0
G5
G2
X4
V/Vf :
0/1
x
s. a. 1
0/1
G4
0/1
V : Signal values in the fault free ckt
Vf : Signal values in the faulty ckt
Two basic concepts in fault detection:
Activation: Creating different V & Vf values at
the fault site.
Example: Create a 0 at G2 for G2 s.a.l
19
Error Propagation
Propagating fault effect to a primary output
Example: the fault effect propagates along
the path G2, G4, G5
A line is sensitized to the fault by the test
t if its value in the test t changes in the
presence of the fault f
Example: G2, G4 and G5 are sensitized.
A path composed of sensitized line is called
a sensitized path.
Example: path G2-G4-G5 is a sensitized path
20
10
Detectability & Redundancy
A fault f is said to be detectable if there
exists a test t that defects f; otherwise, f
is undetectable
For combinational circuits, an undetectable
fault is corresponding to a redundant wire.
s. a. 1
l x
m
n
l
m
n
If l s.a.1 is undetectable, the gate can
be simplified as
m
Y
n
K.T. Tim Cheng,
21
02_fault_model, v1.0
Redundancy
s. a. 0
l x
m
n
l
m
n
If l s.a.0 is undetectable, the entire gate
can be removed & replaced by a constant 0
wire
K.T. Tim Cheng,
02_fault_model, v1.0
22
11
Example: Redundancy Removal
A
B
C
Conflict!
0
1 1
0
s.a.0
A
B
0
C
Z is glitch-free
Z may have glitches
Warning: Redundancy may be required for glitch-free designs!!
If having glitches is not a concern (e.g. synchronous designs),
redundancy can be removed.
K.T. Tim Cheng,
02_fault_model, v1.0
Fault Detection for Sequential Circuits
Fault detection requires a sequence of vectors, not
just one vector.
Suppose
T: A sequence of vectors
R(q,T): Output response w/ initial state being q
Rf(q,T): Output response w/ initial state being q and
fault f is present.
T strongly detects the fault f iff R(q, T) Rf(qf, T)
for every possible pair of initial states q & qf.
K.T. Tim Cheng,
02_fault_model, v1.0
24
12
An Example
y1
X
y2
y1
y2
y1
X
y2
Xa
y1
y2
X
y1
Y1
y1
Y2
y2
b
y2
K.T. Tim Cheng,
25
02_fault_model, v1.0
State table:
In itia l
S ta te
Y1
Y2
A, 0
D, 0
C, 1
C, 1
B, 1
A, 0
A, 1
B, 1
O u tp u t S e q u e n c e to T =
10111
F a u lt-fr e e
a s-a -1
b s-a -0
01011
01010
01101
11100
11100
11101
00011
00010
01010
11001
10010
11010
T strongly detects b s-a-0.
T does not strongly detect a s-a-1.
K.T. Tim Cheng,
02_fault_model, v1.0
26
13
Issues of Strong Detection
Even thought T strongly detects b s-a-0, we
cannot say at which time a fault effect (0/1 or
1/0) will appear.
We must list all possible responses of the fault
free circuit and compare the output response of
the circuit under test with each of the normal
responses to determine the detection of the fault.
Not practical!!
For n FFs, we need to store 2n possible output
responses.
K.T. Tim Cheng,
02_fault_model, v1.0
27
Practical Notion of Detection
Practically, we store just one normal response and
determine the detection on a vector-by-vector basis.
Test sequence T detects the fault f iff for every
possible pair of initial states q and qf, the output
sequences R(q, T) and Rf(qf, T) are different for some
specified vector ti T.
K.T. Tim Cheng,
02_fault_model, v1.0
28
14
Fault Detection for Sequential Ckts
Testing experiment is divided into two phases:
Phase 1: Apply an initialization sequence TI
At the end of TI, both fault-free & faulty circuits are brought to
known states qI & qIf.
Output responses are ignored during TI as they are unpredictable.
Phase 2: Apply a test sequence T.
Both R(qI, T) & R(qIf., T) are predictable.
ti is the first vector of T for which an error is observed.
The applied sequence is TI-T and the stored expected
response is dont cares-R(qI, T).
In testing, we compare the output response of the CUT
with the stored expected response.
When a mismatch occurs at a care vector, detection is reported.
K.T. Tim Cheng,
02_fault_model, v1.0
29
Multiple Stuck-at Faults
A multiple stuck-at fault means that any set of lines
is stuck-at some combination of (0,1) values.
The total number of single and multiple stuck-at
faults in a circuit with k single fault sites is 3k-1.
A single fault test can fail to detect the target
fault if another fault is also present, however, such
masking of one fault by another is rare.
Statistically, single fault tests cover a very large
number of multiple faults.
K.T. Tim Cheng,
02_fault_model, v1.0
30
15
Transistor (Switch) Faults
MOS transistor is considered an ideal switch
and two types of faults are modeled:
Stuck-open - a single transistor is permanently
stuck in the open state.
Stuck-short - a single transistor is permanently
shorted irrespective of its gate voltage.
Detection of a stuck-open fault requires two
vectors.
Detection of a stuck-short fault requires the
measurement of quiescent current (IDDQ).
K.T. Tim Cheng,
31
02_fault_model, v1.0
Stuck-Open Example
Vector 1: test for A s-a-0
(Initialization vector)
pMOS
FETs
1
Vector 2 (test for A s-a-1)
VDD
Stuckopen
Two-vector s-op test
can be constructed by
ordering two s-at tests
1(Z)
Good circuit states
nMOS
FETs
Faulty circuit states
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
K.T. Tim Cheng,
02_fault_model, v1.0
32
16
Stuck-Short Example
Test vector for A s-a-0
pMOS
FETs
1
0
VDD
IDDQ path in
faulty circuit
Stuckshort
nMOS
FETs
Good circuit state
0 (X)
Faulty circuit state
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
K.T. Tim Cheng,
02_fault_model, v1.0
33
Bridging Faults
Shorting of adjacent lines (layout dependent)
Usually assuming a low resistance path (hard short)
Faulty value is identical on shorted lines
Faulty value is AND/OR function of shorted
signals
Covering a large % of physical defects
A large # of bridging faults map into SA faults
K.T. Tim Cheng,
02_fault_model, v1.0
34
17
Delay Faults
Used to test whether device meets performance
specification
Related to propagation delay in combinational circuit
(from inputs/flip-flops to outputs/flip-flops)
Two types of faults
Path-delay fault
Gate-delay fault
Details will be introduced later in Delay Testing
chapter
K.T. Tim Cheng,
02_fault_model, v1.0
35
Path-Delay & Gate-Delay Faults
Path-delay-fault:
Propagation delay of path exceeds clock interval
# of paths grows exponentially with number of gates
9 Only consider long paths or a subset of paths
Tests can detect small distributed failures
Tests for the longest paths can also be used for
speed-sorting
Gate-delay-fault:
A logic model for a defect that delays a rising or a
falling transition
Small distributed timing failures could be missed
#of modeled faults is much smaller and manageable
K.T. Tim Cheng,
02_fault_model, v1.0
36
18
Transition Faults & Small Gate-Delay Faults
Transition fault (Gross gate-delay fault):
The extra delay caused by the fault is assumed to be large
enough to prevent the transition from reaching any primary
output at the time of observation
Can be tested along any path from the fault site to any PO
The test is a vector pair that creates a transition at the fault
site and the second vector is a test for the stuck-at fault at
the fault site
Small gate-delay fault:
Is tested along the longest propagation delay path
K.T. Tim Cheng,
37
02_fault_model, v1.0
PLA Faults
Stuck-at faults
Cross-point faults
Bridging faults
K.T. Tim Cheng,
02_fault_model, v1.0
38
19
Stuck-at Faults In PLA
S-a-0 and s-a-1 on inputs, input inverters,
product lines, and outputs
Easy to simulate in gate model
A
f1
f2
f2
P1
f1
P2 x
K.T. Tim Cheng,
P2
P1
AND-Array
OR-Array Stuck fault sites
Equivalent logic model
PLA
39
02_fault_model, v1.0
Missing Cross-Point Faults In PLA
A
f1
f2
AB
p1
C 00 01 11 10
0 1
1 1 1 1
p2
p2 x
Missing cross-point in AND array
Growth fault
Equivalent to stuck fault
B
X
C
s-a-1
K.T. Tim Cheng,
p1 [ ( C, p1 ) MISSING
OR - ARRAY
DISAPPEARANCE
p1 = B.C.
p1 = B
02_fault_model, v1.0
..
Missing cross-point in OR array
- Disappearance fault
- Equivalent to stuck fault
. . p.1
. .p.2
AND - ARRAY
GROWTH
p1
f1 = p1 + p2
f1 = p2
40
20
Extra Cross - Point Faults In PLA
A
f1
f2
AB
P1
SHRINKAGE
DISAPPEARANCE
P2 x
C 00 01 11 10
0 1
1 1 1 1
p2
p2 : ( C, p2 ) ADDED
APPEARANCE
Extra cross-point in AND array
Extra cross-point in OR array
Shrinkage or disappearance fault
Appearance fault
Disappearance equivalent to stuck
fault
K.T. Tim Cheng,
02_fault_model, v1.0
41
Summary of PLA Faults
Cross-point faults
80-85% covered by stuck-at fault tests
Layout-dependence in folded PLA
Bridging faults
99% covered by stuck-at fault tests
Layout-dependence in all PLAs
K.T. Tim Cheng,
02_fault_model, v1.0
42
21
Summary: Fault Modeling
Current practice
Single stuck-at faults
Simple gate delay faults (transition faults)
Limited usage of path delay faults
Various faults for memory
Other important models
Stuck-open and stuck-short (CMOS)
Interconnect open faults and bridging faults
K.T. Tim Cheng,
02_fault_model, v1.0
43
Isnt 99.9% Good Enough?
The alternative to setting the standards at their highest possible
level becomes clear when we look at the consequences of almost,
but not quite perfect.
If 99.9% is good enough then:
2 million documents will be lost by IRS this year
22K checks will be deducted from the wrong back accounts in the next
hour
12 babies will be given to the wrong parents today
268K defective tires will be shipped this year
14K defective PCs will be shipped this year
2.5 million books will be shipped in the next year with the wrong cover
2 plane landings daily at LAX airport will be unsafe
18K pieces of mail will be mishandled in the next hour
880K credit cards in circulation will have incorrect cardholder information
on their magnetic strips
315 entries in Websterss Dictiorary will be misspelled
...
K.T. Tim Cheng,
02_fault_model, v1.0
44
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