LPDDR4 SDRAM Controller Core
Product Highlights
Block Diagram
Maximizes bus efficiency via LookAhead command processing, Bank
Management and Auto-Precharge
sdram_lb
Bank
Management
Bank
Management
Minimal latency achieved via parameterized pipelining
Supports full rate, half-rate and
quarter-rate clock operation
Multi-mode controller support
DFI Control Interface
l_addr
l_b_size
l_auto_pch
l_r_req
l_w_req
l_busy
MultiBurst
(optional)
Queue
Control
DFI Status Interface
Control and Timing
l_d_req
l_r_valid
DFI Update Interface
Full run-time configurable timing
parameters and memory settings
Initialization
Control
Supports LPDDR4 Data Bus Inversion (DBI) and Data Mask (DM)
Supports self-refresh, partial array self-refresh, power-down, and
deep power down modes
DFI Compatible
DDR PHY
Achieves high clock rates with
minimal routing constraints
Refresh / ZQCal Control
l_datain
l_dm_in
l_dataout
DFI Write Data Interface
Data Control
DFI Read Data Interface
Config Ports
Status Ports
Full set of Add-On Cores available
Delivered fully integrated and
verified with target DDR PHY
Minimal ASIC gate count
sdram_csr (optional)
APB
Broad range of ASIC platforms
supported
Source code available
I2C
Customization and Integration
services available
Product Overview
Northwest Logics Low Power Double Data Rate 4 (LPDDR4)
SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and
translates them to the command sequences required by
LPDDR4 SDRAM devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management modules to monitor the status
of each SDRAM bank. Banks are only opened or closed when
necessary, minimizing access delays.
The core queues up multiple commands in the command
queue. This enables optimal bandwidth utilization for both
short transfers to highly random address locations as well as
longer transfers to contiguous address space. The command
queue is also used to opportunistically perform look-ahead
activates, precharges and auto-precharges further improving
overall throughput.
Copyright 2016 Northwest Logic
The core is provided with run-time programmable inputs for all
memory timing parameters and configuration settings. This
ensures compatibility with all LPDDR4 SDRAM configurations.
Add-On Cores such as a Multi-Port Front-End and Reorder Core
can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY.
Northwest Logic supports a broad range of third party and its
own soft DDR PHY. Contact Northwest Logic for more information.
Northwest Logic also provides IP Core customization services.
Contact Northwest Logic for a quote.
Product Deliverables:
Core (Netlist or Source Code)
Testbench (Source Code)
Complete Documentation
Expert Technical Support & Maintenance Updates
13
Northwest Logic Proprietary
