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Design Rules

The document contains design rules for creating N-well structures and components in integrated circuits such as minimum widths, spacings, and areas for wells, diffusions, polysilicon gates, contacts, and metals. It also outlines the steps for designing an nMOS transistor, creating an N-well, adding a pMOS, connecting the transistors to form an inverter, assigning a signal to the inverter input, and simulating the inverter to obtain its transfer characteristics.

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rushikant
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33 views34 pages

Design Rules

The document contains design rules for creating N-well structures and components in integrated circuits such as minimum widths, spacings, and areas for wells, diffusions, polysilicon gates, contacts, and metals. It also outlines the steps for designing an nMOS transistor, creating an N-well, adding a pMOS, connecting the transistors to form an inverter, assigning a signal to the inverter input, and simulating the inverter to obtain its transfer characteristics.

Uploaded by

rushikant
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Design Rules

N- Well
r101
r102
r110

Minimum width
Between wells
Minimum well Area

r 101

N - Well

r 102

12
12
144 2

r201

Minimum N+ and P+ diffusion width 4

r 201

P+ Diff

r 201

N+ Diff

N - Well

r202

Between two P+ and N+ diffusions

r 202

P+ Diff

N - Well

r 202

N+ Diff

r203

Extra N-well after P+ diffusion

r 203

P+ Diff

r 203
N - Well

N+ Diff

r204

Between N+ diffusion and n-well

P+ Diff

N - Well
r 204

N+ Diff

r210

Minimum diffusion area

r 210

P+ Diff

r 210

N+ Diff

N - Well

162

r301

Polysilicon Width

Polysilicon
r 301

P+ Diff

N - Well

Polysilicon
r 301

N+ Diff

r302

Polysilicon gate on Diffusion


Polysilicon

r 302
P+ Diff

N - Well

Polysilicon

r 302
N+ Diff

r307

Extra Polysilicon surrounding Diffusion 3


Polysilicon

r 307

P+ Diff

r 307
N - Well

Polysilicon
r 307

N+ Diff
r 307

r304

Between two Polysilicon boxes


Polysilicon

r 304
P+ Diff

N - Well

Polysilicon

r 304
N+ Diff

r307

Diffusion after Polysilicon


Polysilicon

r 307

r 307

P+ Diff

N - Well

Polysilicon

r 307

r 307
N+ Diff

r401

Contact width 2
Contact
r 401

Polysilicon Contact

Metal/Polysilicon Contact

r404

Extra Poly surrounding contact


Contact

r 404

Polysilicon Contact

Metal/Polysilicon Contact

r 404

r405

Extra metal surrounding contact


Contact

Polysilicon Contact

Metal/Polysilicon Contact

r 405

r 405

r403

Extra diffusion surrounding contact 1

r 403

Polysilicon

P+ Diff

N - Well
r 403

Polysilicon

N+ Diff

r501

Between two Metals 4

Metal 1

Metal 4
r 501

Metal 2

Metal 5
r 501

Metal 3

Metal 6

r510

Metal 1

Metal 2

Minimum Metal area 162

r 510

r 510

r 510

r 510

Metal 3

Metal 4

Metal 5

Metal 6
r 510

r 510

Step 1: Select Foundary

Step 2: Select Foundary

Step 3: n+ Diffussion

Step 4: Polysilicon

Step 5: n+diff and Metal Contact

This Completes nMOS design


Now go for pMOS Design, and the first need is
to construct N Well

Step 6: Create N Well

Step 6: p+ Diffusion

Step 7: Polysilicon

Step 8: Contacts

Final Connections
pMOS Completed
Now Interconnection of pMOS and nMOS to
complete inverter
Connect Source of pMOS to VDD and Source of
nMOS to VSS.

Short the Drain of both pMOS and nMOS.

INVERTER: Complete Design

Check DRC

Assign Source
Assign Signal (Clock) to Gate Terminal
Add Visible node at Output

Inverter with Source

Run Simulation

VTC Characteristics

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