MOSFET DC Circuits Analysis
1.
2.
3.
4.
5.
6.
Assume an operation region (usually the saturation region)
Apply KVL at the gate source loop to find VGS
Use VGS from step 2 to calculate ID
Apply KVL at the drain source loop and use ID from step 3 to find VDS
Check the validity of operation region assumptions by comparing VDS to VDSat
Change assumptions and analyze again if required.
NOTES :
An enhancement-mode device with VDS = VGS is always in saturation
If we have a source resistance, we need to solve the equations in steps 2
and 3 together to find ID and VGS.
If we include channel length modulation or we are in the triode region, we
will solve the equations in steps 3 and 4 together
If we include channel length modulation or we are in the triode region and
we have a source resistance, we will solve the equations in steps 2, 3, and 4
together
Bias Analysis: Example 1
Assumption: Transistor is
saturated, IG=IB=0
Analysis: First, simplify circuit,
split VDD into two equal-valued
sources and apply Thevenin
transformation to find VEQ and REQ
for gate-bias voltage
Problem: Find the Q-pt (ID, VDS)
Given: VTN=1V, Kn=25A/V2
Approach: Assume operation
region, find Q-point, check to see
if result is consistent with
operation region
Bias Analysis: Example 1 (contd.)
V 2 + 0.05V 7.21 = 0
GS
GS
V = 2.71V,+2.66V
GS
Since VGS<VTN for VGS= -2.71 V
and MOSFET will be cut-off,
we ignore it
V = +2.66V and ID= 34.4 A
GS
=V + I R
EQ GS D S
K
2
I = n V
V
D
2 GS TN
KVL at G-S loop,
K R
2
V
=V
+ n S V
V
EQ GS
2 GS TN
4 =V
GS
6
3
2510
3910
V
+
GS
2
KVL at D-S loop,
= I ( R + R ) +V
DD D D S
DS
V
= 6.08V
DS
VDS>VGS-VTN. Hence saturation
region assumption is correct.
Q-pt: (34.4 A, 6.08 V)
with VGS= 2.66 V
Bias Analysis: Example 2
Find the Q-point for the shown
circuit with body effect using
2F=0.6 V, VTO=1V, and =0.5V1/2:
KVL at G-S loop,
V =V
I R = 6 22,000 I
D
GS EQ D S
SB
= I R = 22,000 I
D
D S
V = V + ( V + 2 2 )
TN TO
F
F
SB
V = 1 + 0.5( V + 0.6 0.6 )
TN
SB
25 10 6
2
V
I '=
V
D
TN
GS
2
Iterative solution can be found
by following steps:
Estimate value of ID and use
it to find VGS and VSB
Use VSB to calculate VTN
Find ID using above 2 steps
If ID is not same as original
ID estimate, start again.
Bias Analysis: Example 2 (contd.)
The iteration sequence leads to ID= 88.0 A
V
DS
=V
DD
I ( R + R ) = 10 40,000 I = 6.48V
D D S
D
VDS>VGS-VTN. Hence saturation region assumption is correct.
Q-pt: (88.0 A, 6.48 V)
Bias Analysis: Example 3
Find the Q-point for the shown circuit?
V
V
V =V
GS DD
2 GS TN
2.6 10 4 104
2
V = 3.3
V
1
GS
GS
2
Kn R
V = 0.769V,+2.00V
GS
Since VGS<VTN for VGS= -0.769
V and MOSFET will be cut-off,
it will be ignored.
V = +2.00V and ID= 130 A
GS
Assumption: IG=IB=0, transistor
VDS>VGS-VTN. Hence saturation
is saturated (since VDS = VGS)
region assumption is correct.
Analysis:
Q-pt: (130 A, 2.00 V)
V
DS
=V
GS
=V
DD
I R
D D
Bias Analysis: Example 4
( Biasing in Triode Region)
Find the Q-point for the shown circuit?
KVL at D-S loop,
= I R +V
DD D D
DS
4 = 1600 I +V
D DS
V
= 2.19V
DS
V
But VDS<VGS-VTN. Hence, saturation
region assumption is incorrect Using
triode region equation,
Assumption: IG=IB=0,
transistor is saturated
Analysis: VGS=VDD=4 V
I
= 250 A (4 1)2 = 1.13mA
D 2 V2
V
A
4 V
= 1600* 250
(4 1 DS )V
DS
DS
2
V2
V
= 2.3V and ID=1.06 mA
DS
VDS<VGS-VTN, transistor is in triode region
Q-pt:(1.06 mA, 2.3 V)
Bias Analysis: Example 5
Find the Q-point for the shown circuit?
15V (220k)I
SG
=0
2
15V (220k) 50 A V
2 V
=0
SG
2 V2 SG
V
SG
= 0.369V,3.45V
Since VSG= 0.369 V is less than
|VTP|= 2 V, VSG = 3.45 V
ID = 52.5 A and VSG = 3.45 V
Assumption: IG=IB=0, transistor
is saturated (since VDS= VGS)
Analysis:
KVL at G-S loop,
SD
>V
SG
V
TP
Hence saturation assumption is correct.
Q-pt: (52.5 A, 3.45 V)
MOSFET Circuits At DC
Fig. Ex6
Fig. Ex7
Fig. Ex8
Example 6: Design the circuit of Fig. Ex6 so that the transistor operates at
ID=0.3 mA and VD=+1V. The NMOS transistor has Vt = 1V, nCox=20 A/V2,
L=1 m, and W=30m.
Example 7: Design the circuit in Fig. Ex7 to obtain a current ID of 0.4 mA. Find
the value required for R and find the DC voltage VD. The NMOS transistor has Vt
= 0.5V, nCox=20 A/V2, L=1 m, and W=40m.
Example 8: Design the circuit in Fig. Ex8 to establish a drain voltage of 0.1 V.
What is the effective resistance between drain and source at this operating
point? Let Vt = 1V and kn = 1 mA/V2
MOSFET Circuits At DC (contd.)
Fig. Ex9
Fig. Ex10
Example 9: Analyze the circuit shown in Fig. Ex9 to determine
the voltages at all nodes and the currents through all branches.
Let Vt = 1V and kn(W/L) = 1 mA/V2
Example 10: Design the circuit in Fig. Ex10 for the shown
currents and voltages (i.e find R, (W/L) for each transistor). Let
Vt=1 V, nCox=20 A/V2
MOSFET As A Current Source
Ideal current source
gives fixed output
current regardless of
the voltage across it.
MOSFET behaves as
as an ideal current
source if biased in
the pinch-off region
(output current
depends on terminal
voltage).
NMOS Current Mirror
'
n
I
=
REF
2 L
'
W
n
I =
O
2 L
V GS1
M 1
V GS2
M 2
But VGS2=VGS1
Assumption: M1 and
M2 have identical VTN,
Kn, and W/L and are
in saturation.
L
I = I
O REF W
TN
TN
2
1+ V
DS1
2
1+ V
DS2
W
1+ V
M 2
DS2 L
1+ V
W
DS1 L
M 1
M 2 I
REF
M 1
Thus, output current mirrors
reference current if VDS1=VDS2 or
= 0, and both transistors have
the same (W/L)
NMOS Current Mirror: Example 11
Find the output current and the minimum output
voltage vo to maintain the given current mirror in
proper operation.
Given data: IREF= 50 A, VO= 12 V, VTN= 1 V, Kn= 75 A/V2, = 0 V-1,
(W/L)M1 = 2, (W/L)M2=10
Analysis:
I = I
O REF
GS
=V
TN
2I
L M 2
W
L M1
= 250A
= 1V + 2(50A) = 1.82V
W
A
2*75
K n (1+ V
)
DS 1
L
V2
REF
Hence, Vomin =VGS VTN = 0.82 V.
