UNIT-III [April-15]

[EPRVD-201B]
5. a) Define Mobility of an operational unit. With an example
explain how ASAP scheduling algorithm is used to determine M.Tech. Degree Examination
Mobility 6
VLSI Design
b) What do you mean by High level synthesis? What are the II SEMESTER
general steps in High level synthesis? 6
VLSI CAD
OR (Effective from the admitted batch 201213)
6. a) Discuss about Reduced Ordered Binary Decision Diagrams Time: 3 Hours Max.Marks: 60
with an example 6 ------------------------------------------------------------------------------------------------------
Instructions: Each Unit carries 12 marks.
b) Explain briefly about:
Answer all units choosing one question from each unit.
i) Two-Level Logic synthesis ii) High Level Transformations 6 All parts of the unit must be answered in one place only.
UNIT-IV Figures in the right hand margin indicate marks allotted.
------------------------------------------------------------------------------------------------------
7. a) Discuss about longest path algorithm with an example 6
UNIT-I
b) Classify the placement algorithms and explain them in detail 6
1. What are the different graph algorithms used in VLSI physical
OR
design problems and explain
8. a) What are the major constraints and objectives for partitioning a) Graph Search Algorithms
in VLSI? 6 b) Shortest Path Algorithms with an example 12
b) Explain about Kerninghan-Lin algorithm with an example 6 OR
UNIT-V 2. Explain about
a) Linked List of Blocks 4
9. a) Write the algorithm for integer programming based and
b) Explain briefly about the summary of NP hardness and
rectangular based floor planning used in VLSI chip 8
NP-completeness 4
b) Explain the standard cell layout design in combinational logic c) Approximation Algorithms 4
network 4
OR UNIT-II
10. a) What are various floor planning methods? Explain them clearly 8 3. a) Discuss about Switch-level modeling and simulation 6
b) Explain the sequences of Global routing and explain briefly 4 b) Distinguish event driven simulation with compiler driven
simulation and explain the limitations of event driven simulation
with an example 6
[12/II S/215] OR
4. a) Explain the delay in combinational logic network and how
combinational delay can be reduced 6
b) Discuss about:
i) Gate-level modeling ii) Signal modeling 6
 UNIT-III [April-15]
[EPRVD-201B]
5. a) Define Mobility of an operational unit. With an example
explain how ASAP scheduling algorithm is used to determine M.Tech. Degree Examination
Mobility 6
VLSI Design
b) What do you mean by High level synthesis? What are the II SEMESTER
general steps in High level synthesis? 6
VLSI CAD
OR (Effective from the admitted batch 201213)
6. a) Discuss about Reduced Ordered Binary Decision Diagrams Time: 3 Hours Max.Marks: 60
with an example 6 ------------------------------------------------------------------------------------------------------
Instructions: Each Unit carries 12 marks.
b) Explain briefly about:
Answer all units choosing one question from each unit.
i) Two-Level Logic synthesis ii) High Level Transformations 6 All parts of the unit must be answered in one place only.
UNIT-IV Figures in the right hand margin indicate marks allotted.
------------------------------------------------------------------------------------------------------
7. a) Discuss about longest path algorithm with an example 6
UNIT-I
b) Classify the placement algorithms and explain them in detail 6
1. What are the different graph algorithms used in VLSI physical
OR
design problems and explain
8. a) What are the major constraints and objectives for partitioning a) Graph Search Algorithms
in VLSI? 6 b) Shortest Path Algorithms with an example 12
b) Explain about Kerninghan-Lin algorithm with an example 6 OR
UNIT-V 2. Explain about
a) Linked List of Blocks 4
9. a) Write the algorithm for integer programming based and
b) Explain briefly about the summary of NP hardness and
rectangular based floor planning used in VLSI chip 8
NP-completeness 4
b) Explain the standard cell layout design in combinational logic c) Approximation Algorithms 4
network 4
OR UNIT-II
10. a) What are various floor planning methods? Explain them clearly 8 3. a) Discuss about Switch-level modeling and simulation 6
b) Explain the sequences of Global routing and explain briefly 4 b) Distinguish event driven simulation with compiler driven
simulation and explain the limitations of event driven simulation
with an example 6
[12/II S/215] OR
4. a) Explain the delay in combinational logic network and how
combinational delay can be reduced 6
b) Discuss about:
i) Gate-level modeling ii) Signal modeling 6