ALGORITHMS FOR VLSI DESIGN AUTOMATION
II Semester: VLSI SYSTEM DESIGN
Course Code Category Hours / Week Credit Maximum Marks
L T P s
C CIA SEE Total
17CD04204 Foundation
4 0 - 4 40 60 100
Contact Classes: 60 Tutorial Classes: Nil Practical Classes: Nil Total Classes: 60
OBJECTIVES:
Study techniques for electronic design automation (EDA), a.k.a. computer aided design
(CAD)
Study IC technology evolution and their impacts on the development of EDA tools
Study problem-solving (-finding) techniques
To impart knowledge on implementation of graph theory in VLSI
To impart knowledge on automation methods for VLSI physical design
To impart knowledge on automation methods on VLSI interconnects
OUTCOMES:
Gain knowledge on various design methodologies and design automation tools.
Able to Know the different search algorithms.
Able to know the modeling and simulation.
Able to know the logic synthesis.
UNIT - I PRELIMINARIES Classes: 15
Introduction to Design Methodologies, Design Automation tools, Algorithmic Graph Theory,
Computational complexity, Tractable and Intractable problems.
General Purpose Methods For Combinational Optimization:
Backtracking, Branch and Bound, Dynamic Programming, Integer Linear Programming, Local
Search, Simulated Annealing, Tabu search, Genetic Algorithms
UNIT - II LAYOUTS Classes: 10
Layout Compaction, Placement, Floor planning And Routing Problems, Concepts and Algorithms
Modelling And Simulation: Gate Level Modelling and Simulation, Switch level Modeling and
Simulation
UNIT - III LOGIC SYNTHESIS AND VERIFICATION Classes: 10
Basic issues and Terminology, Binary-Decision diagrams, Two-Level logic Synthesis
UNIT - IV HIGH-LEVEL SYNTHESIS Classes: 10
Hardware Models, Internal representation of the input Algorithm, Allocation, Assignment and
Scheduling, Some Scheduling Algorithms, Some aspects of Assignment problem, High-level
Transformations
UNIT - V PHYSICAL DESIGN AUTOMATION OF FPGA’S Classes: 15
FPGA technologies, Physical Design cycle for FPGA‟s, partitioning and Routing for segmented
and staggered Models
Physical Design Automation Of MCM’S
MCM technologies, MCM physical design cycle, Partitioning, Placement- Chip Array based and
Full Custom Approaches, Routing, Maze routing, Multiple stage routing, Topologic routing,
Integrated Pin, Distribution and routing, Routing and Programmable MCM‟s.
Text Books:
1. S.H.Gerez, “Algorithms for VLSI Design Automation”, WILEY Student Edition, John wiley&
Sons (Asia) Pvt. Ltd., 1999.
2. NaveedSherwani, “Algorithms for VLSI Physical Design Automation” ,3rd edition,
Springer International Edition, 2005
Reference Books:
1. Computer Aided Logical Design with Emphasis on VLSI, Hill & Peterson, Wiley, 1993.
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2. Modern VLSI Design Systems on silicon – Wayne Wolf, Pearson Edn Asia, 2/e, 1998.
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