Mixed-Signal Testing &

DfT Techniques

 Outline
z Mixed-Signal Test Problems
z Mixed-Signal DfT Techniques
z IEEE Standard for a Mixed-Signal Test Bus
z DSP-Based Mixed-Signal Testing
z DSP-Based Mixed-Signal SoC Self-Testing

May, 2002 J.L. Huang, EE/GIEE, NTU 2

Mixed-Signal Test Problems
 The Role of Testing
z The role of testing is to detect whether
something went wrong.
z Diagnosis, on the other hand, tries to
determine exactly what went wrong & where
the process has to be altered.
z Test objectives
Design verification
Ensure product quality
Diagnosis & repair

May, 2002 J.L. Huang, EE/GIEE, NTU 4

 What are we after?
z Design errors
z Fabrication errors (caused by human errors)
z Fabrication defects (caused by imperfect
manufacturing process)
z Physical failures

May, 2002 J.L. Huang, EE/GIEE, NTU 5

 Costs of Testing
z Design for testability (DFT)
Chip area overhead and yield reduction
Performance overhead
z Test development
Test generation and fault simulation
Test programming and debugging
z Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost

May, 2002 J.L. Huang, EE/GIEE, NTU 6

 Components of an ATE
z Powerful computer
z Powerful 32-bit Digital Signal Processor
(DSP) for analog testing
z Test Program
written in high-level language) running on the
computer
z Probe Head
actually touches the bare or packaged chip to
perform fault detection experiments
z Probe Card or Membrane Probe
contains electronics to measure signals on chip pin
or pad

May, 2002 J.L. Huang, EE/GIEE, NTU 7

 Automated Test Equipment Cost
z Tester cost = b + (m x)
z Other cost factors
Tester depreciation
Tester maintenance cost
Test operation cost

b m x
Tester segments Base cost Cost per pin Pin count
K$ $
High-performance ASIC/MPU 250 400 2,700 6,000 512
Mixed-Signal 250 350 3,000 18,000 128 192
DfT Tester 100 350 150 650 512 2500
Low-end C / ASIC 200 350 1,200 2,500 256 1,024
Commodity Memory 200+ 800 1,000 1,024
RF 200+ ~50,000 32
[ITRS 2001]
May, 2002 J.L. Huang, EE/GIEE, NTU 8
 Mixed-Signal System-on-Chip

Audio
A
n Digital
a
Storage Video l system
o
g
Interface

Sensors / Transmission
Actuators media

z Analog/mixed-signal circuitries are essential in

real-world systems.

May, 2002 J.L. Huang, EE/GIEE, NTU 9

 Mixed-Signal vs. Digital Testing

Digital Analog
Test signal Single type Multiple types

Need mathematical
Response analysis Direct interpretation
post-processing
Measurement
Low-precision High-precision
requirement
Both catastrophic and
Fault model Mainly catastrophic
parametric
Tolerance range in
Fault-free response Binary vectors
multi-dim. space

May, 2002 J.L. Huang, EE/GIEE, NTU 10

 Analog/Mixed-Signal Testing Problems
z Size not a problem.
z Much harder analog device modeling
No widely-accepted analog fault model.
Infinite signal range.
Tolerances depend on process and measurement
error.
Tester (ATE) introduces measurement error.
Digital / analog substrate coupling noise.
Absolute component tolerances +/- 20%, relative
+/- 0.1%.
Multiple analog fault model mandatory.
z No unique signal flow direction.
May, 2002 J.L. Huang, EE/GIEE, NTU 11
 Current Status
z Specification-based (functional) tests
Tractable and does not need an analog fault
model.
Long test time.
Expensive ATE.
Long test development time: application, setup
dependent.
z Structural ATPG used for digital, just
beginning to be used for analog (exists)
z Separate test for functionality and timing
impossible.
May, 2002 J.L. Huang, EE/GIEE, NTU 12
 The Challenges
z ATE cost problem
Pin inductance (expensive probing)
Multi-GHz frequencies
High pin count (1024)

z High-speed serial interfaces are gaining

growing popularity.
High speed, differential, low voltage swing, large
numbers of pin counts.
z Analog effects appear as digital clock speeds
increase and reach fundamental limits.
May, 2002 J.L. Huang, EE/GIEE, NTU 13
 Solutions?
z Employ DfT techniques to limit the functional
test performance envelope in production by
Reducing I/O data rate requirements,
Enabling low pin count testing, and
Reducing the dependence on expensive
instruments.

z Structural testing methodoloty.

May, 2002 J.L. Huang, EE/GIEE, NTU 14

Mixed-Signal DfT Techniques
 Fundamental Issue of Analog
Measurement* - Precision

z Definition
Measurement sample deviation relative to
measurement mean, e.g. standard deviation (MEAS)
of a set of measurements
z Sources of imprecision: various noise
z Basic technique to increase precision:
integration
the more samples averaged, the better
*S. Sunter, ITC tutorial #15, 1999
May, 2002 J.L. Huang, EE/GIEE, NTU 16
 Fundamental Issue of Analog
Measurement* - Accuracy

z Definition
Measurement mean relative to true mean, e.g.
average measurement error (MEAS - 0)
z Sources of inaccuracy: systematic errors
z Basic technique to increase accuracy:
substraction
e.g. measure with/without stimulus, inverted/non-
inverted
*S. Sunter, ITC tutorial #15, 1999

May, 2002 J.L. Huang, EE/GIEE, NTU 17

 Reconfiguration Techniques
z Bypass to gain accessibility of internal nodes

Analog Analog
function function
sel1 sel2

z Loop around for back-to-back testing

voice Modulator RF

sel2
De- Down-
voice RF
modulator converter
sel1

May, 2002 J.L. Huang, EE/GIEE, NTU 18

 A DfT Technique for SC Filters [Soma VTS94]

z In mission mode:
1
C2
2 2 2
1 1
z In test mode, bypass a filter
stage by converting it to an all-
C1
1 2 C4 pass gain stage
v1 - v2 Open grounding switches
2 1
+ Close signal path switches
v2 = -(C1 / C2||C4) v1
z Gated 2-phase clock signals

May, 2002 J.L. Huang, EE/GIEE, NTU 19

 SW Opamp Design [Huertas VTS96]
Test
z SW opamp
V+
V- With additional inputs: Test, VT
VT Test = 1: unit buffer
Test = 0: regular opamp
Test=1
Test=0 VT is connected to the output of
V+ + VT + previous stage
V- - - z In test mode
Test = 0 for stage under test
Test = 1 for others
z Switches are inserted on small signal
V+
Test
V+
Test
V+
Test path to reduce performance
V- V- V-
degradation
VT VT VT

Stage#1 Stage#2 Stage#3

May, 2002 J.L. Huang, EE/GIEE, NTU 20

 Oscillation BIST [Kaminska VTS96]

z Analog CUT plus added circuitry

Oscillator become an oscillator in test mode
Oscillation induced through positive
Analog feedback
CUT z Defects cause deviations in
Oscillation frequency
Oscillation amplitude
Added z Very sensitive to process variations
circuitry
Causes yield loss

Freq.
counter

May, 2002 J.L. Huang, EE/GIEE, NTU 21

 Analog Checksum [Chatterjee D&T96]

z Sum the voltages at selected

Analog internal nodes
CUT
z Fault effects appear as error
voltage

+
- Error voltage

May, 2002 J.L. Huang, EE/GIEE, NTU 22

 Built-in Current Sensor

Vdd
z Insert current sensor between CUT and
Vdd (Vss)
Current Current
sensor signature z Use current signature to make pass/fail
decision
z Compare to:
CUT DC threshold (on-chip or off-chip)
Expected spectrum (off-chip)
z Cons: resistance in Vdd Path
Vss

May, 2002 J.L. Huang, EE/GIEE, NTU 23

 Analog Output Response Compaction
[Bertrand EDTC 97]

!Ci

Ci

Analog +
CUT Analog
- signature

z Opamp-based integrator for analog signal compaction

z Suffer fault aliasing problem

May, 2002 J.L. Huang, EE/GIEE, NTU 24

 Subband Filtering [Abraham ITC99]
Signature generation / Pass
comparison

Sampled Subband
CUT Pass
filter Signature generation /
response
comparison
Signature generation /
comparison

z Pros
Subband filtering requires relatively less
hardware
More immune from fault aliasing problems
z Cons
Requires on-chip ADC

May, 2002 J.L. Huang, EE/GIEE, NTU 25

IEEE Standard for a Mixed-
Signal Test Bus
 Test Board with Mixed-Signal Parts

z The introduction of analog components to 1149.1

compliant chip introduces new problems.
z The ability to isolate faulty interconnects on the
analog I/O pins does not exist!!
May, 2002 J.L. Huang, EE/GIEE, NTU 27
 Scope of the Standard

z Interconnect test
Testing for opens and shorts
among the interconnections
in a PCA (Printed Circuit
Assembly).
z Parametric test
Making analog characterization measurements.
Testing for presence and value of discrete components in a
PCA.
z Internal test
Testing the internal circuitry of the mixed-signal component
itself regardless of whether it is part of a PCA.
Not mandatory.

May, 2002 J.L. Huang, EE/GIEE, NTU 28

 Feature Overview
z Capabilities
Continuous-time voltage, current access via two analog pins.
Measure R, L, C, gain, etc. with < 1% error.
True differential access, and other options.
1149.1 compliant

z The idea is to include a set of digitally-controllable

analog boundary cells that can perform the following
four functions:
Disconnect the I/O pin from the analog core.
Set the I/O pin at a logic high or low level.
Detect the logic level present on the I/O pin.
Connect the I/O pin to a two-wire analog test bus.

May, 2002 J.L. Huang, EE/GIEE, NTU 29

 A Minimally Configured 1149.4-Conformant
Component Analog boundary
module (ABM)
Boundary-scan path

A
B VH
M VL
VG Analog pins
Core
Circuit
A
B VH
M VL
Analog Test

AB1
AB2
VG
Access Port
(ATAP)
Digital boundary AT1
module (DBM) Test bus interface
circuit (TBIC) AT2
Test Access
Port (TAP)
TDI Test Control Circuitry
TDO
TMS TAP controller
TCK Instruction Register & decoder
May, 2002 J.L. Huang, EE/GIEE, NTU 30
 Required Test Functions for Analog Pins

z Isolation
Connect to core.
Disconnected from core (CD state).
z Perform tests equivalent to 1149.1
Drive pins Vmax, Vmin (DC).
Compare VPIN to pins VTH.
z Facilitate analog parametric tests
Deliver analog ground (VG) via power rail.
Deliver current to pin via AT1 pin and AB1 bus.
Monitor pins voltage via AB2 bus and AT2 pin.

May, 2002 J.L. Huang, EE/GIEE, NTU 31

 Test Access Port (TAP) Pins
z TCK test clock
z TMS test mode select
z TDI test data in
Instruction or scan data
z TDO test data out
Test results or for next chip
z TRST optional reset

May, 2002 J.L. Huang, EE/GIEE, NTU 32

 Analog TAP pins
z AT1 stimulus current bus
At least capable of conveying 100 A
May be any combination of AC and DC
DC 10 KHz minimum bandwidth
Sufficient for state-of-the-art ATE to achieve < 1% error
Convey response output (optional)
z AT2 resultant voltage bus
At least capable of conveying 100 mV
Range: (VSS - 100 mV) to (VDD + 100 mV)
Ensures that protection diodes are not partially activated.
Convey stimulus input (optional)
z AT1N, AT2N inverted pins for differential
testing.
May, 2002 J.L. Huang, EE/GIEE, NTU 33
 1149.4 Board-Level View

TMS
TCK

TDI TDI TDO TDI TDO TDI TDO TDO

AT1
AT2

May, 2002 J.L. Huang, EE/GIEE, NTU 34

 Test Register Architecture
TBIC ABMs DBMs
Boundary Scan Register

Design-Specific
Test Data Register(s)

Bypass Register

MUX O/P
stage TDO
TDI Instruction Register

Test control Instruction

Control signals
circuitry Decoder for register enables,
internal re-configuration,
TMS TAP MUX selection, etc.
TCK Controller

May, 2002 J.L. Huang, EE/GIEE, NTU 35

 ABM Switching Architecture

May, 2002 J.L. Huang, EE/GIEE, NTU 36

 Possible Control Structure for ABM

May, 2002 J.L. Huang, EE/GIEE, NTU 37

 TBIC Switching Architecture

May, 2002 J.L. Huang, EE/GIEE, NTU 38

 TBIC Sample Implementation of the
Control Structure

May, 2002 J.L. Huang, EE/GIEE, NTU 39

 Virtual Probing

May, 2002 J.L. Huang, EE/GIEE, NTU 40

 Extended Interconnect Measurement
Measurement One

May, 2002 J.L. Huang, EE/GIEE, NTU 41

 Extended Interconnect Measurement
Measurement Two

May, 2002 J.L. Huang, EE/GIEE, NTU 42

 Network Measurement

May, 2002 J.L. Huang, EE/GIEE, NTU 43

 Connectivity of Residual Elements

May, 2002 J.L. Huang, EE/GIEE, NTU 44

 Testing the Analog Core

May, 2002 J.L. Huang, EE/GIEE, NTU 45

DSP-Based Mixed-Signal
Testing
 Analog Test Setup

DC

RMS
filter
CUT
CUT PEAK
DC

(etc.)
(etc.) ATE

z Low test throughput.

z Less flexibility.

May, 2002 J.L. Huang, EE/GIEE, NTU 47

 DSP-Based Analog Testing
Synthesizer Digitizer

Analog
RAM DAC ADC RAM
CUT

synchronization

DSP/Vector processor

ATE
z Flexible
single setup for multiple types of tests
z High throughput.
z Performance limited by ADC/DAC.
May, 2002 J.L. Huang, EE/GIEE, NTU 48
 Test Waveform Synthesis
z Test signal
digitized sinusoid
digitized multi-tone
pseudo random

May, 2002 J.L. Huang, EE/GIEE, NTU 49

 Output Response Digitization
z Response analysis:
FFT
IEEE 1057 sinewave fitting
cross-correlation / auto-correlation

May, 2002 J.L. Huang, EE/GIEE, NTU 50

 DSP-based vs. analog ATE
z Increased test throughput
z Reduced switching & settling time
z Device response is memorized and analyzed
for different parameters
z Software DSP doesnt have to be real-time
z Performance limited by ADC/DAC

May, 2002 J.L. Huang, EE/GIEE, NTU 51

DSP-Based Mixed-Signal
SoC Self-Testing
 New Opportunities
z Utilize on-chip DSP capabilities to facilitate
mixed-signal testing.
Test the digital parts first.

z On-chip ATE!!

May, 2002 J.L. Huang, EE/GIEE, NTU 53

 DSP-Based Self-Testing of Analog
Components
z DSP-based BIST on-chip
tester
DAC
Analog
DAC
Analog
ADC
DUT ADC CUT
Relieve the need of expensive
ATE
Reduce external noise DSP/Processor core
z Practical issues
Synchronization Synchronization
Test quality limited by
DAC/ADC
Digital signal processing Digital signal processing
DAC/ADC are not always
Memory
available, and must be tested Memory
first
DSP-based ATE SOC
May, 2002 J.L. Huang, EE/GIEE, NTU 54
 The Delta-Sigma Modulation
Analog input Digital output

Delta-sigma
modulation modulation
noise

fo Hz fs >> 2fo fo Hz

z High sampling rate (fs >> 2fo), low output amplitude resolution
Average output tracks input value
z Allows the use of relatively imperfect components
Suitable for VLSI implementation

May, 2002 J.L. Huang, EE/GIEE, NTU 55

 MADBIST - Mixed Analog-Digital BIST

Testing ADC first!!

DAC ADC DSP

analog sig. gen. f

z Build a precision analog signal generator into the DAC:

z high frequency, pulse density modulated single bit-stream
using modulation technique
z producing high-quality analog sinusoidal/multitone signal
z Could perform SNR, FR and IMD tests for ADC
Ref: Toner & Roberts, ITC93, VTS94

May, 2002 J.L. Huang, EE/GIEE, NTU 56

 Multiple Test Phases......
Analog
P1 oscilator
A/D DSP

P0: Testing DSP

D/A A/D DSP
P1: Testing ADC P2
OR
P2: Testing DAC P1+P2 high-rsl.
D/A A/D DSP
P3: Testing analog (scaling)

blocks
analog
D/A A/D DSP
P3 block

May, 2002 J.L. Huang, EE/GIEE, NTU 57

 Delta-sigma Modulation Based Signal
Generation [Roberts]
Digital signal processing
N-bit Software
N-bit
delta-sigma
DAC
modulator

N-bit DAC
o/p levels

z 1+ bit in DAC 6dB SNR gain

z How to measure the DAC output levels using on-chip
resources?

May, 2002 J.L. Huang, EE/GIEE, NTU 58

 Delta-Sigma Modulation Based
BIST Architecture

ATE ATE DUT DUT

Test stimuli Software 1-bit

1-bitDAC
DAC
& spec. modulator &&LPF
LPF
Programmable Analog
Analog
core + memory CUT
CUT
Pass/fail ?
Response 1-bit
1-bit
analysis modulator
modulator

May, 2002 J.L. Huang, EE/GIEE, NTU 59

 Pesudo-Random Testing
P
Device
R x[n] D/A A/D y[n]
Under
P
Test
G
Cross-correlation

delayed Computing
by x[n-m] the
m samples Average

E{x[n-m]y[n]}
Digital white noise stimulus
Testing multiple specs. in one test session
Effective dynamic testing
Ref: Pan & Cheng, ICCAD95

May, 2002 J.L. Huang, EE/GIEE, NTU 60

 Pseudo-Random Testing

P
Device
R x[n] D/A A/D y[n]
Under
P
Test
G
Auto-correlation

Computing
the
Average

E{y[n]y[n]}

Ref: Pan & Cheng, ICCAD95

May, 2002 J.L. Huang, EE/GIEE, NTU 61

 Automatic Mapping of Tolerance Range

specification space observation space

mapping of

tolerance range

z Tools for automatic mapping of tolerance range from

the given specs. to the observation space are needed
z Perfect mapping may not be possible
Objective: minimize misclassification

May, 2002 J.L. Huang, EE/GIEE, NTU 62

Conclusion
 z Although expected to lag leading-edge device
performance and complexity, DfT techniques
are essential to reduce dependence on
expensive ATE.

z Need more research into the area of structure

testing.
No proven alternative to performance-based
analog testing exists.

May, 2002 J.L. Huang, EE/GIEE, NTU 64

May, 2002 J.L. Huang, EE/GIEE, NTU 65