Systematic Design

of Operational Amplifiers

Willy Sansen
KULeuven, ESAT-MICAS
Leuven, Belgium
[email protected]

Willy Sansen 10-05 061

Table of contents

• Design of Single-stage OTA

• Design of Miller CMOS OTA
• Design for GBW and Phase Margin
• Other specs: Input range, output range, SR, ...

Ref.: Sansen : Analog design essentials, Springer 2006

Willy Sansen 10-05 062

 Single-stage CMOS OTA : GBW

VDD ro
M7 Av = gm1
2
IB
if ro2 = ro4 = ro
v- v+
3 M2
M1 1
vOUT BW =
ro
2π (CL+Cn1)
2 1 CL 2

M3 M4 gm1
GBW =
VSS 2π (CL+Cn1)

Willy Sansen 10-05 063

 CMOS OTA : Maximum GBW

gm1 IB
GBW = gm1 =
2π CL VGS1-VT
IB
v- v+ IB 1
GBWmax =
CL CL VGS1-VT 2π CL

vOUT+ vOUT- 0.2 V

IB = 10 µA CL = 1 pF GBWmax ≈ 10 MHz
[8]
GBW.CL
FOM = = 1000 [800]
IB MHzpF/mA

Willy Sansen 10-05 064

 Single stage CMOS OTA : fnd

VDD gm1
M7 GBW =
2π (CL+Cn1)
IB
v- v+ gm3
M1
3 M2 fnd =
2π Cn2
vOUT
Cn2 ≈ 2CGS3+ CDB3+ CDB1
2 1 CL
≈ 4 CGS3
M3 M4
fT3
VSS fnd ≈
4

Willy Sansen 10-05 065

Simple CMOS OTA : fnd
Av
M5
2x

f
- 3 M2 +
M1 2x f
0o

vOUT -90o
fnd 2fnd
Cn2 2 1 gm3
M3 M4 fnd =
2π Cn2

GBW GBW
PM = 90o - arctan + arctan ≈ 85o
fnd 2 fnd
Willy Sansen 10-05 066
Single stage CMOS OTA : Design 1

GBW = 100 MHz for CL = 2 pF

Techno: Lmin = 0.35 µm; K’n = 60 µA/V2 & K’p = 30 µA/V2

IDS ? W ? L ?

gm = GBW 2π CL = 1.2 mS
VGS-VT gm
VGS-VT = 0.2 V IDS = gm 2 = 10 = 0.12 mA

W IDS Lp = Ln = 1 µm GAIN !
L = K'(VGS-VT)2 =100 Wp = 100 µm; Wn = 50 µm
Willy Sansen 10-05 067
Table of contents

• Design of Single-stage OTA

• Design of Miller CMOS OTA
• Design for GBW and Phase Margin
• Other specs: Input range, output range, SR, ...

Willy Sansen 10-05 068

 Miller CMOS OTA

VDD Two nodes

M7 1 : B
M5
1 4
5
vOUT with high
v- v+ 4
3 M2 Cc Impedance
M1

RL CL cause
two poles
2 1 M6
M3 M4 Cn1 split by Cc
VSS

Willy Sansen 10-05 069

 Miller CMOS OTA : small-signal
v- v+ Cc 4 vOUT GBW= 1MHz
3 M2
M1 ZL CL = 10 pF
RL = 10 kΩ
2 1 gm1 = 7.5 µS
M6
M3 M4 Cn1 go24 = 0.03 µS
Cn1 = 0.37 pF
1 Cc 4 Cc = 1 pF
gm6 = 246 µS
gLo6 = 120 µS
gm1 go24 Cn1 gm6 gLo6 CLn4 = 10.2 pF

IDS1 = 1.1 µA IDS6 = 25 µA

Willy Sansen 10-05 0610
 Miller CMOS OTA : GBW

M7 1 : B gm1 gm6
M5 Av1 = Av2 =
5
go24 gLo6

vOUT BW =
go24
v- v+ 4
3 M2 Cc 2π Av2Cc
M1

RL CL gm1
GBW =
2π Cc
2 1 M6
M4 Cn1
gm6 1
M3 fnd ≈
2π CLn4 Cn1
1+
Cc
Willy Sansen 10-05 0611
Miller CMOS OTA : poles and zero
Cc
fd fz Pole splitting
1pF
starts at
0.1pF
fnd
Cct Cn1
f Cct ≈ ≈ 20 fF
10fF
1k 1M Hz Av2
|Av| Av0
1000 Cc = 0
but is sufficient
for Cc = 1pF
100

10 Cc = 1pF
gm6
BW fz =
1
GBW 2π Cc
0.1 f
1k 1M
Willy Sansen 10-05 0612
Table of contents

• Design of Single-stage OTA

• Design of Miller CMOS OTA
• Design for GBW and Phase Margin
• Other specs: Input range, output range, SR, ...

Willy Sansen 10-05 0613

Miller CMOS OTA: Design plan

gm1
GBW = GBW = 100 MHz and CL = 2 pF
2π Cc
gm6 1
fnd ≈
2π CLn4 Cn1
1+
Cc

Two equations for

Three variables gm1, gm6 and Cc ?!?
Solution : choose gm1 or gm6 or Cc !!!
Willy Sansen 10-05 0614
What is wrong with

choosing Cc = 1 pF ?

Willy Sansen 10-05 0615

Miller CMOS OTA: Design vs Cc

gm1
Choose Cc ≈ 3 Cn1 GBW =
2π Cc
gm6 1
3GBW ≈
2π CLn4 1.3
gm6 CL
≈ 4
gm1 Cc

GBW = 100 MHz and CL = 2 pF

Choose Cn1 < Cc < CL
Choice Cc = 1 pF gives gm1 = 0.6 mS and gm6 = 4.8 mS

Willy Sansen 10-05 0616

Miller CMOS OTA: Design vs Cc

gm gm6min =
gm6
3 GBW (2π CL)
gm1

gm6min

Cc
Ccopt ≈ 4 CL

Willy Sansen 10-05 0617

 1 MHz Miller CMOS OTA: Design vs Cc
mS
2

1.8 GBW = 1 MHz

1.6 CL = 10 pF
Cn1 ct
1.4
gmtot 2gm1 Cn1 = 0.4 pF
1.2

1 K’ = 20 µA/V2
0.8
Cn1 ~ gm6 VGS-VT = 0.2 V
0.6

0.4 L = 10 µm
0.2 gm6
0
0.01 0.1 1 10 100
pF Cc
Cn1 = 0.4 pF

Willy Sansen 10-05 0618

Miller CMOS OTA : Design vs IDS6

Area gm6min =

Area Cc 3 GBW (2π CL)

Area M6

gm6
gm6min gm6opt ≈ 1.3 gm6min

+ 30 %
Willy Sansen 10-05 0619
Miller CMOS OTA : Design vs IDS1

Area

Area M6
Area Cc

CL

gm1

Willy Sansen 10-05 0620

Optimum design for high speed Miller OTA - 1

gm1 CL = α Cc α≈2
GBW =
2π Cc
Cc = β Cn1 = β CGS6 β≈3
gm6 1
fnd = fnd = γ GBW γ≈2
2π CL 1 + Cn1/Cc
CGS = kW k = 2 10 -11 F/cm

fnd gm6 1
GBW = =
γ 2π CL γ (1 + 1/ β)

CL = α Cc = α β Cn1 = α β CGS6 = α β kW6 W6 if CL

Willy Sansen 10-05 0621

 Optimum design Miller for high speed OTA - 2
Elimination of CL yields

gm6 1 W 17 10-5
GBW = gm =
2π kW6 α β γ (1 + 1/ β) L 1 + 2.8 104 L /VGST

fT6 W, L in cm

1 1 8.5 106
GBW = L in cm
2π L6 α β γ (1 + 1/ β) 1 + 2.8 104 L6 / VGST6

GBW is not determined by CL, only by L (and VGST) !!

fT is also determined by L !!!
Willy Sansen 10-05 0622
Optimum design Miller for high speed OTA - 3
Substitution for fT yields gm
fT =
2πCGS

fT6 1 1.35
GBW = fT =
L 1 + 2.8 104 L / VGST
α β γ (1 + 1/ β)
L in cm
fT in MHz
GBW is not determined by CL, only by fT
fT is determined by L (and VGST) !!!

If VGST = 0.2 V, vsat takes over for L < 65 nm (If 0.5 V for L < 0.15 µm)

Willy Sansen 10-05 0623

Maximum GBW versus channel length L
GBW VGS-VT ≈ 0.2 V
GHz
vsat α≈2
10 β≈3
γ≈2
or 16 x
1
K’
fT6
GBW ≈
16
0.1
10 nm 100 nm L 1 µm

Willy Sansen 10-05 0624

Design optimization for high speed Miller OTA

• Choose α β γ
• Find minimum fT6 for specified GBW
• Choose maximum channel length L6 (max. gain)
for a chosen VGS6-VT
• W6 is calculated from CL ,
and determines IDS6
• Cc is calculated from CL through α
• gm1 and IDS1 are calculated from Cc
• Noise is determined by gm1 or Cc

Willy Sansen 10-05 0625

Design Ex. for GBW = 0.4 GHz & CL = 5 pF
• Choose α β γ 2 3 2
• Minimum fT6 for GBW = 0.4 GHz fT6 = 6.4 GHz
• Maximum channel length L6 L6 = 0.5 µm
for a chosen VGS6-VT = 0.2 V
• L6 is taken to be the minimum L
• W6 is calculated from CL , W6 = 417 µm
and determines IDS6 (K’n = 70 µA/V2) IDS6 = 2.3 mA
and determines Cn1 (k = 2 fF/µm) Cn1 = 0.83 pF
• Cc is calculated from CL through α Cc = 2.5 pF
• gm1 and IDS1 are calculated from Cc IDS1 = 0.63 mA
Willy Sansen 10-05 0626
Optimum design Miller for low speed OTA

fT6 fT
GBW = = i (1 - e - i ) ≈ i for small i
α β γ (1 + 1/ β) fTH

2 µ kT/q
fTH =
2π L2

GBW is not determined by CL, only by fT

fT is determined by L and i !!!

Willy Sansen 10-05 0627

Design optimization for low speed Miller OTA

• Choose α β γ
• Find minimum fT6 for specified GBW
• Choose channel length L6 (max. gain), which gives fTH6
• Calculate i6
• W6 is calculated from CL ,
and determines IDST6 and IDS6
• Cc is calculated from CL through α
• gm1 and IDS1 are calculated from Cc
• Noise is determined by gm1 or Cc
Willy Sansen 10-05 0628
 Design Ex. for GBW = 1 MHz & CL = 5 pF

• Choose α β γ 2 3 2
• Minimum fT6 for GBW = 1 MHz fT6 = 16 MHz
• Maximum channel length L6 L6 = 0.5 µm
gives fTH6 fTH6 = 2 GHz
• Inversion coefficient i is i = 0.008
• W6 is calculated from CL , W6 = 417 µm
and determines IDST6 (K’n = 70 µA/V2) IDST6 = 0.33 mA
and determines IDS6 IDS6 = 2.7 µA
and determines Cn1 (k = 2 fF/µm) Cn1 = 0.83 pF
• Cc is calculated from CL through α Cc = 2.5 pF
• gm1 and IDS1 are calculated from Cc IDS1 = 1.6 µA
Willy Sansen 10-05 0629
Table of contents

• Design of Single-stage OTA

• Design of Miller CMOS OTA
• Design for GBW and Phase Margin
• Other : SR, Output Impedance, Noise, ...

Willy Sansen 10-05 0630

Miller CMOS OTA: Specifications 1

1. Introductory analysis
1.1 DC currents and voltages on all nodes
1.2 Small-signal parameters of all transistors

2. DC analysis
2.1 Common-mode input voltage range vs supply Voltage
2.2 Output voltage range vs supply Voltage
2.3 Maximum output current (sink and source)

Willy Sansen 10-05 0631

Miller CMOS OTA: Specifications 2

3. AC and transient analysis

3.1 AC resistance and capacitance on all nodes
3.2 Gain versus frequency : GBW, …
3.3 Gainbandwidth versus biasing current
3.4 Slew rate versus load capacitance
3.5 Output voltage range versus frequency
3.6 Settling time
3.7 Input impedance vs frequency (open & closed loop)
3.8 Output impedance vs frequency (open & closed loop)

Willy Sansen 10-05 0632

Miller CMOS OTA: Specifications 3

4. Specifications related to offset and noise

4.1 Offset voltage versus common-mode input Voltage
4.2 CMRR versus frequency
4.3 Input bias current and offset
4.4 Equivalent input noise voltage versus frequency
4.5 Equivalent input noise current versus frequency
4.6 Noise optimization for capacitive/inductive sources
4.7 PSRR versus frequency
4.8 Distortion

Willy Sansen 10-05 0633

Miller CMOS OTA: Specifications 4

5. Other second-order effects

5.1 Stability for inductive loads
5.2 Switching the biasing transistors
5.3 Switching or ramping the supply voltages
5.4 Different supply voltages, temperatures, ...

Willy Sansen 10-05 0634

M C O : Other specifications

o Common-mode input voltage range

o Output voltage range
o Slew Rate
o Output impedance
o Noise

Willy Sansen 10-05 0635

 Miller CMOS OTA

VDD GBW = 1 MHz

M7 1 : B
M5 CL = 10 pF
5 RL = 10 kΩ
vOUT
v- v+ 4
gm1 = 7.5 µS
3 M2 Cc
M1
IDS1 = 1 µA
RL CL go24 = 0.03 µS
2 gm6 = 246 µS
1 M6
IDS6 = 25 µA
M3 M4
VSS Cc = 1 pF

Willy Sansen 10-05 0636

Miller CMOS OTA : CM Input Voltage Range

VICM
3V

2V VDD
1V VICMmax
0V
VICM
-1V

-2V VSS
VICMmin
-3V
0 1V 2V ±2.5V 3V 4V VDD = |VSS|

Willy Sansen 10-05 0637

Miller CMOS OTA : Output Voltage Range

VOUT Rail-to-rail output if no RL

3V VDD
2V VDD VOUTmax M5

1V
4
vOUT
0V
VOUT
-1V RL CL

-2V VSS
VOUTmin
-3V
0 1V 2V ±2.5V 3V 4V VDD = |VSS|

Willy Sansen 10-05 0638

 Miller CMOS OTA : Slew Rate - 1

1 : B
VDD Switch input :
M7
M5
5
v+ > 1
3 v- > 0
IB1 4 vOUT
v- IB1 C
c
M1
RL CL ∆VOUT
SR =
2 ∆t
1 M6
M3 M4 IB1
VSS SR =
Cc

Willy Sansen 10-05 0639

 Miller CMOS OTA : Slew Rate - 2

vIN vIN

t t

vOUT vOUT
VOUTmax
SR
SR SR
SR t t

SR
SR SR Tmax
≈4 VOUTmax ≈
VOUTmaxfmax 4 fmax 4

Willy Sansen 10-05 0640

Miller CMOS OTA : Slew Rate - 3

Vp VOUT
SR
2 VOUTmax ≈
4 fmax
1.5

SR = 2.2 V/µs
1

0.5

0 f
0 0.2M 0.4M 0.6M 0.8M 1MHz

Willy Sansen 10-05 0641

Design for GBW or SR ?

SR IDS1 IDS1 VGS1-VT

= 4π = ≈ 0.1 ... 0.3 V for MOST (si)
GBW gm1 gm1 2
x10
IDS1 nkT
= ≈ 30 … 50 mV for MOST (wi)
gm1 q
ICE1 kT
= ≈ 26 mV for Bipolar trans.
gm1 q
ICE1 kT
= (1 + gm1RE) ≈ ... 0.5 V with RE
gm1 q
Solomon, JSSC Dec 74, 314-332

Willy Sansen 10-05 0642

High SR by gm reduction

VDD
IB IB SR
1:n 2π GBW
n:1
v- v+
M1 M2
= x (n+1)
M3 M4
vOUT
CL
M5 M6
VSS
Ref. Schmoock, JSSC Dec.75, 407-411

Willy Sansen 10-05 0643

External vs internal Slew Rate

VDD
M5
IB
SRint =
IDS5 Cc

IB C
4 vOUT IDS5
c SRext = is larger !
CL
CL
gm6 CL IDS5
=4 =
1 M6 gm1 Cc IDS1
M4 2IDS1
IDS5
VSS ≈2
CL Cc

Willy Sansen 10-05 0644

Slew Rate and settling

vIN

tTOT = tSlew + t0.1

t
VOUT
vOUT 0.1 % VOUT tSlew =
SR
7
SR t0.1 =
2π BW
t
tSlew t0.1 ln (1000) ≈ 7

Willy Sansen 10-05 0645

 Miller CMOS OTA Output Impedance

VDD GBW = 1 MHz

M7 1 : B
M5 CL = 10 pF
5
ZOUT
v- v+ 4 ZOUTCL
3 M2 Cc
M1
gm1 = 7.5 µS
RL CL IDS1 = 1 µA
go24 = 0.03 µS
2 1 M6
gm6 = 246 µS
M3 M4
IDS6 = 25 µA
VSS
Cc = 1 pF

Willy Sansen 10-05 0646

Miller CMOS OTA : Output impedance ZOUT

ZOUT 1/go56 ≈ 0.5 MΩ

go24
fz =
open loop 2πCc
Av20
fz ≈ 4.8 kHz
1/gm6 ≈ 4 kΩ

Av10 Av with CL

closed loop

f
fd fz GBW fnd
Willy Sansen 10-05 0647
Miller CMOS OTA : Noise density 1

dvin22 Cc
dvin1 2
1 4 vOUT

vin vn1
go24 Cn1 gLo6 CL

vneq gm1vin gm6vn1

2 4/3 2 2/3
dvin1 ≈ 4kT g df dvin2 ≈ 4kT g df
m1 m6

Willy Sansen 10-05 0648

Miller CMOS OTA : Noise density 2
Dominant on linear frequency scale !
dveq 2

dvin22
dvneq22 =
dvin12 |Av1|2
2/3
4kT df
Av102 gm6 gm1
Av10 =
dvneq22 go24

go24
fz =
f 2πCc
fz GBW fnd

Willy Sansen 10-05 0649

Miller CMOS OTA : Integrated Noise
∞
dvnieq2
A
1
vnieq2 = ∫ 1 + (f/ GBW) 2
0
∞
dx
f ∫ 1+x 2
=
π
2
0
GBW GBWn
π vnieq2 = 4kT 4/3 GBW π
= 2 GBW gm1 2

2 4 kT
vnieq =
3 Cc
Cc = 1pF vRs= 74 µVRMS
Willy Sansen 10-05 0650
Noise density vs integrated noise

A 4/3
dvni 2
= 4kT df
gm

∞
dvni2 4kT
f 2
vni = ∫ 1 + (f/ BW) 2
=
3Cc
BW BWn 0

Noise density (V2/Hz) ~ 1/gm (or RS)

Integrated noise (VRMS) ~ 1/Cc

Willy Sansen 10-05 0651

CMOS Miller OTA layout
IN+
IN- GBW = 1 MHz
VSS
CL = 10 pF

SR = 2.2 V/µs

VDD = 5 V

ITOT = 27 µA
OUT IB
370 MHzpF/mA

VDD

Willy Sansen 10-05 0652

Miller CMOS OTA : Exercise

GBW = 50 MHz for CL = 2 pF : use min. IDS6 !

Techno: Lmin = 0.5 µm; K’n = 50 µA/V2 & K’p = 25 µA/V2

CGS = kW (= CoxWL) and k = 2 fF/ µm

VGS -VT = 0.2 V

Find
gm6 IDS6 W6 Cn1 = CGS6 Cc gm1 IDS1 dvineq2 vinRMS

Willy Sansen 10-05 0653

Conclusion : Table of contents

• Design of Single-stage OTA

• Design of Miller CMOS OTA
• Design for GBW and Phase Margin
• Other specs: Input range, output range, SR, ...

Willy Sansen 10-05 0654