Design Verification & Testing ATPG CMPE 418
D-Algorithm -- Roth (IBM 1966)
Roth's D-Algorithm (D-ALG) defined the calculus and algorithms for ATPG using D-
cubes.
Definitions
X Singular cover: Defined to be the minimal set of input signal assignments needed to rep-
resent essential prime implicants in Karnaugh map.
A
d
F
B e
AND a b d NOR d e F
1 0 X 0 4 1 X 0
2 X 0 0 5 X 1 0
3 1 1 1 6 0 0 1
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Design Verification & Testing ATPG CMPE 418
D-Calculus and D-Algorithm
X D-cube: A collapsed truth table entry.
For example, combine rows 3 and 1 of the AND gate singular cover, and express it in
Roth's 5-valued algebra (row 3 is good machine).
D1D
Rows 3 and 2 yield the propagation D-cube:
1DD
A third is D D D
Inverting D to D in each of these yields the 6 D-cubes for the AND gate.
3 of the NOR gate D-cubes are:
D0D
0DD
DDD
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Design Verification & Testing ATPG CMPE 418
D-Calculus and D-Algorithm
X D-intersection: Define how different D-cubes can coexist for different gates in a logic
circuit.
0∩0 = 0∩X = X∩0 = 0
1∩1 = 1∩X = X∩1 = 1
X∩X = X
Rule: If one cube assigns a specific signal value, the other cubes must assign either the
same signal or X
For example, 0 X X intersect 1 X X is the empty cube (incompatible).
D-intersection 0 1 X D D
0 0 φ 0 ψ ψ
1 φ 1 1 ψ ψ
X 0 1 X D D
D ψ ψ D µ λ
D ψ ψ D λ µ
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Design Verification & Testing ATPG CMPE 418
D-Calculus and D-Algorithm
X D-intersection (contd.):
The greek symbols φ and ψ represent incompatible assignments.
If the values are incompatible during propagation or implications, the assignment is
called inconsistent and backtracking is necessary.
Greek symbols µ and λ indicate incompatibilities if both are present in D-cubes with
multiple input D and D.
For example, if only l occurs, invert the Ds in the second cube and perform inter-
section.
X D-contains: A cube A D-contains cube B if the set of A cube vertices contains (is a
superset of) the B cube vertices.
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Design Verification & Testing ATPG CMPE 418
D-Calculus and D-Algorithm
X Primitive D-cubes of failure (PDF): These model faults including:
T SA0 (represented by D)
T SA1 (represented by D)
T Bridging faults (short circuits)
T Arbitrary change in logic gate function (e.g., from AND to OR).
For the AND gate, the PDF for output SA0 is 1 1 D
Here the good machine generates a 1 when both inputs are 1, while the bad
machine generates a 0.
The PDFs for the AND gate output SA1 are 0 X D and X 0 D.
Note the PDF are distinct from the propagation D-cubes.
The former models a failure at the gate.
The latter models the conditions for fault effect propagation.
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Design Verification & Testing ATPG CMPE 418
D-Calculus and D-Algorithm
X Implication procedure: Consists of the following steps:
T Model the fault with the appropriate PDF.
T Select propagation D-cubes to propagate fault-effect to PO(s) (D-drive procedure).
T Select singular cover cubes to justify internal circuit signals (consistency procedure).
The D-algorithm's main problem is that it selects cubes and singular covers arbitrarily dur-
ing test generation.
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Design Verification & Testing ATPG CMPE 418
D-ALG
Select a fault
Start Generate a PDF
no More lines yes Is there D
Pattern to justify? or D on PO?
yes no
Select a line Propagate D-cube Mark the lines to
to justify. and intersect be justified
no no
Inconsistency? Inconsistency?
Consistency yes yes D-Drive
Alt path for yes yes Alt gate for
justification? propagation?
no no
Backup one level Backup one level
select another path select another path
Revisiting no no Options
a node? exhausted?
No pattern
yes exists yes
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Design Verification & Testing ATPG CMPE 418
D-ALG Examples
Assign PDF A B C d e F
A 1 SA0 1 1 1
1 1 d 0 0
D
Singular Cover
B F 0 0
e 2
D 1 1 0
3 0
C 1 0 1
Propagate 0 1
Consistency 1 0
1 0
Truth Table 0 0 1
A B C F A B C d e F
0 0 0 0 Propagation D-cubes D 1 D
0 0 1 0 1 D D
0 1 0 0 D D D
0 1 1 1 D 1 D
1 0 0 0 1 D D
1 0 1 0 D D D
1 1 0 0 D 0 D
1 1 1 0 0 D D
D D D
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Design Verification & Testing ATPG CMPE 418
D-ALG Examples
The following procedure is carried out for d SA0 in the previous circuit:
Step A B C d e F Type of cube
1 1 1 D PDF for AND gate
2 D 0 D Propagation D-cube for NOR gate
3 1 1 0 Singular cover of NAND gate
Example #2:
Consistency
DX k
0 1 4
C0 g
5 1
f
B0 e 0 6 D 3 D
D 7
1 0 h
2
AD
SA0
Assign PDF Propagate
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Design Verification & Testing ATPG CMPE 418
D-ALG Examples
Steps followed to generate test cube (tc):
Step A B C D e f g h k L
D-drive 1 D
2 D 0 D
3 D 0 D 1 D
Consistency 4 or 1 1
5 not 0 1
6 or 0 0 0
7 and 0 0
tc D 0 0 0 0 1 D 1 D
D-chain dies
This example and table is given in Roth's paper.
Several other examples are covered in the paper.
Note that all implications are performed in the consistency procedure here.
A later example by our authors indicates the implications are carried out after each D
propagation step in the D-drive?
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Design Verification & Testing ATPG CMPE 418
D-ALG Examples
Example #3
Consistency 1
F 4
E 1
C 0 1 5
SA0 1 D
B 1 6 3
D
D
1
A 1 2
Assign PDF Propagate
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Design Verification & Testing ATPG CMPE 418
D-ALG Examples
Example #4
e
f 5 0 X
r
n
1 D 1
A 1 d g SA1 t
6 m
B 1 1 k 4 s 2 D Y
1 p q 0
3
h
u
D
9 i 7 v
8 D
1 Z
C
Assign PDF Propagate Consistency
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