Integrated Circuit

True RMS-to-DC Converter

Data Sheet AD536A
FEATURES FUNCTIONAL BLOCK DIAGRAM
True rms-to-dc conversion AD536A
Laser trimmed to high accuracy ABSOLUTE
VIN VALUE
±0.2% maximum error (AD536AK)
±0.5% maximum error (AD536AJ)
Wide response capability dB
SQUARER/
Computes rms of ac and dc signals COM DIVIDER

450 kHz bandwidth: V rms > 100 mV +VS +

2 MHz bandwidth: V rms > 1 V CAV

Signal crest factor of 7 for 1% error CURRENT

MIRROR
dB output with 60 dB range
25kΩ
Low power: 1.2 mA quiescent current RL
Single- or dual-supply operation IOUT
Monolithic integrated circuit +VS
−55°C to +125°C operation (AD536AS) BUFFER IN
BUF

25kΩ
BUFFER
GENERAL DESCRIPTION OUT

00504-001
80kΩ
The AD536A is a complete monolithic integrated circuit that
–VS
performs true rms-to-dc conversion. It offers performance
comparable or superior to that of hybrid or modular units costing Figure 1.
much more. The AD536A directly computes the true rms value of The AD536A is available in two accuracy grades (J and K) for
any complex input waveform containing ac and dc components. commercial temperature range (0°C to 70°C) applications, and
A crest factor compensation scheme allows measurements with 1% one grade (S) rated for the −55°C to +125°C extended range.
error at crest factors up to 7. The wide bandwidth of the device The AD536AK offers a maximum total error of ±2 mV ± 0.2%
extends the measurement capability to 300 kHz with less than 3 dB of reading, while the AD536AJ and AD536AS have maximum
errors for signal levels greater than 100 mV. errors of ±5 mV ± 0.5% of reading. All three versions are available
An important feature of the AD536A, not previously available in a hermetically sealed 14-lead DIP or a 10-pin TO-100 metal
in rms converters, is an auxiliary dB output pin. The logarithm header package. The AD536AS is also available in a 20-terminal
of the rms output signal is brought out to a separate pin to allow leadless hermetically sealed ceramic chip carrier.
the dB conversion, with a useful dynamic range of 60 dB. Using
The AD536A computes the true root-mean-square level of a
an externally supplied reference current, the 0 dB level can be
complex ac (or ac plus dc) input signal and provides an equiva-
conveniently set to correspond to any input level from 0.1 V to
lent dc output level. The true rms value of a waveform is a more
2 V rms.
useful quantity than the average rectified value because it relates
The AD536A is laser trimmed to minimize input and output offset directly to the power of the signal. The rms value of a statistical
voltage, to optimize positive and negative waveform symmetry signal also relates to its standard deviation.
(dc reversal error), and to provide full-scale accuracy at 7 V rms.
An external capacitor is required to perform measurements to the
As a result, no external trims are required to achieve the rated
fully specified accuracy. The value of this capacitor determines the
unit accuracy.
low frequency ac accuracy, ripple amplitude, and settling time.
The input and output pins are fully protected. The input circuitry
The AD536A operates equally well from split supplies or a
can take overload voltages well beyond the supply levels. Loss of
single supply with total supply levels from 5 V to 36 V. With
supply voltage with the input connected to external circuitry does
1 mA quiescent supply current, the device is well suited for a
not cause the device to fail. The output is short-circuit protected.
wide variety of remote controllers and battery-powered
instruments.

Rev. G Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1976–2019 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD536A Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Frequency Response .....................................................................9
General Description ......................................................................... 1 AC Measurement Accuracy and Crest Factor ...........................9
Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 11
Revision History ............................................................................... 2 Typical Connections .................................................................. 11
Specifications..................................................................................... 3 Optional External Trims For High Accuracy ......................... 11
Absolute Maximum Ratings............................................................ 5 Single-Supply Operation ........................................................... 12
ESD Caution .................................................................................. 5 Choosing the Averaging Time Constant ................................. 12
Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 14
Theory of Operation ........................................................................ 8 Ordering Guide .......................................................................... 15
Connections for dB Operation ................................................... 8

REVISION HISTORY
3/2019—Rev. F to Rev. G Change to Figure 2 ............................................................................5
Changes to Figure 5 and Table 5 ..................................................... 7 Changes to Figure 15...................................................................... 10
Change to Figure 16 ....................................................................... 12 Changes to Connections for dB Operation Section .................. 11
Changes to Ordering Guide .......................................................... 15 Changes to Figure 17...................................................................... 12
Changes to Frequency Response Section .................................... 12
11/2014—Rev. E to Rev. F Updated Outline Dimensions ....................................................... 14
Change to Figure 1 ........................................................................... 1 Changes to Ordering Guide .......................................................... 15
Changes to Table 1 ............................................................................ 3
Change to Figure 16 ....................................................................... 12 3/2006—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 15 Updated Format .................................................................. Universal
Changed Product Description to General Description ................1
7/2012—Rev. D to Rev. E Changes to General Description .....................................................1
Reorganized Layout ............................................................ Universal Changes to Table 1.............................................................................3
Changes to Figure 1 .......................................................................... 1 Changes to Table 2.............................................................................5
Changes to Figure 6 .......................................................................... 8 Added Pin Configurations and Function Descriptions ...............6
Changes to Figure 7 .......................................................................... 9 Changed Standard Connection to Typical Connections .............8
Changes to Figure 13, Figure 14, and Figure 15 ......................... 11 Changed Single Supply Connection to Single Supply
Changes to Figure 16, Figure 17, and Single-Supply Operation Operation............................................................................................9
Section .............................................................................................. 12 Changes to Connections for dB Operation................................. 11
Changes to Figure 21 ...................................................................... 13 Changes to Figure 17...................................................................... 12
Updated Outline Dimensions ....................................................... 14 Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
8/2008—Rev. C to Rev. D
Changes to Features Section............................................................ 1 6/1999—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Figure 1 .......................................................................... 1 1/1976—Revision 0: Initial Version
Changes to Table 2 ............................................................................ 5

Rev. G | Page 2 of 15
Data Sheet AD536A

SPECIFICATIONS
TA = +25°C and ±15 V dc, unless otherwise noted.

Table 1.
AD536AJ AD536AK AD536AS
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
TRANSFER FUNCTION VOUT = √Avg(VIN)2 VOUT = √Avg(VIN)2 VOUT = √Avg(VIN)2
CONVERSION ACCURACY
Total Error, Internal Trim1 ±5 ± 0.5 ±2 ± 0.2 ±5 ± 0.5 mV ± % of rdg
(See Figure 13)
vs. Temperature
TMIN to +70°C ±0.1 ± 0.01 ±0.05 ± ±0.1 ± mV ± % of rdg/°C
0.005 0.005
+70°C to +125°C ±0.3 ± mV ± % of rdg/°C
0.005
vs. Supply Voltage ±0.1 ± 0.01 ±0.1 ± 0.01 ±0.1 ± 0.01 mV ± % of rdg/V
DC Reversal Error ±0.2 ±0.1 ±0.2 mV ± % of rdg
Total Error, External Trim1 ±3 ± 0.3 ±2 ± 0.1 ±3 ± 0.3 mV ± % of rdg
(See Figure 16)
ERROR VS. CREST FACTOR2
Crest Factor 1 to Crest Factor 2 Specified accuracy Specified accuracy Specified accuracy
Crest Factor = 3 −0.1 −0.1 −0.1 % of rdg
Crest Factor = 7 −1.0 −1.0 −1.0 % of rdg
FREQUENCY RESPONSE3
Bandwidth for 1% Additional
Error (0.09 dB)
VIN = 10 mV 5 5 5 kHz
VIN = 100 mV 45 45 45 kHz
VIN = 1 V 120 120 120 kHz
±3 dB Bandwidth
VIN = 10 mV 90 90 90 kHz
VIN = 100 mV 450 450 450 kHz
VIN = 1 V 2.3 2.3 2.3 MHz
AVERAGING TIME CONSTANT 25 25 25 ms/μF
(See Figure 19)
INPUT CHARACTERISTICS
Signal Range, ±15 V Supplies
Continuous RMS Level 0 to 7 0 to 7 0 to 7 V rms
Peak Transient Input ±20 ±20 ±20 V peak
Continuous RMS Level, 0 to 2 0 to 2 0 to 2 V rms
VS = ±5 V
Peak Transient Input, ±7 ±7 ±7 V peak
VS = ±5 V
Maximum Continuous ±25 ±25 ±25 V peak
Nondestructive Input Level
(All Supply Voltages)
Input Resistance 13.33 16.67 20 13.33 16.67 20 13.33 16.67 20 kΩ
Input Offset Voltage 0.8 ±2 0.5 ±1 0.8 ±2 mV
OUTPUT CHARACTERISTICS
Offset Voltage, VIN = COM ±1 ±2 ±0.5 ±1 ±2 mV
(See Figure 13)
vs. Temperature ±0.1 ±0.1 ±0.2 mV/°C
vs. Supply Voltage ±0.1 ±0.1 ±0.2 mV/V
Voltage Swing, ±15 V Supplies 0 to +11 +12.5 0 to +11 +12.5 0 to +11 +12.5 V
± 5 V Supply 0 to +2 0 to +2 0 to +2 V
dB OUTPUT, 0 dB = 1 V rms
(See Figure 7)
Error, 7 mV < VIN < 7 V rms ±0.4 ±0.6 ±0.2 ±0.3 ±0.5 ±0.6 dB
Scale Factor −3 −3 −3 mV/dB
Scale Factor Temperature −0.033 −0.033 −0.033 dB/°C
Coefficient
Uncompensated +0.33 +0.33 +0.33 % of rdg/°C
IREF for 0 dB = 1 V rms 5 20 80 5 20 80 5 20 80 μA
IREF Range 1 100 1 100 1 100 μA

Rev. G | Page 3 of 15
AD536A Data Sheet
AD536AJ AD536AK AD536AS
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
IOUT TERMINAL
IOUT Scale Factor 40 40 40 μA/V rms
IOUT Scale Factor Tolerance ±10 ±20 ±10 ±20 ±10 ±20 %
Output Resistance 20 25 30 20 25 30 20 25 30 kΩ
Voltage Compliance −VS to −VS to −VS to V
(+VS − 2.5 V) (+VS − 2.5 V) (+VS − 2.5 V)
BUFFER AMPLIFIER
Input and Output Voltage −VS to −VS to −VS to V
Range (+VS − 2.5V) (+VS − 2.5V) (+VS − 2.5V)
Input Offset Voltage, RS = 25 kΩ ±0.5 ±4 ±0.5 ±4 ±0.5 ±4 mV
Input Bias Current 20 60 20 60 20 60 nA
Input Resistance 108 108 108 Ω
Output Current (+5 mA, (+5 mA, (+5 mA,
−130 μA) −130 μA) −130 μA)
Short-Circuit Current 20 20 20 mA
Output Resistance 0.5 0.5 0.5 Ω
Small-Signal Bandwidth 1 1 1 MHz
Slew Rate4 5 5 5 V/μs
POWER SUPPLY
Voltage Rated Performance ±15 ±15 ±15 V
Dual Supply ±3.0 ±18 ±3.0 ±18 ±3.0 ±18 V
Single Supply +5 +36 +5 +36 +5 +36 V
Quiescent Current
Total VS, 5 V to 36 V, TMIN to TMAX 1.2 2 1.2 2 1.2 2 mA
TEMPERATURE RANGE
Rated Performance 0 +70 0 +70 −55 +125 °C
Storage −55 +150 −55 +150 −55 +150 °C
NUMBER OF TRANSISTORS 65 65 65

1
Accuracy is specified for 0 V to 7 V rms, dc or 1 kHz sine wave input with the AD536A connected as in the figure referenced.
2
Error vs. crest factor is specified as an additional error for 1 V rms rectangular pulse input, pulse width = 200 μs.
3
Input voltages are expressed in volts rms, and error is expressed as a percentage of the reading.
4
With 2 kΩ external pull-down resistor.

Rev. G | Page 4 of 15
Data Sheet AD536A

ABSOLUTE MAXIMUM RATINGS

Stresses at or above those listed under Absolute Maximum
Table 2.
Ratings may cause permanent damage to the product. This is a
Parameter Rating
stress rating only; functional operation of the product at these
Supply Voltage
or any other conditions above those indicated in the operational
Dual Supply ±18 V
section of this specification is not implied. Operation beyond
Single Supply +36 V
the maximum operating conditions for extended periods may
Internal Power Dissipation 500 mW
affect product reliability.
Maximum Input Voltage ±25 V peak
Buffer Maximum Input Voltage ±VS ESD CAUTION
Maximum Input Voltage ±25 V peak
Storage Temperature Range −55°C to +150°C
Operating Temperature Range
AD536AJ/AD536AK 0°C to +70°C
AD536AS −55°C to +125°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Rating 1000 V
Thermal Resistance θJA1
10-Pin Header (H-10 Package) 150°C/W
20-Terminal LCC (E-20 Package) 95°C/W
14-Lead SBDIP (D-14 Package) 95°C/W
14-Lead CERDIP (Q-14 Package) 95°C/W
1
θJA is specified for the worst-case conditions, that is, a device soldered in a
circuit board for surface-mount packages.

0.1315 (3.340)
+VS COM RL
14 10 9

IOUT
8

0.0807
(2.050)

VIN
1A1
BUF IN
VIN 7
1B1

–VS CAV dB BUF OUT

3 4 5 6
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE
TO-100 14-LEAD CERAMIC DIP PACKAGE.
1BOTHPADS SHOWN MUST BE CONNECTED TO VIN.
THE AD536A IS AVAILABLE IN LASER-TRIMMED CHIP FORM.
00504-002

SUBSTRATE CONNECTED TO –VS.

Figure 2. Die Dimensions and Pad Layout

Dimensions shown in inches and (millimeters)

Rev. G | Page 5 of 15
AD536A Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VIN 1 14 +VS
NC 2 13 NC
–VS 3 AD536A 12 NC
CAV 4 TOP VIEW 11 NC
(Not to Scale)
dB 5 10 COM

BUF OUT 6 9 RL
BUF IN 7 IOUT

00504-003
8

NC = NO CONNECT

Figure 3. D-14 and Q-14 Packages Pin Configuration

Table 3. D-14 and Q-14 Packages Pin Function Descriptions

Pin No. Mnemonic Description
1 VIN Input Voltage
2 NC No Connection
3 −VS Negative Supply Voltage
4 CAV Averaging Capacitor
5 dB Log (dB) Value of the RMS Output Voltage
6 BUF OUT Buffer Output
7 BUF IN Buffer Input
8 IOUT RMS Output Current
9 RL Load Resistor
10 COM Common
11 NC No Connection
12 NC No Connection
13 NC No Connection
14 +VS Positive Supply Voltage

IOUT
RL 10 BUF IN
1 9

COM 2 8 BUF OUT

AD536A
TOP VIEW
(Not to Scale)
+VS 3 7 dB

4 6
00504-004

VIN 5 CAV
–VS

Figure 4. H-10 Package Pin Configuration

Table 4. H-10 Package Pin Function Descriptions

Pin No. Mnemonic Description
1 RL Load Resistor
2 COM Common
3 +VS Positive Supply Voltage
4 VIN Input Voltage
5 −VS Negative Supply Voltage
6 CAV Averaging Capacitor
7 dB Log (dB) Value of the RMS Output Voltage
8 BUF OUT Buffer Output
9 BUF IN Buffer Input
10 IOUT RMS Output Current

Rev. G | Page 6 of 15
Data Sheet AD536A

+VS
VIN
NC

NC

NC
3 2 1 20 19

–VS 4 18 NC

NC 5 AD536A 17 NC
CAV 6 TOP VIEW 16 NC
(Not to Scale)
NC 7 15 NC

dB 8 14 COM

9 10 11 12 13

BUF IN

IOUT

RL
BUF OUT

NC

00504-005
NC = NO CONNECT

Figure 5. E-20-1 Package Pin Configuration

Table 5. E-20-1 Package Pin Function Descriptions

Pin No. Mnemonic Description
1 NC No Connection
2 VIN Input Voltage
3 NC No Connection
4 −VS Negative Supply Voltage
5 NC No Connection
6 CAV Averaging Capacitor
7 NC No Connection
8 dB Log (dB) Value of the RMS Output Voltage
9 BUF OUT Buffer Output
10 BUF IN Buffer Input
11 NC No Connection
12 IOUT RMS Output Current
13 RL Load Resistor
14 COM Common
15 NC No Connection
16 NC No Connection
17 NC No Connection
18 NC No Connection
19 NC No Connection
20 +VS Positive Supply Voltage

Rev. G | Page 7 of 15
AD536A Data Sheet

THEORY OF OPERATION
The AD536A embodies an implicit solution of the rms equation The current mirror also produces the output current, IOUT, which
that overcomes the dynamic range as well as other limitations equals 2I4. IOUT can be used directly or can be converted to a
inherent in a straightforward computation of rms. The actual voltage with R2 and buffered by A4 to provide a low impedance
computation performed by the AD536A follows the equation voltage output. The transfer function of the AD536A results in
the following:
V 2 
V rms  Avg  IN  VOUT = 2R2 × I rms = VIN rms
 V rms 
The dB output is derived from the emitter of Q3 because the
Figure 6 is a simplified schematic of the AD536A. Note that it is voltage at this point is proportional to –log VIN. The emitter
subdivided into four major sections: absolute value circuit follower, Q5, buffers and level shifts this voltage so that the dB
(active rectifier), squarer/divider, current mirror, and buffer output voltage is zero when the externally supplied emitter
amplifier. The input voltage (VIN), which can be ac or dc, is current (IREF) to Q5 approximates I3.
converted to a unipolar current (I1) by the active rectifiers
(A1, A2). I1 drives one input of the squarer/divider, which has CONNECTIONS FOR dB OPERATION
the transfer function The logarithmic (or decibel) output of the AD536A is one of
2
I4 = I /I3
I
its most powerful features. The internal circuit computing dB
works accurately over a 60 dB range. The connections for dB
The output current, I4, of the squarer/divider drives the current measurements are shown in Figure 7.
mirror through a low-pass filter formed by R1 and the exter-
nally connected capacitor, CAV. If the R1 CAV time constant is Select the 0 dB level by adjusting R1 for the proper 0 dB reference
much greater than the longest period of the input signal, then current (which is set to cancel the log output current from the
I4 is effectively averaged. The current mirror returns a current squarer/divider at the desired 0 dB point). The external op amp
I3, which equals Avg[I4], back to the squarer/divider to complete provides a more convenient scale and allows compensation of
the implicit rms computation. Thus, the +0.33%/°C scale factor drift of the dB output pin.

I4 = Avg[II2/I4] = II rms The temperature-compensating resistor, R2, is available online

in several styles from Precision Resistor Company, Inc., (Part
CURRENT MIRROR
14
Number AT35 and Part Number ST35). The average temperature
+VS coefficients of R2 and R3 result in the +3300 ppm required to
10 compensate for the dB output. The linear rms output is available
COM
R1 0.4mA at Pin 8 on the DIP or Pin 10 on the header device with an output
0.2mA 25kΩ FS
I3
ABSOLUTE VALUE; FS
4 8 9
impedance of 25 kΩ. Some applications require an additional
VOLTAGE-CURRENT
A3 IOUT R2 RL buffer amplifier if this output is desired.
CONVERTER I2 25kΩ
I1
Q1 BUF
5 For dB calibration,
R4
|VIN|R–1 IN BUFFER dB
VIN 50kΩ Q3 OUT
7
A4
1. Set VIN = 1.00 V dc or 1.00 V rms.
1
Q2 Q5 2. Adjust R1 for dB output = 0.00 V.
A1 Q4 6
12kΩ A2 25kΩ 3. Set VIN = +0.1 V dc or 0.10 V rms.
BUF
R3 12kΩ ONE-QUADRANT 80kΩ OUT
25kΩ SQUARER/DIVIDER
4. Adjust R5 for dB output = −2.00 V.
3 Any other desired 0 dB reference level can be used by setting
00504-106

NOTES –VS
1. PINOUTS ARE FOR 14-LEAD DIP. VIN and adjusting R1 accordingly. Note that adjusting R5 for the
Figure 6. Simplified Schematic proper gain automatically provides the correct temperature
compensation.

Rev. G | Page 8 of 15
Data Sheet AD536A

VIN +VS +VS

ABSOLUTE
1 VALUE 14
4.6V TO 18V
+E
NC 2 AD536A 13 NC
–VS SQUARER/ EOUT
–VS 3 DIVIDER 12 NC AD580J
C1, CAV 2.5V dB SCALE
CAV FACTOR ADJUST

+
+VS 4 11 NC R4
–E 33.2kΩ
C2 dB COM R1
5 CURRENT 10
MIRROR 500kΩ +VS R5
0.1µF RL 5kΩ
BUF OUT
6 9 0dB
dB OUT 25kΩ REF R6 7
24.9kΩ 2
3mV/dB BUF IN ADJUST
7 BUF 8 R3
IOUT
60.4Ω
OP77 6
LINEAR TEMPERATURE
rms 3
4 COMPENSATED
OUTPUT R21 dB OUTPUT
1kΩ +100mV/dB
–VS

00504-107
1SPECIAL TC COMPENSATION RESISTOR, +3300ppm/°C,
PRECISION RESISTOR COMPANY PART NUMBER AT 35 OR PART NUMBER ST35.
Figure 7. dB Connection

FREQUENCY RESPONSE Figure 9 illustrates a curve of reading error for the AD536A for
The AD536A utilizes a logarithmic circuit in performing the a 1 V rms input signal with crest factors from 1 to 11. A rectan-
implicit rms computation. As with any log circuit, bandwidth gular pulse train (pulse width = 100 μs) was used for this test
is proportional to signal level. The solid lines in the graph of because it is the worst-case waveform for rms measurement (all
Figure 8 represent the frequency response of the AD536A at of the energy is contained in the peaks). The duty cycle and
input levels from 10 mV rms to 7 V rms. The dashed lines indicate peak amplitude were varied to produce crest factors from 1 to
the upper frequency limits for 1%, 10%, and ±3 dB of reading 11 while maintaining a constant 1 V rms input amplitude.
T
additional error. For example, note that a 1 V rms signal produces өO
less than 1% of reading additional error up to 120 kHz. A 10 mV VP η = DUTY CYCLE =
100µs
T
signal can be measured with 1% of reading additional error 0 CF = 1/√η
өIN (rms) = 1 V rms
(100 μV) up to only 5 kHz.
100µs

1
10
INCREASE IN ERROR (% of Reading)

7V rms INPUT 1%
10% 0
1 ±3dB
VOUT (V)

1V rms INPUT
–1
0.1
100mV rms INPUT
–2

0.01
10mV rms INPUT
–3
00504-016

1k 10k 100k 1M 10M

–4 00504-017
FREQUENCY (Hz) 1 2 3 4 5 6 7 8 9 10 11
CREST FACTOR
Figure 8. High Frequency Response
Figure 9. Error vs. Crest Factor
AC MEASUREMENT ACCURACY AND CREST
FACTOR
INCREASE IN ERROR

Crest factor is often overlooked when determining the accuracy

(% OF READING)

of an ac measurement. The definition of crest factor is the ratio 10

1V rms CF = 10
of the peak signal amplitude to the rms value of the signal
(CF = VP/V rms). Most common waveforms, such as sine and 1
triangle waves, have relatively low crest factors (<2). Waveforms 1V rms CF = 3

that resemble low duty cycle pulse trains, such as those occurring
0.1
00504-018

in switching power supplies and SCR circuits, have high crest 1µs 10µs 100µs 1000µs

factors. For example, a rectangular pulse train with a 1% duty PULSE WIDTH (µs)

cycle has a crest factor of 10 (CF = 1√n). Figure 10. Error vs. Pulse Width Rectangular Pulse

Rev. G | Page 9 of 15
AD536A Data Sheet
25
25

20
20

±PEAK INPUT OR OUTPUT (V)

±PEAK INPUT OR OUTPUT (V)

VIN
VIN
15
15
VOUT

10 10
VOUT

5 5

2.5

00504-022
0
0 5 10 20 30

00504-019
±6 ±10 ±16 ±18
VOLTS (DUAL SUPPLY) VOLTS (SINGLE SUPPLY)

Figure 11. Input and Output Voltage Ranges vs. Figure 12. Input and Output Voltage Ranges vs.
Dual Supply Single Supply

Rev. G | Page 10 of 15
Data Sheet AD536A

APPLICATIONS INFORMATION
CAV VIN +VS
TYPICAL CONNECTIONS
NC NC NC
The AD536A is simple to connect to for the majority of high 3 2 1 20 19
accuracy rms measurements, requiring only an external capaci- –VS
–VS ABSOLUTE
4 VALUE 18 NC
tor to set the averaging time constant. The standard connection AD536A
NC 5 SQUARER/ 17 NC
is shown in Figure 13 through Figure 15. In this configuration, CAV DIVIDER
6 16 NC
the AD536A measures the rms of the ac and dc levels present at
the input, but shows an error for low frequency input as a function NC 7 CURRENT 15 NC
MIRROR
BUF COM
of the filter capacitor, CAV, as shown in Figure 19. Thus, if a 4 μF dB 8 25kΩ 14

capacitor is used, the additional average error at 10 Hz is 0.1%; 9 10 11 12 13

at 3 Hz, the additional average error is 1%. VOUT

BUF IN

IOUT
BUF OUT

RL
NC

00504-021
The accuracy at higher frequencies is according to specification.
To reject the dc input, add a capacitor in series with the input,
Figure 15. 20-Terminal Standard RMS Connection
as shown in Figure 17. Note that the capacitor must be nonpolar.
If the AD536A supply rails contain a considerable amount of The input and output signal ranges are a function of the supply
high frequency ripple, it is advisable to bypass both supply pins voltages; these ranges are shown in Figure 11 and Figure 12.
to ground with 0.1 μF ceramic capacitors, located as close to the The AD536A can also be used in an unbuffered voltage output
device as possible. mode by disconnecting the input to the buffer. The output then
CAV
appears unbuffered across the 25 kΩ resistor. The buffer ampli-
AD536A fier can then be used for other purposes. Further, the AD536A
VIN +VS can be used in a current output mode by disconnecting the
VIN ABSOLUTE
1 14 +VS
VALUE 25 kΩ resistor from ground. The output current is available at
NC 2 13 NC
–VS
Pin 8 (IOUT, Pin 10 on the H-10 package) with a nominal scale of
SQUARER/
–VS 3 12 NC
DIVIDER 40 μA per V rms input positive output.
4 11 NC
CAV
dB 5 CURRENT 10
COM OPTIONAL EXTERNAL TRIMS FOR HIGH
MIRROR
VOUT
BUF OUT
6 9
ACCURACY
25kΩ RL
BUF IN 7 BUF 8 The accuracy and offset voltage of the AD536A is adjustable
IOUT
00504-006

with external trims, as shown in Figure 16. R4 trims the offset.

Note that the offset trim circuit adds 365 Ω in series with the
Figure 13. 14-Lead Standard RMS Connection
internal 25 kΩ resistor. This causes a 1.5% increase in scale factor,
IOUT
which is compensated for by R1. The scale factor adjustment
RL
BUF IN range is ±1.5%.
25kΩ

AD536A BUF OUT The trimming procedure is as follows:

COM
BUF VOUT
CURRENT
MIRROR
1. Ground the input signal, VIN, and adjust R4 to provide 0 V
+VS
output from Pin 6. Alternatively, adjust R4 to provide the
+VS SQUARER/
DIVIDER dB correct output with the lowest expected value of VIN.
ABSOLUTE
2. Connect the desired full-scale input level to VIN, either dc
VALUE
VIN or a calibrated ac signal (1 kHz is the optimum frequency).
CAV
00504-020

3. Trim R1 to provide the correct output at Pin 6. For example,

CAV –VS
1.000 V dc input provides 1.000 V dc output. A ±1.000 V
Figure 14. 10-Pin Standard RMS Connection peak-to-peak sine wave should provide a 0.707 V dc output.
Any residual errors are caused by device nonlinearity.
The major advantage of external trimming is to optimize device
performance for a reduced signal range; the AD536A is
internally trimmed for a 7 V rms full-scale range.

Rev. G | Page 11 of 15
AD536A Data Sheet
CAV
SCALE
CHOOSING THE AVERAGING TIME CONSTANT
FACTOR
ADJUST
The AD536A computes the rms of both ac and dc signals. If the
+VS input is a slowly varying dc signal, the output of the AD536A
VIN ABSOLUTE +VS
1 VALUE 14
R1 tracks the input exactly.
500Ω AD536A +VS
NC 2 13 NC
–VS SQUARER/ R4 OFFSET At higher frequencies, the average output of the AD536A
–VS 3 DIVIDER 12 NC 50kΩ ADJUST
approaches the rms value of the input signal. The actual output
4 11 NC –VS
CAV of the AD536A differs from the ideal output by a dc (or average)
COM R3
dB 5 CURRENT 10 750kΩ
error and some amount of ripple, as shown in Figure 18.
MIRROR
BUF OUT EO
VOUT 6 9
25kΩ RL R2
BUF IN 365Ω
7 BUF 8 IDEAL EO
IOUT
25kΩ

00504-007
DC ERROR = EO – EO (IDEAL)

Figure 16. Optional External Gain and Output Offset Trims

AVERAGE EO – EO
SINGLE-SUPPLY OPERATION DOUBLE FREQUENCY
RIPPLE

00504-009
Refer to Figure 17 for single supply-rail configurations between
5 V and 36 V. When powered from a single supply, the input TIME

stage (VIN pin) is internally biased at a voltage between ground Figure 18. Typical Output Waveform for Sinusoidal Input
and the supply, and the input signal ac coupled. Biasing the The dc error is dependent on the input signal frequency and
device between the supply and ground is simply a matter of the value of CAV. Use Figure 19 to determine the minimum value
connecting the COM pin to an external resistor divider and of CAV, which yields a given percentage of dc error above a given
bypassing to ground. The resistor values are large, minimizing frequency using the standard rms connection.
power consumption, as the COM pin current is only 5 μA.
The ac component of the output signal is the ripple. There are
Note that the 10 kΩ and 20 kΩ resistors connected to the COM pin two ways to reduce the ripple. The first method involves using a
(Figure 17) are asymmetrical, that is, the voltage at the COM pin is large value of CAV. Because the ripple is inversely proportional
1/3 of the supply. This ratio of input bias to supply is optimum to CAV, a tenfold increase in this capacitance affects a tenfold
for the precision rectifier (aka absolute value circuit) input reduction in ripple.
circuit employed for rectifying ac input waveforms and ensures
When measuring waveforms with high crest factors, such as low
full input symmetry for low signal voltages.
duty cycle pulse trains, the averaging time constant should be at
Capacitor C2 is required for AC input coupling, however an least 10 times the signal period. For example, a 100 Hz pulse
external dc return is unnecessary because biasing occurs rate requires a 100 ms time constant, which corresponds to a
internally. SelectC2 for the desired low frequency breakpoint 4 μF capacitor (time constant = 25 ms per μF).
using an input resistance of 16.7 kΩ for the 1/ωRC calculation;
C2 = 1 μF for a cutoff at 10 Hz. Figure 11 and Figure 12 show
the input and output signal ranges for dual and single supply
configurations, respectively. The load resistor, RL, provides a
path to sink output sink current when an input signal is
disconnected.

CAV

C2
1µF
VIN ABSOLUTE +VS +VS
VIN 1 14
VALUE
0.1µF
NONPOLARIZED NC 2 AD536A 13 NC
–VS SQUARER/
3 DIVIDER 12 NC
20kΩ
4 11 NC
CAV
CURRENT COM
dB 5 10
MIRROR 0.1µF
VOUT BUF OUT RL
6 9
25kΩ
RL BUF IN
7 BUF 8 10kΩ
10kΩ IOUT
TO
00504-008

1kΩ

Figure 17. Single-Supply Connection

Rev. G | Page 12 of 15
Data Sheet AD536A
The primary disadvantage in using a large CAV to remove ripple The settling time, however, is increased by approximately a
is that the settling time for a step change in input level is factor of 3. Therefore, the values of CAV and C2 can be reduced
increased proportionately. Figure 19 illustrates that the to permit faster settling times while still providing substantial
relationship between CAV and 1% settling time is 115 ms for ripple reduction.
each microfarad of CAV. The settling time is twice as great for The two-pole postfilter uses an active filter stage to provide
decreasing signals as it is for increasing signals. The values in even greater ripple reduction without substantially increasing
Figure 19 are for decreasing signals. Settling time also increases the settling times over a circuit with a one-pole filter. The values
for low signal levels, as shown in Figure 20. of CAV, C2, and C3 can then be reduced to allow extremely fast
100 100
settling times for a constant amount of ripple. Caution should
be exercised in choosing the value of CAV, because the dc error

FOR 1% SETTLING TIME IN SECONDS

0.
01
% is dependent on this value and is independent of the postfilter.

MULTIPLY READING BY 0.115

ER
10 10
0.

R
For a more detailed explanation of these topics, refer to the RMS to
1%

O
REQUIRED CAV (µF)

R
ER

DC Conversion Application Guide, 2nd Edition.

R
1%

O
R
ER
R

1 1
O
10

VIN +VS
%

VIN ABSOLUTE
ER

1 VALUE 14 +VS
R

VALUES FOR CAV AND

O

AD536A
R

1% SETTLING TIME NC 2 13 NC
0.1 FOR STATED % OF READING 0.1 –VS SQUARER/
AVERAGING ERROR1 –VS 3 DIVIDER 12 NC
ACCURACY ± 20% DUE TO CAV
COMPONENT TOLERANCE 4 11 NC
CAV COM
0.01 0.01 CURRENT
00504-010

1 10 100 1k 10k 100k dB 5 10

MIRROR
INPUT FREQUENCY (Hz) BUF OUT RL
6 9
1PERCENT DC ERROR AND PERCENT RIPPLE (PEAK) 25kΩ IOUT
BUF IN
7 BUF 8
Figure 19. Error/Settling Time Graph for Use with the Standard RMS
Connection (See Figure 13 Through Figure 15)

+ Rx –
C2 24kΩ
– C31 +
SETTLING TIME RELATIVE TO 1V rms

10.0

00504-012
Vrms OUT
INPUT SETTLING TIME

1FOR SINGLE POLE, SHORT Rx, REMOVE C3.

7.5 Figure 21. Two-Pole Postfilter

5.0 10
DC ERROR OR RIPPLE (% of Reading)

PEAK-TO-PEAK RIPPLE
2.5 PEAK-TO-PEAK CAV = 1µF
RIPPLE (ONE POLE)
1.0 CAV = 1µF, C2 = 2.2µF
Rx = 0Ω
00504-011

1m 10m 100m 1 10 1 DC ERROR

rms INPUT LEVEL (V) CAV = 1µF
(ALL FILTERS)
Figure 20. Settling Time vs. Input Level
PEAK-TO-PEAK RIPPLE
A better method to reduce output ripple is the use of a postfilter. CAV = 1µF
C2 = C3 = 2.2µF (TWO-POLE)
Figure 21 shows a suggested circuit. If a single-pole filter is used
00504-013

(C3 removed, RX shorted) and C2 is approximately twice the value 0.1

10 100 1k 10k
of CAV, the ripple is reduced, as shown in Figure 22, and settling FREQUENCY (Hz)
time is increased. For example, with CAV = 1 μF and C2 = 2.2 μF, Figure 22. Performance Features of Various Filter Types
the ripple for a 60 Hz input is reduced from 10% of reading to (See Figure 13 to Figure 15 for Standard RMS Connection)
approximately 0.3% of reading.

Rev. G | Page 13 of 15
AD536A Data Sheet

OUTLINE DIMENSIONS
0.005 (0.13) MIN 0.080 (2.03) MAX

14 8
0.310 (7.87)
1 0.220 (5.59)
7
PIN 1
0.100 (2.54)
BSC 0.320 (8.13)
0.765 (19.43) MAX 0.290 (7.37)
0.200 (5.08) 0.060 (1.52)
MAX 0.015 (0.38)
0.150
(3.81)
0.200 (5.08) MIN
0.125 (3.18) SEATING 0.015 (0.38)
0.070 (1.78) 0.008 (0.20)
PLANE
0.023 (0.58) 0.030 (0.76)
0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 23. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-14)
Dimensions shown in inches and (millimeters)

0.049 (1.24)
0.075 (1.91) 0.200 (5.08)
0.041 (1.04) REF REF
0.100 (2.54) 0.100 (2.54) REF
0.064 (1.63) 0.095 (2.41) 0.015 (0.38)
0.075 (1.90) 19 3 MIN
20
18 4
0.358 (9.09) 0.011 (0.28) 1 0.028 (0.71)
0.358
0.342 (8.69) (9.09) 0.007 (0.18) 0.022 (0.56)
BOTTOM VIEW
SQ MAX R TYP
SQ 0.050 (1.27)
14 8 BSC
0.075 (1.91)
REF 13 9
SIDE VIEW 45° TYP
0.088 (2.24) 0.055 (1.40) 0.150 (3.81)
0.054 (1.37) 0.045 (1.14) BSC

12-05-2017-B
PKG-000045

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUI VALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 24. 20-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-20-1)
Dimensions shown in inches and (millimeters)

0.005 (0.13) MIN 0.098 (2.49) MAX

14 8
0.310 (7.87)
1
0.220 (5.59)
7

PIN 1
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.785 (19.94) MAX
0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX
0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
SEATING 0.015 (0.38)
0.023 (0.58) 0.070 (1.78) PLANE 15°
0.008 (0.20)
0.014 (0.36) 0.030 (0.76) 0°

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 25. 14-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-14)
Dimensions shown in inches and (millimeters)

Rev. G | Page 14 of 15
Data Sheet AD536A
REFERENCE PLANE

0.500 (12.70) 0.160 (4.06)

0.185 (4.70)
MIN 0.110 (2.79)
0.165 (4.19)
PIN 5 IS INTEGRAL
CONNECTION TO 6
HEADER 7
5
0.370 (9.40)
0.335 (8.51) 0.021 (0.53) 8
0.115 4
0.016 (0.40) (2.92) 0.045 (1.14)
9
0.335 (8.51) BSC 0.025 (0.65)
3
0.305 (7.75)
2
10 0.034 (0.86)
1
0.025 (0.64)
SIDE VIEW 0.230 (5.84) BOTTOM VIEW
BASE & SEATING PLANE BSC
0.040 (1.02) MAX 36° BSC

0.050 (1.27) MAX

DIMENSIONS PER JEDEC STANDARDS MO-006-AF

01-19-2015-A
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 26. 10-Pin Metal Header Package [TO-100]

(H-10)
Dimensions shown in inches and (millimeters)

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD536AJD 0°C to +70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536AJDZ 0°C to +70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536AKDZ 0°C to +70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536AJH 0°C to +70°C 10-Pin Metal Header Package [TO-100] H-10
AD536AJHZ 0°C to +70°C 10-Pin Metal Header Package [TO-100] H-10
AD536AKHZ 0°C to +70°C 10-Pin Metal Header Package [TO-100] H-10
AD536AJQ 0°C to +70°C 14-Lead Ceramic Dual In Line Package [CERDIP] Q-14
AD536ASD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536ASD/883B −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536ASE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1
AD536ASH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD536ASH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD536ASCHIPS −55°C to +125°C Die
5962-89805012A −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1
5962-8980501CA −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
5962-8980501IA −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
1
Z = RoHS Compliant Part.

©1976–2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00504-0-3/19(G)

Rev. G | Page 15 of 15