Chapter 3

Gate-Level Minimization

3-1

Outline
! Karnaugh Map Method
! NAND and NOR Implementations
! Other Two-Level Implementations
! Exclusive-OR Function
! Hardware Description Language

3-2

1
 Why Logic Minimization ?
! Minimize the number of gates used
! Reduce gate count = reduce cost
! Minimize total delay (critical path delay)
! Reduce delay = improve performance
! Satisfy design constrains
! Maximum fanins and fanouts, …
! Remove undesired circuit behavior
! Hazard, race, …
3-3

The Map Method

! The map method is also known as the
Karnaugh map or K-map
! Provide a straightforward procedure for
minimizing Boolean functions
! The simplified expressions are always in one
of the two standard forms:
! Sum of Products (SOP)
! Product of Sums (POS)

3-4

2
 Two-Variable Map (1/2)
! Two-variable function has four minterms
! Four squares in the map for those minterms
! The corresponding minterm of each square is
determined by the bit status shown outside

3-5

Two-Variable Map (2/2)

x + y = x(y+y’) + y(x+x’)
= xy (m3) + xy’ (m2) + x’y (m1)
= m1 + m2 + m3 3-6

3
 Three-Variable Map (1/2)
Gray Code

3-7

Three-Variable Map (2/2)

F ( x, y, z ) = ∑ (3,4,6,7) = yz + xz ' F ( x, y, z ) = ∑ ( 0, 2, 4,5,6 ) = z '+ xy '

xz’ yz z’ xy’
(all y covered) (all x covered) (x, y covered) (all z covered)
3-8

4
Four-Variable Map (1/2)
Gray Code

Gray
Code

3-9

Four-Variable Map (2/2)

F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’ = ∑ (0,1,2,6,8,9,10)
= B’D’ + B’C’ + A’CD’

A’CD’

B’D’ B’C

3-10

5
 Five-Variable Map (1/2)

* Maps with six or more variables need too many squares

and are impractical to use.
3-11

Five-Variable Map (2/2)

F(A,B,C,D,E) = (0,2,4,6,9,13,21,23,25,29,31)
= A’B’E’ + BD’E + ACE

BD’E
(same position) 3-12

6
 Prime Implicants
ab
! Implicant (cube) : cd 00 01 11 10 prime
implicant
A group of minterms
00 1 1 1 ac'
that form a cube
a'b'c'd'
ab'c'
! Prime implicant : 01 1 1
Combine maximum abc'
possible number of 11 1
adjacent squares in a'b'c
prime
the map implicant 10 1 1

a'cd'
prime implicant
3-13

Essential Prime Implicants

! If a minterm is covered by only one prime
implicant, that prime implicant is essential
and must be included
ab
cd
00 01 11 10

00 1 1
a'c'
Note: 1's in red color are covered by
01 1 1
only one prime implicant. All other
1's are covered by at least two prime
11 1 1 1 acd implicants

10 1

a'b'd'
3-14

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 Systematic Simplification
! Identify all prime implicants on the k-map
! Select all essential prime implicants
! Select a minimum subset of the remaining prime
implicants that cover all 1’s
! Ex: F ( A, B, C , D) = ∑ (0,2,3,5,7,8,9,10,11,13,15)

F = BD + B' D'
CD + AD
CD + AB'

+
 B' C + AD
 B' C + AB'

3-15

Product of Sums Simplification

! The complement of a function is represented in
the map by the squares not marked by 1’s
! Choose 1 " sum of products (minterms)
! Choose 0 " product of sums (Maxterms)

F ( A, B, C , D) = ∑ (0,1,2,5,8,9,10)
=B’D’+B’C’+A’C’D
=(A’+B’)(C’+D’)(B’+D)

3-16

8
 Two Gate Implementations
! Sometimes product-of-sums representations
may have smaller implementations
7 literals, 4 gates 6 literals, 4 gates

3-17

Don’t Care Conditions

! X = don't care (can be 0 or 1)
! Don’t cares can be included to form a larger cube,
but not necessary to be completely covered
! Ex: F ( w, x, y, z ) = ∑ (1,3,7,11,15) d ( w, x, y, z ) = ∑ (0,2,5)

larger cube
with don’t
cares

3-18

9
 Outline
! Karnaugh Map Method
! NAND and NOR Implementations
! Other Two-Level Implementations
! Exclusive-OR Function
! Hardware Description Language

3-19

NAND and NOR Implementation

! Digital circuits are frequently constructed with NAND
or NOR gates rather than with AND and OR gate
! NAND and NOR gates are much easier to fabricate
! NAND or NOR gates are both universal gates
! Any digital system can be implemented with only NAND
gates or NOR gates

3-20

10
 Alternative Graphic Symbols
! To facilitate the conversion to NAND or NOR logic, it
is convenient to define alternative graphic symbols
! “Bubble” means complement

obtained by DeMorgan’s theorem

3-21

Two-Level Implementation (NAND)

! It’s easy to implement a Boolean function with only
NAND gates if converted from a sum of products form
! Ex: F = AB+CD = ((AB)’(CD)’)’
1. add two bubbles
at the ends

3. all-NAND 2. convert to
circuit has NAND gate
produced using
DeMorgan’s
theorem
3-22

11
 Example 3-10
F ( x, y, z ) = ∑ (1,2,3,4,5,7)
Procedures:
1. Simplify the function in sum of
products
2. Draw NAND gates for the first
level
3. Draw a single AND-invert or
invert-OR in the second level
4. Add an inverter at
the first level for
the term with a
single literal

3-23

Two-Level Implementation (NOR)

! It’s easy to implement a Boolean function with only
NOR gates if converted from a product of sums form
! Ex: F=(A+B)(C+D)E
1. add two bubbles
at the ends

3. convert to
2. complement NOR gate
this input to add using
the third bubble DeMorgan’s
(if required) theorem
3-24

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 Multilevel NAND Circuits
! Procedures:
F=A(CD+B)+BC’
1. Convert all AND gates
to NAND gates with
AND-invert symbols
2. Convert all OR gates
to NAND gates with
invert-OR symbols
3. Check all bubbles and
insert an inverter for
the bubble that are
not compensated by
another bubble

3-25

Multilevel NOR Circuits

! For NOR gates, AND " invert-AND, OR " OR-invert
! Other procedures are the same as those for NAND

F=(AB’+A’B)(C+D’)

complemented

complemented
3-26

13
 Outline
! Karnaugh Map Method
! NAND and NOR Implementations
! Other Two-Level Implementations
! Exclusive-OR Function
! Hardware Description Language

3-27

Wired Logic
! Wired logic: direct wire connection that results in a
specific logic function
! Wired-AND
! Wired-OR
! Some NAND and NOR implementations (not all) have
such a property

3-28

14
 Nondegenerate Forms
! There are 16 possible combinations of two-level
forms
! Eight of these combinations will degenerate to a single
operation
! The other eight nondegenerate forms produce
an implementation in SOP or POS
The two forms
AND-OR OR-AND
at the same line
NAND-NAND NOR-NOR
NOR-OR NAND-AND
are dual to
OR-NAND each other AND-NOR
3-29

AND-OR-INVERT Implementation
! NAND-AND and AND-NOR are equivalent and both
perform the AND-OR-INVERT (AOI ) function
! Require sum-of-products form in nature
! When starting from product-of-sums form, complement it
using DeMorgan’s theorem to obtain sum-of-products form
! Ex: F = (AB + CD + E)’

3-30

15
 OR-AND-INVERT Implementation
! OR-NAND and NOR-OR are equivalent and both
perform the OR-AND-INVERT (OAI ) function
! Require product-of-sums form in nature
! When starting from sum-of-products form, complement it
using DeMorgan’s theorem to obtain product-of-sums form
! Ex: F = [(A+B)(C+D)E]’

3-31

Implement with Two-Level Forms

3-32

16
 Example 3-11
choose 0

! F = x’y’z’ + xyz’
(choose 1 in K-map)
= (x’y + xy’ + z)’
(choose 0 in K-map)

choose 1

3-33

Outline
! Karnaugh Map Method
! NAND and NOR Implementations
! Other Two-Level Implementations
! Exclusive-OR Function
! Hardware Description Language

3-34

17
 Exclusive-OR (XOR) Function
! XOR is often denoted by the symbol ⊕
! Logic operation of XOR
! X ⊕ Y = XY’ + X’Y
! Equal to 1 if only x is equal to 1 or if only y is equal to 1,
but not when both are equal to 1
! It’s complement, exclusive-NOR (XNOR), is often
denoted by the symbol ⊙
! Logic operation
! X ⊙ Y = XY + X’Y’
! It is equal to 1 if both x and y are equal to 1 or if both are
equal to 0
! Seldom used in general Boolean functions
! Particularly useful in arithmetic operations and error detection
and correction circuits
3-35

Exclusive-OR Implementations

3-36

18
 Odd Function
! The multiple-variable
XOR operation is defined
as an odd function
! TRUE when no. of “1” in
inputs is odd
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1 3-37

Even Function
! The multiple-variable
XNOR operation is defined
as an even function
! TRUE when no. of “1” in
inputs is even
A B C F
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0 3-38

19
 Four-Variable XOR Function

3-39

Parity Generation and Checking

! An extra parity bit is often added and
checked at the receiving end for error
! The circuit that generates the parity bit in the
transmitter is called a parity generator
! The circuit that checks the parity in the
receiver is called a parity checker
! Exclusive-OR functions are very useful to
construct such circuits

3-40

20
 Parity Generator
! For even parity:
! The total number of “1”
(including P) is even
! The number of “1” at
inputs is odd
! Generated with an XOR
gate (odd function)
! P = x ⊕ y ⊕ z (for 3-bit
message)
! Similarly, odd parity can
be generated with an
XNOR gate
3-41

Parity Checker
! For even parity, the total
number of “1” in the
message is even
! An error occurs when the
received number of “1” is odd
! An XOR gate (odd function)
can detect such an error
! Has n+1 inputs

3-42

21
 Outline
! Karnaugh Map Method
! NAND and NOR Implementations
! Other Two-Level Implementations
! Exclusive-OR Function
! Hardware Description Language

3-43

Hardware Description Language

! Have high-level language constructs to describe the
functionality and connectivity of the circuit
! Can describe a design at some levels of abstraction
! Behavioral, RTL, Gate-level, Switch
! Can describe functionality as well as timing
! Can model the concurrent actions in real hardware
! Can be used to document the complete system
design tasks
! testing, simulation … related activities
! Comprehensive and easy to learn
! Two popular languages: Verilog & VHDL
! Will be taught in another course
3-44

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 Why Use an HDL ?
! Hard to design directly for complex systems
! Formal description using HDL
! Verify the specification through simulation or verification
! Easy to change
! Enable automatic synthesis
! Allow architectural tradeoffs with short turnaround
! Reduce time for design capture
! Encourage focus on functionality
! Shorten the design verification loop
*HDL = Hardware Description Language
3-45

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