ECE 223 Digital Circuits and Systems

Logic Minimization
M. Sachdev,
Dept. of Electrical & Computer Engineering University of Waterloo

Karnaugh Maps - Introduction

2-Level Logic implementation using SOP or POS is not the most economical in terms of #gates & #inputs A Karnaugh map is a graphical representation of a truth table
The map contains one cell for each possible minterm Adjacent cells differ in only one literal; i.e. x (or x) Function is plotted by placing 1 in cells corresponding to minterms Put 0 in rest of the cells
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K Map with 2 Variables

F =f(x,y)
y x 0 0 1 1 y 0 1 0 1 F m0 m1 m2 m3 1 m2 m3 0 m0 m1 x 0 1

Example, F1 = xy

y x 0 1
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K Map with 3 Variables

3 Variable, F = f(x,y,z); Given F2 = (2,3,4,5)
Represent it on the K map minimize the function
yz x 0 1 x 0 1 00 01 11 10 yz x 0 1 00 m0 m4 01 m1 m5 11 m3 m7 10 m2 m6

yz 00 01 11 xyz xyz 10 xyz xyz

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xyz xyz xyz xyz

K Map with 3 Variables

3 Variable, F = f(x,y,z); Given F3 = (3,4,6,7)
Minimize the function using K map Function minimization Find maximum size groups that cover all 1s in the map
(Comment a group should not be a subset of other group) 4 cell group 2 literals can be removed 2 cell group 1 literal can be removed

Guidelines for logic synthesis (SOP)

Fewer groups fewer AND gates, and fewer inputs to the OR gate Fewer literals (larger group) fewer inputs to an AND gate

Synthesis Objective: Fewest # of gates and # of inputs

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K Map with 4 Variables

4 Variable, F = f(w,x,y,z) Given, F4 = (3,4,5,7,9,13,14,15)
represent it on the map Minimize the logic

yz wx 00 01 11 10
yz wx 00 01 11 10 00 0 0 1 0 01 0 1 1 1 11 1 1 1 0 10 0 0 1 0

00 m0 m4 m12 m8

01 m1 m5 m13 m9

11 m3 m7 m15 m11

10 m2 m6 m14 m10

Clues
Make all possible groups Do we need the group of 4? F4 = wxy +wxy +wyz +wyz

Implicants & Prime Implicants,

Implicant: A group of one or more k map cell Prime implicant: an implicant that is not a subset of another implicant Essential Prime Implicant: a prime implicant that covers at least one cell not covered by another prime implicant Example, F5 (w,x,y,z) = (0,1,2,5,6,7,9,13,14)
yz wx 00 01 11 10 00 1 0 0 0 01 1 1 1 1 11 0 1 0 0 10 1 1 1 0
wx 00 01 11 10 yz 00 1 0 0 0 01 1 1 1 1 11 0 1 0 0 10 1 1 1 0

Product of Sum Expression

Let F be the function F = (all minterms not in F) F = (all minterms not in F) (de Morgans theorem) Therefore, one cam obtain POS expression by
1. 2.

Group all 0s on K map Use de Morgans theorem to obtain POS expression

F6 = xz +xy + wyz (SOP) = (w +x)(y +z)(x +z) (POS) One is often simpler than the other Check both
yz wx 00 01 11 10 00 1 0 0 1 01 1 1 0 1 11 0 0 0 0 10 1 0 0 1
wx 00 01 11 10 yz 00 1 0 0 1 01 1 1 0 1 11 0 0 0 0 10 1 0 0 1
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Plotting Product of Sum Expression

Given, F7 = (w +x)(x +y +z)(y +z)
F7 = [(w +x)(x +y +z)(y +z)] = (w +x) +(x +y +z) +(y +z) = wx +xyz +yz
wx 00 01 11 10 yz 00 0 0 0 0 01 0 1 1 1 11 0 1 1 1 10 0 1 1 0

F7 is plotted by putting 0s in appropriate cells Can F7 be simplified further?

F7 = wx +xz +yz F7 = (w +x)(x +z)(y +z)

Dont care Conditions

Some time, not all values of a function are defined
Some inputs conditions will never occur We dont care what the output is for that input condition

In these cases, we can choose the output to be wither 0 or 1, whichever simplifies the circuit Example A circuit to produce output 1 if a BCD digit is multiple of 3
BCD Four inputs (wxyz) 0 (0000) Values of wxyz 10 (1010) 9 (1001) 15 (1111) dont care

The function F8 = (3,6,9) +d(10,11,12,13,14,15)

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Dont Care - Plotting

Dont care are plotted as X in the K map SOP expression Treat X as 1 if it allows a larger group POS expression Treat x as 0 if it allows a larger group F8_1 = wz +xyz +xyz (SOP) F8_2 = xz +wy +xz {F = (all minterms not in F)} F8_2 = (x +z)(w +y)(x +z) de Morgans theorem Is F8_1 = F8_2?? yz yz
wx 00 01 11 10 00 0 0 X 0 01 0 0 X 1 11 1 0 X X 10 0 1 X X

wx 00 01 11 10

00 0 0 X 0

01 0 0 X 1

11 1 0 X X

10 0 1 X X 11

Simplest 2-Level Expression

Example, F(w,x,y,z) = (0,1,2,5,6,7,9,14) +d(13)
Determine essential and prime implicants

yz wx 00 01 11 10 00 1 0 0 0 01 1 1 X 1 11 0 1 0 0 10 1 1 1 0 wx

yz 00 00 01 11 10 1 0 0 0 01 1 1 X 1 11 0 1 0 0 10 1 1 1 0

Essential prime implicants

Prime implicants
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Simplest 2-Level Expression

Example, F(w,x,y,z) = (0,1,2,5,6,7,9,14) +d(13)
Determine essential and prime implicants
0 yz (1,5,9,13) xyz (6,14) wxy (0,1) wxz (0,2) wxz (5,7) wxy (6,7) wyz (2,6) 1 2 5 6 7 9 14 A B C D E

All minterms must be covered

i.e., essential prime implicants must be included Different choices for prime implicants B +C; or B +D; or A +C +E; or A +D +E
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Tabulation (Quine-McCluskey) Method

The map method of simplification is convenient if # of variables 4
Tabulation method is preferred for function with large # of variables

For F(w,x,y,z) consider adjacent minterms

let a = m4 +m5 or Similarly, b =m12 +m13 wxy +wxy = xy = -10= wxyz + wxyz = wxy = 0100 + 0101 = 010= wxyz + wxyz = wxy = 110-

Let c = a +b = m4 +m5 +m12 +m13 Adjacent terms differ by a single bit in their representation Tabulation method consists of grouping of minterms and systematically checking for single bit differences
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Tabulation (Quine-McCluskey) Method

Example, F(w,x,y,z) = (0,3,4,6,7,8,10,11,15) +d(5,9)
Place minterms in different Sections according to # of 1s in their binary representation Each member of each Section is compared with each member of Sections below; all reduction are recorded in next column Mark terms that combine All unmarked terms are prime implicants

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Tabulation Method - Example

Example

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NAND & NOR Implementation

In digital logic families NAND & NOR implementations are cheaper compared to AND & OR implementations
Hence, NAND & NOR are preferred

NAND and NOR are universal gates

Can mimic any logic gate Example, NAND gate can implement: NOT short inputs AND {(xy)} OR (xy) = x +y

Similarly for NOR gate, one can show its universality

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NAND 2-level Implementation

Can implement any arbitrary logic Example, F = AB + CD

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NAND 2-level Implementation

Given, F9 (x,y,z) = (1,2,3,4,5,7)
Minimize the function, and implement it with NAND gates

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NAND 2-level Implementation Procedure

1. 2. 3. 4.

Simplify the function and express it in SOP form Draw a NAND gate for each product term Draw a single gate using AND-invert or invert-OR symbol for the sum term A term with single literal, complement if needed Multi-level NAND Circuits Convert all AND gates to NAND gates Convert all OR gates to NAND gates with invert-OR symbols Balance all bubbles, insert an inverter if needed
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1. 2. 3.

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NOR Implementation
NOR gate is a dual of NAND
Same rules and procedures

Example, F = (A +B)(C +D)E

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Wired Logic
Two logic gate outputs are not shorted together
May create logical conflicts Logic is not defined

In some technologies, it is possible to short O/Ps of some logic gates (wired logic)
F1 = (AB)(CD) = (AB + CD) (wired AND) F2 = (A +B) + (C +D) = [A +B)(C +D)] (wired OR)

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Exclusive-OR Function
XOR gate is expensive to implement in silicon
XOR = xy +xy XNOR = (xy +xy) = xy +xy

But they are useful in

Parity checking Arithmetic circuits (adders, subtractors)

x 0 0 1 1

y 0 1 0 1

XOR 0 1 1 0

XNOR 1 0 0 1
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Exclusive-OR Function
XOR gate properties
Commutative Associative

Odd and Even Functions

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Exclusive-OR Function
4 Variable XOR

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Parity Generation and Checking

Parity checking is useful for detecting and correcting errors when transmitting binary data
We can always append a parity bit to the end of the data bits (e.g. 32) so that the number of 1s in the packet is always even or odd

If we lose a bit in transmission, we can use the parity bit to tell us there has been a problem

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Book Sections Logic Minimization

Material is covered in Sections 3.1 3.8

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