tm TE

CH T62M0001A

Digital Sound Processor

T62M0001A With 64K SRAM
Features Description
l Low Noise (-90dBV typical) T62M0001 is a digital echo/surround processor
l Low Distortion (0.17% typical) IC utilizing CMOS technology. Analog signal
l Built –in 64 K SRAM to T62M0001 is digitized by a built-in A/D
l Sleep Mode Function converter and then stored in the internal
l Two Control Modes Selection: memory. After an adjustable delay time, data in
Easy Mode Using Parallel Data the memory is read and converted back to
u-COM Mode Using Serial Data analog signal via the other D/A converter. With
l Auto-Mute Function the built-in 64K SRAM, T62M0001 can create
l Built-in Automatic Reset Circuit very high performance echo/surround sound
l Pin Compatible with M65831 effect and meet the application of A/V system
such as CD player VCD,DVD ….etc.

Part Number Examples

Part NO. Pkg Description
T62M0001A-D 24-SOP 24-SOP
T62M0001A-K 24-DIP 600mil-24-DIP

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to change products or specifications without notice. Revision:A
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CH T62M0001A

Pin Configuration

c
VDD 1 24 VCC

XIN 2 23 LPF1 IN

XOUT 3 22 LPF1 OUT

D1/REQ 4 21 OP1 OUT

D2/SCK 5 20 OP1 IN

D3/DATA 6 19 REF

D4/IDSW 7 18 CC1

TEST 8 17 CC2

EASY/u-COM 9 16 OP2 IN

SLEEP 10 15 OP2 OUT

D-GND 11 14 LPF2 IN

A-GND 12 13 LPF2 OUT

24 PINS DIP/SOP

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CH T62M0001A

Pin Description
Symbol I/O Function Pin no.

VDD P Digital supply voltage 1

XIN I Oscillator input 2

XOUT O Oscillator output 3

Easy mode : inputs D1 data

D1/REQ I 4
u-COM mode :inputs request data
Easy mode : inputs D2 data
D2/SCK I 5
u-COM mode : inputs shift clock
Easy mode : inputs D3 data
D3/DATA I 6
u-COM mode : inputs serial data
Easy mode : inputs D4 data
D4/IDSW I 7
u-COM mode : controls ID code
TEST I L = normal mode 8

H = easy mode
EASY/u-COM I 9
L = u-COM mode
SLEEP I H = sleep mode 10
L = normal mode
D-GND G Digital ground 11

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CH T62M0001A

Symbol I/O Function Pin no.

A-GND G Analog ground 12

LPF2 OUT O Low pass filter 2 output 13

LPF2 IN I Low pass filter 2 input 14

OP2 OUT O Integrator 2 output 15

OP2 IN I Integrator 2 input 16

CC2 - Current control 2 17

CC1 - Current control 1 18

REF - Analog reference voltage ( = 1/2 VCC ) 19

OP1 IN I Integrator 1 input 20

OP1 OUT I Integrator 1 output 21

LPF1 OUT - Low pass filter 1 output 22

LPF1 IN O Low pass filter 1 input 23

VCC P Analog supply voltage 24

P : supply voltage G : ground

I : input pin O : output pin

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CH T62M0001A

Function description
1.Easy mode (parallel data input)
When the pin EASY/ µ − COM = “High”, then in the easy mode.

D4 D3 D2 D1 fs Td

L L L L Fck/3 12.3

L L L H Fck/3 24.6

L L H L Fck/3 36.9
L L H H Fck/3 49.2

L H L L Fck/3 61.4

L H L H Fck/3 73.7

L H H L Fck/3 86.0

L H H H Fck/3 98.3

H L L L Fck/6 110.6
H L L H Fck/6 122.9

H L H L Fck/6 135.2

H L H H Fck/6 147.5

H H L L Fck/6 159.7

H H L H Fck/6 172.0
H H H L Fck/6 184.3

H H H H Fck/6 196.6

Note : f s : sampling frequency (Hz) ; Fck : oscillator frequency(example Fck=2MHz)

Td : delay time (msec)

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CH T62M0001A
2.u-COM mode (serial data input)

When the pin EASY/ u − COM = “Low” , then in the u-COM mode.
The timing is shown as the diagram below:

H Delay time H ID code

= Sleep mode = Mute

This timing chart shows that delay time is set by serial data from u-COM.
DATA signal is latched at the falling edge of SCK signal, the last ten datas are set at the rising edge
of REQ signal when ID codes are satisfied.

ID1, ID3 = Low

ID2 = High
ID4 = Equal to IDSW

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CH T62M0001A

REQ, SCK, DATA input timing

Symbol Parameter Limits Unit

Min. Typ. Max.
t1 SCK pulse width 250 - - ns

ds SCK pulse duty - 50 - %

t2 DATA setup time 100 t1/2 - ns

t3 DATA hold time 100 t1/2 - ns

t4 REQ hold time 100 - - ns

t5 REQ pulse width 250 - - ns

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CH T62M0001A
3.Mute
(1) Easy mode
Automatic mute upon changing delay time, cancelling SLEEP mode and power on.
(2) u-COM
MUTE=H : mute.
MUTE=L : automatic mute.
Automatic mute :
Delay signal before change mode Delay signal after change mode

(a) Upon changing delay time

Delay signal

(b) Upon cancel sleep mode

Delay signal

Power on
(c) Upon power on

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CH T62M0001A
4.SLEEP mode
SLEEP data is :
H=clock and RAM stop to reduce circuit current (SLEEP mode)
L=normal operation

5.System reset
Automatically reset power-on. The reset time is about 120 m second.
Delay time is set at 147.5 m second.

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CH T62M0001A

Absolute maximum rating (Ta=25ºC,unless otherwise noted)

symbol paramatic ratings unit

Vcc Supply voltage 6 V

Icc Circuit current 100 mA

Pd Power dissipation 1.7 W

Topr Operating temperature -20~75 ºC

Tstg Storage temperature -25~125 ºC

Recommended operating conditions

rating
symbol parameter unit
Min. Typ. Max.
VCC Supply voltage 4.5 5 5.5 V

VDD Supply voltage 4.5 5 5.5 V

VCC-VDD Difference voltage -0.3 0 0.3 V

fck Clock frequency 1 2 3 MHz

VIH “H” input voltage 0.7VDD - - V

VIL “L” input voltage - - 0.3VDD V

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CH T62M0001A

Electrical characteristics
(Vcc=5.0V,fin=1KHz,Vi=100mVrms,fck=2MHz,Ta=25ºC, unless otherwise noted)

symbol Parameter Test condition Min. Typ. Max. unit

Icc Circit current No signal - 13 20 mA

Gv Voltage gain RL=47KΩ - -0.5 2.5 dB
Circit current
Iccs Sleep Mode - 7 10 mA
(Sleep Mode)

Vomax Max. output voltage THD=10% 1.3 1.6 - Vrms

30KHz fs=666KHz - 0.17 0.6 %

THD Output distorton
L.P.F. fs=333KHz - 0.4 1.0 %
Upon changing delay time 508 528 548 ms
TMUTE Mute time
Upon canceling sleep mode 508 528 548 ms

No Output noise voltage DIN-AUDIO(fs=666KHz) - -90 -80 dBV

DC electrical characteristics
limits
symbol parameter unit
Min. Typ. Max.

Vcc Supply voltage 4.5 5 5.5 V

Icc Circuit current - 13 20 mA

VIH “H” input voltage 0.7VDD - - V

VIL “L” input voltage - - 0.3VDD V

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CH T62M0001A

Application circuit
VCC

100UF/10v C1 EASY MODE

C2
0.1UF U1

C3 Y1 1 24 C4 4700PF IN
100PF VDD VCC C5
2 23 R1 R2
C6 XIN LPF1_IN C7 10K 20K 1
2MHZ 3 22 560PF 1UF
100PF XOUT LPF1_OUT R3
4 21 18K
D1 OP1_OUT C8 C9
SETING 5 20 0.1UF
D2 OP1_IN 1UF
DELAY 6 19 47UF/10V
TIMES D3 REF C10 R4
7 18 20K
D4 CC1 C11
VCC 8 17 0.33UF
TEST CC2 C12
9 16 0.33UF R5
SW1 EASY/£g-COM OP2_IN C13 30K C14
1 2 10 15
SLEEP OP2_OUT 0.1UF 0.01UF
11 14
DGND LPF2_IN C15
12 13
AGND LPF2_OUT 560PF R6 R7 R8
10K 18K 3K
T62M0001A C16

4700PF
DGND R9
C17 20K
AGND
0.01UF C18
R10
1UF
1

OUT 2.7K

VCC

100UF/10v C1 u-COM MODE

C2
0.1UF U1

C3 Y1 1 24 C4 4700PF IN
100PF VDD VCC C5
2 23 R1 R2
C6 XIN LPF1_IN C7 10K 20K 1
2MHZ 3 22 560PF 1UF
100PF XOUT LPF1_OUT R3
4 21 18K
D1 OP1_OUT C8 C9
5 20 0.1UF
D2 OP1_IN 1UF
u-COM
6 19 47UF/10V
D3 REF C10 R4
7 18 20K
D4 CC1 C11
VCC 8 17 0.33UF
TEST CC2 C12
9 16 0.33UF R5
SW1 EASY/£g-COM OP2_IN C13 30K C14
1 2 10 15
SLEEP OP2_OUT 0.1UF 0.01UF
11 14
DGND LPF2_IN C15
12 13
AGND LPF2_OUT 560PF R6 R7 R8
10K 18K 3K
T62M0001A C16

4700PF
DGND R9
C17 20K
AGND
0.01UF C18
R10
1UF
1
OUT 2.7K

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CH T62M0001A

IC package
T62M0001A(24-DIP)

A1

B2
B
B3 A1
B1
D2
C1 C D1

Dimension in mm Dimension in inch

Symbol
min. typ. max min. typ. max.
A - 32.26 - - 1.270 -
A1 13.21 - 14.22 0.520 - 0.560
B - - 5.08 - - 0.20
B1 3.18 - - 0.125 - -
B2 - - 4.57 - - 0.180
B3 0.51 - - 0.020 - -
C 2.24 2.54 2.84 0.088 0.100 0.112
C1 4.06 4.57 5.08 0.16 0.18 0.20
D 14.99 - 15.49 0.59 - 0.61
D1 - 0~15° - - 0~15° -
D2 - 0.25 - - 0.01 -

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CH T62M0001A

T62M0001A(24-SOP)
D
24 13
.....

E E1

A
.....
1 12 C

S C A L E :"A "

..... A2 A
Z e b A1

L'
L1'

Symbol Dimension in mm Dimension in inch

min. typ. max min. typ. max.
A - - 2.4 - - 0.0945
A1 0.05 - - 0.002 - -
A2 - 2.0 - - 0.0787 -
b 0.35 0.4 0.5 0.0138 0.0157 0.0197
C 0.13 0.15 0.2 0.0051 0.0059 0.0079
D 14.8 15.0 15.2 0.5827 0.5906 0.5984
E 8.2 8.4 8.6 0.3228 0.3307 0.3386
e - 1.27 - - 0.05 -
E1 11.63 11.93 12.23 0.4579 0.4697 0.4815
L 0.3 0.5 0.7 0.0118 0.0197 0.0276
L1 - 1.7650 - - 0.0448 -
Y - - 0.15 - - 0.0059
0° - 10° 0° - 10°

TM Technology Inc. reserves the right P. 14 Publication Date: JUN. 2002

to change products or specifications without notice. Revision:A