UNIT I
1 Explain with suitable examples the difference between computer architecture and 5
computer organization.
2 Prove that Memory Access Time (MAT) is less than that of the memory cycle time 5
(MCT) with suitable example.
3 Explain the general organization of CPU. State the function of following CPU registers 10
:—(i) MAR (Memory Address Register) (ii) MDR (Memory Data Register) (iii) IR
(Instruction Register) (iv) PC (Program Counter) (v) SP (Stack Pointer).
4 Vonneuman model in detail. 10
5 Explain different bus arbitration schemes with suitable diagrams 10
6 PCI Bus 05
7 Describe in detail the organization of a typical CPU. It should include program control 10
unit, data processing unit and appropriate registers
8 Explain Instruction cycle with interrupt execution in detail. 10
9 Explain Instruction cycle with different stages. 10
UNIT II
1 Explain and solve the following problem using by non-restoring division algorithm 10
Hence divide (10)10 with (3)10
2 Explain with suitable example booth s Algorithm for signed multiplication. 5
3 Explain IEEE format for floating point number representation. 10
4 Perform division of the following numbers using restoring division :–Dividend = 17; 10
Divisor = 03.
5 Multiply (– 7) with (3) by using Booth's multiplication. 10
6 With neat flow chart, explain the procedure for division of floating point numbers 10
carried out in a computer.
7 Explain multiplication of signed numbers –13 *-5 using Booth's algorithm. 10
8 Explain Booth-Algorithm and implement for the number (-7) and (+13). 10
9 Explain Non-Restoring division algorithm for performing 19/4. 10
10 Explain with flowchart floating-point addition/subtraction algorithm. 10
11 Explain and solve the following problem using by restoring division algorithm? 10 10
Hence divide (163)10 with (11)10.
UNIT III
1 Define the term "softwired" and "hardwired". Explain with diagram the softwired i.e. 10
micro programmed and hardwired control unit organization.
2 What is "Micro program"? Write a Micro program using RTL(Register transfer 10
language) notation for the following arithmetic operation
3 Explain in detail characteristics of RISC and CISC. 10
4 Explain microinstructions, micro operations, micro-program in detail. 10
5 Explain Micro instruction sequencing and execution. 10
6 Distinguish between :— (i) Hardwire control and microprogrammed control (ii) 10
Horizontal and vertical microprogrammed control unit.
7 Describe in detail the organization of a typical CPU. It should include program control 10
unit, data processing unit and appropriate registers.
8 What do you mean by Fetch cycle, instruction cycle, machine cycle and interrupt 10
acknowledgement cycle. Explain in brief.
9 What is microoperation ? Give suitable examples of some four types of 10
microoperations.
10 Explain with an example, how effective addresses calculated in different types of 10
addressing modes.
11 Explain any two methods of hardwired control unit. 10
12 Explain different Hardwired control unit design techniques. 10
13 Explain different Instruction formats with suitable example. 10
14 Define the following terms microinstruction, microoperation, microprogram. 10
15 (b) What is "Micro program" ? Write a Micro program using RTL. (Register Transfer 10
language) notation for the following arithmetic operation.
(i) SUB RIA2 i.e RI RI - R2
(ii) MUL RI,R2 i.e RI RI*R2
16 Explain nano-programming. 10
17 Write and explain the microprogram for LOAD AC. 10
UNIT IV
1 A two level memory (Ml , M2) has the access times tAl = 10-8 s and 10 tA2 = 10- 3 s. What 10
must be the hit ratio H in order for the access efficiency to be atleast 65 % of it's maximum
possible value?
2 A block set associative cache consists of a total of 128 cache block 10 with two blocks/set. 10
The main memory containing 4 K blocks with 16 words/ block. Draw a figure explaining
the mapping and show the partitions of an address into TAG, SET, and WORD bit.
What is cache coherency problem?
3 Explain with state diagram, MESI (Mutual Exclusive Shared Invalid) protocol. 10
4 What is memory interleaving? Discuss various memory leaving techniques. 10
5 Main memory has 3 pages and the processor requires pages from virtual memory in the 10
following order.
2 3 2 1 5 2 4 5 3 2 5 2 show the implementation of FIFO, LRU, LFU.
6 What is cache memory? explain cache coherence strategies in single and multiprocessor 10
systems .
7 Explain memory characteristics 10
8 Explain page replacement algorithm. Find out page fault for following string using LRU 10
method. Consider page frame size = 3
70120304230321201701
9 What is Virtual Memory ? Explain how paging is useful in implementing virtual memory. 10
10 A block set-associative cache consists of 64 blocks divided in 4 block sets. 10 The main 10
memory contains 4096 blocks, each consisting of 128 words of 16 bit length :—
How many bits are there in main memory ?
How many bits are there in each of the TAG, SET and WORD fields ?
11 In two level memory, tA1 = 10-7s and tA2 = 10-2S. What must the hit ratio it be in order for 10
the access efficiency to be at least 90% of its maximum possible value ?
12 What is locality at reference ? Explain the different types of locality. 10
13 Explain the performance characteristic of two level memory with respect to cost, access 10
time and performance.
14 Explain the different mapping techniques of cache memory. 10
15 Explain difference between SRAM and DRAM 05
16 Explain different Mapping techniques of Cache Memory 10
17 Compare and contrast DMA, programmed I/O and Interrupt driven I/O. 10
18 What is virtual memory? Explain how virtual address is mapped to actual physical address 10
19 What is cache coherency ? Explain different protocols to solve cache coherency 10
20 What is virtual memory ? Explain Role of paging and segmentation in virtual memory. 10
21 Characteristics of two level memory. 10
22 Explain types of memories based on the hierarchy of speed and size. 10
23 Explain Interleaved Memory with low-order and high-order 'interleaving. 10
24 Short note: Paging and Segmentation. Page Replacement Algorithm 10
25 Draw Direct and set associative mapping for cache memory with advantages and 10
disadvantages.
26 What is Virtual memory ? Explain how paging is useful in implementing virtual memory ? 10
27 How many 128 bytes RAM chips are required to provide a memory of 2048 10 bytes ? 10
Show details of connections, clearly indicating address, data and decoder configuration.
28 Short Note: Spatial locality of reference, Temporal locality of reference, Cache block. 10
29 What is Cache coherence ? Explain Cache coherence strategies in single 10 processor and 10
multiprocessor systems.
30 Explain page replacement algorithm Find out page fault for following string using LRU 10
method.
6 0 12 0 30 4 2 30 32 1 20 15 (Consider page frame size = 3).
31 A 32- bit computer has a 32 bit memory address. It has 8 KB of cache memory. The 10
computer follows four-way set associative mapping. Each line size is 16 bytes. Show the
memory address format and cache memory organization.
UNIT V
1 Explain I/O processor and I/O channels with diagram. 10
2 Define "(Input/Output) I/O Module". State the difference between programmable and non- 10
programmable device. Explain in brief the structure of 8089 I/0 processor.
3 Short notes on : DMA 10
4 Compare & contrast DMA, Programmed I/O . & interrupt driven I/O. 10
5 Short Note: Interrupt driven I/O, I/O:processor and I/O channels 10
6 What do you mean by initialization of DMA controller 10
7 How DMA controller works? Explain with suitable block diagram. 10
8 Short Note: i)DMA (ii) Programmed I/O (iii) Interrupt Driven I/O. 10
UNIT VI
1 What is the difference between pipelining & parallelism ? Explain the Flynn's Classification in 10
detail.
2 What is pipelining ? Explain with suitable example the difference 10 between serial instruction 10
execution and pipelined instruction execution. Also prove that why pipelined instruction
execution is faster as compared to serial instruction execution.
3 What is pipelining? Explain six stage instruction pipeline with suitable diagram 10
4 explain Flynn's classifications with suitable diagrams . also comment on design issues of 10
pipeline architecture . (
5 Formulate a four segment instruction pipeline for a computer. Specify the operation to be 10
performed in each segment.
6 What is the difference between pipelining and parallelism? Show that k-stage pipelined 10
processor has k-times speed up as compared to non-pipelined system
7 MIMD and SIMD 10
