DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
SEMESTER: IV
SUBJECT CODE: CS404/IO404
SUBJECT NAME: COMPUTER ORGANIZATION AND ARCHITECURE
Question Bank
UNIT-3
1. Elaborate serial and parallel data transfer with the help of an example.
2. How the data is transferred through synchronous and asynchronous modes? Discuss by giving
the example of each modes.
3. Discuss the working of Direct Memory Access (DMA) in terms of IO organization of the
computer organization and it’s various methods.
4. How does IO Processor Works? Explain in detail with the help of a suitable diagram.
5. Compare the working of Direct Memory Access (DMA) and IO Processor in detail.
6. Explain I/O interface. Why I/O interface is required?
7. Explain the following I/O interfaces –
i. PCI bus interface
ii. SCSI bus interface
iii. USB bus interface
8. Explain procedures of strobe pulse and handshaking in Asynchronous transfer.
9. Explain different modes of data transfer between the central computer and IO devices.
10. What is program controlled I/O? Explain in detail with block diagram.
11. What do you understand by interrupt driven I/O? Explain daisy chaining priority method of
data transfer.
12. Discuss hardware interrupt and software interrupt in detail.
13. What is direct memory access? Explain the role of DMA controller in data transfer between I/O
devices and memory with cycle stealing and burst mode.
UNIT-4
1. What is Memory Organization? Discuss different types of memory organization.
2. Comment on “Methods of Improving Cache Performance”.
3. Draw and explain memory hierarchy in computer organization? What are the advantages of
Cache memory?
4. What is mapping? Explain different types of cache mapping.
5. With a diagram, explain address translation in virtual memory.
6. Discuss the memory management hardware. How memory is managed?
7. Compare and contrast Main Memory and Secondary Memory of the Computer system.
8. Discuss various cache mapping schemes in detail.
9. A CPU has 32 bit memory address and 256 KB cache memory. The Cache is organized as 4-
way set associative cache with cache block size of 16 bytes:
a) What is the number of sets in the cache?
b) What is the size of the tag field per cache block?
c) How many address bits are required to find the byte offset within a cache block?
d) What is the total amount of extra memory (in bytes) required for the tag bits?
10. A virtual memory system has 6 K words of address space and 3K words of memory space.
Page references are made by CPU in the following sequence:
3,2,0,3,4,1,2,2,0
Find out the pages that are available at the end if the replacement algorithm used is (a) LRU
(b) FIFO. Assume the page and block size of 1 K words.
11. What is cache memory? Explain the following:
i. Hit Ratio
ii. Average Access Time
12. A cache memory needs an access time of 30 ns and main memory 150 ns, what is the average
access time of CPU (assume hit ratio = 80%)?
13. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block
size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB.
Determine the number of bits for Tag field.
14. Explain write through and write back policy for cache coherence.
15. Consider a fully associative cache with 8 cache blocks and the following sequence of
memory block requests:
4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7
(i) If LRU replacement policy is used, which cache block will have memory block 7?
(ii) Calculate the hit ratio using First In First Out (FIFO) replacement policy
16. What is paging? Describe different page replacement algorithms.
17. Explain virtual memory organization.
18. Write a short note on improving cache performance methods in details
UNIT-5
1. Can you elaborate on the concept of multiprocessing within computer architecture, and provide
a comprehensive discussion on the various types of data transfer methods employed in
multiprocessing systems?
2. What are the key characteristics that define multiprocessor systems, and how does their
structure facilitate parallel processing and enhance overall computational performance?
3. What is the layout of pipelined instruction in computer architecture? Explain.
4. Explain the structure of general purpose multiprocessors with diagrams.
5. Write a short note on Multicore Processor-Intel
6. Write a short note on AMD.
7. Compare RISC and CISC in detail.
8. What is Parallel processing? Write its advantages.
9. What is Flynn’s Taxonomy? Explain.
10. What is pipelining? Draw a space-time diagram for a six-segment pipeline showing the time
it takes to process eight tasks.
11. Consider an instruction pipeline with four stages with the stage delays 5 nsec, 6 nsec, 11
nsec, and 8 nsec respectively. The delay of an inter-stage register stage of the pipeline is 1
nsec. What is the approximate speedup of the pipeline in the steady state under ideal
conditions as compared to the corresponding non pipelined implementation?
12. What do you understand by inter-process communication in multiprocessor systems?
13. Prove that a K-stage pipeline Processor has speedup K-times over a K-stage processor
without pipelining.
14. What are the pipeline hazards? How do they affect the speedup.
15. Differentiate between Arithmetic and Instruction pipeline
16. Explain Array Processing and Vector Processing.
17. What is Multiprocessor?? Explain Inter process communication in detail.
